KR100451749B1 - Timing recovery apparatus in digital TV receiver - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock demodulation device for a digital TV receiver for receiving a signal transmitted by a VSB modulation scheme. In particular, the clock demodulator performs a clock demodulation after removing a residual phase error that is not completely removed from a carrier recovery unit using a nonlinear device. Thus, even when there is a residual phase error, stable clock demodulation is performed without being affected by the residual phase error. In addition, the clock is demodulated by converting the VSB I, Q signal from which the residual phase error has been eliminated to the OQAM I, Q signal, so that the accurate clock can be corrected even when the fs / 2 frequency portion that causes timing information due to ghost is greatly distorted. Demodulation can be performed, and by synchronizing the reset of the NCO2 and decimator to the first mask signal to make the VSB signal into an OQAM signal, the initial phase of the NCO and decimator is constant with respect to the system-wide reset during a system-wide reset. This will allow the clock demodulator to demodulate the clock at a more stable location.

Description

Clock demodulation device for digital TV receiver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital TV receiver, and more particularly, to a clock demodulation apparatus of a digital TV receiver that performs clock demodulation by converting a VSB (Offset Quadrature Amplitude Modulation) signal to an OQAM signal.

Currently, the ATSC (Advanced Television Systems Committee) method, which is adopted as a domestic and US digital TV (DTV) standard, transmits using a VSB modulation method. At this time, in the VSB transmission system, only data is transmitted in a transmission signal in order to increase frequency efficiency. That is, the receiver does not transmit information about the clock necessary for data recovery. Therefore, the receiving side should generate the same clock as used at the time of transmission to recover these data among the received signals in which only data exists. The part which plays this role is a clock demodulator.

FIG. 1 is a block diagram illustrating a typical digital TV receiver provided with such a clock demodulator, and illustrates a VSB transmission method as an example.

That is, when a RF (Radio Frequency) signal modulated by the VSB method is received through the antenna 101, the tuner 102 selects only a specific channel frequency desired by the user and then fixes the VSB signal of the RF band loaded on the channel frequency. Lower to the first intermediate frequency band and filter out other channel signals as appropriate.

The output signal of the tuner 102, which lowers the spectrum of an arbitrary channel to a fixed primary IF band, is adopted as a function of removing the adjacent channel signal, the high frequency component generated from the tuner 102, and the noise signal cancellation function. Surface Acoustic Wave (SAW) filter 103 is passed through.

At this time, the digital broadcast signal, for example, since all information is present in the band of 6 MHz from the intermediate frequency of 44 MHz, the SAW filter 103 removes all remaining sections except for the 6 MHz band in which the information exists from the output of the tuner 102. The output is then output to the down converter 104. Figure 2 shows the spectrum of the I-channel signal in the 6MHz band, the pilot signal is located at 8.69MHz when the center frequency of the signal is located at 6MHz.

The down converter 104 down-converts the signal filtered by the SAW filter 103 to an oscillation frequency for generating a second IF signal, converts the signal into a second IF signal, and then converts the analog / digital (A / D) converter. Output to (105).

The A / D converter 105 samples the analog output of the down converter 104 at a fixed frequency, that is, a constant clock of 25 MHz, and outputs it to the delay unit 106 and the Hilbert converter 107. In other words, while the transmitting side transmits data sampled at 21.52 MHz, which is twice the symbol frequency, the data output from the A / D converter 105 is digital data sampled at 25 MHz.

In this case, the Hilbert transformer 107 inverts the signal of the real component input by 90 degrees, converts the signal into an imaginary component signal, outputs the complex component to the complex multiplier 108, and the delay unit 106 outputs the Hilbert transformer. The signal of the real component input by the processing time at 107 is delayed and then output to the complex multiplier 108.

For convenience of description, the signal passed through the delay unit 106 is referred to as an I channel signal, and the signal passed through the Hilbert converter 107 is referred to as a Q channel signal.

The complex multiplier 108 receives feedback of a carrier from which carrier recovery is performed by the carrier recovery unit 109 and demodulates I, Q signals of a pass band output from the delay unit 106 and the Hilbert transformer 107 to pass through the pass band. After the I, Q signal of the baseband is lowered and output to the resampler (Resampler) (110) for conversion into a symbol recovered signal.

The carrier recovery unit 109 includes a frequency phase locked loop (FPLL) 109a, a loop filter 109b, and an NCO1 109c. The complex multiplier 108 may be included in the carrier recovery unit.

The FPLL 109a is a frequency locked loop (FLL) process that removes a frequency difference between a carrier component of a received signal and a reference carrier component of the receiver itself, and a PLL that removes a phase error between the two carrier signals from which the frequency difference is removed. (Phase Locked Loop) process is executed at the same time.

That is, the FPLL unit 109a detects the frequency offset and the phase error from the baseband pilot signal output from the complex multiplier 108 and outputs the frequency offset and phase error to the loop filter 109b.

The loop filter 109b filters and integrates the frequency offset and phase error and outputs the result to NCO1 109c. The NCO1 109c generates a complex sine wave proportional to the output of the loop filter 109b and outputs it to the complex multiplier 108.

Meanwhile, the resample unit 110 basically changes the sampling rate. That is, since the data sampled at 21.52 MHz and received are sampled at 25 MHz by the A / D converter 105, the resampler 110 samples the output at 21.52 MHz again.

To this end, the resample unit 110 offsets the baseband digital signal output through the A / D converter 105 and the complex multiplier 108 from the NCO2 113d of the clock demodulator 113. Interpolate and output the digital signal of 21.52MHz by using the value.

The output of the resample unit 110 is output to the matched filter 111, the matched filter 111 is a digital matched filter having the same roll-off value as the square root matched filter used in the transmission stage, the resample If the signal synchronously output from the unit 110 passes through the matched filter 111, the SNR at the symbol position is maximized.

The signal output from the matched filter 111 is added by the adder 112 so that only a real component signal is output for channel equalization and output to the clock demodulator 113.

The clock demodulator 113 includes a prefilter 113a, a timing error detector 113b, a loop filter 113c, and a numerically controlled oscillator NCO2 113d.

The prefilter 113a passes only the edge portion of the spectrum from which the timing information can be obtained from the real component signal output from the adder 112, and outputs the result to the timing error detector 113b. The timing error detector 113b may use, for example, a gardner method to detect a timing error value (ie, a compensation value for a timing offset) in various ways. The timing error value detected by the timing error detector 113b is output to the loop filter 113c, and the loop filter 113c filters only low-band signal components among the timing error values extracted by the timing error detector 113b. To NCO2 113d. The NCO2 113d continues to estimate the symbol clock from the low-band filtered timing error value to determine the current A / D sample (ie, data sampled at 25 MHz) and the actual symbol sample (ie, data sampled at 21.52 MHz). After calculating the time difference with and outputs the offset that is the difference value to the resample unit (110). In addition, the NCO2 113d generates a mask signal to remove a clock input to the resampler 110 through the A / D converter 105 when the offset value exceeds a preset reference value. Output to the resample unit 110. That is, the mask signal contains position information of the A / D samples to be removed due to the low sampling frequency of the output with respect to the input of the resample unit 110.

3 is a diagram illustrating an example of a resampling process of the resample unit 110 and illustrates a relationship between a 25 MHz clock and a 21.52 MHz clock.

Referring to FIG. 3, since the A / D converter 105 samples input data with a clock of 25 MHz, the A / D converter 105 outputs the resampled unit 110 through the A / D converter 105 and the complex multiplier 108. The data to be obtained is the data at the m _{k + n} clock positions. The data at the (k + n) Ti clock position is data sampled at 21.52 MHz, which is interpolated and output from the resample unit 110. U _k is an offset value output from NCO2 113d.

For example, assuming that m _k-1 and (k-1) Ti match, m _k and kTi have an offset of U _k . At this time, m _k data in the clock position is data known, because the data in the remote kTi clock position as U _k is unknown data, m _k to find out the data (the position spaced U _k from the (data that is already known) Data). If we assume that we are using an ideal filter, we can infer data at a time (i.e. kTi clock position) away from the known data (i.e. m _k ) by U _k . This is called interpolation.

However, when 25 MHz is converted to 21.52 MHz, the value of U _{k + n} exceeds a preset threshold. That is, the offset value is larger than the time difference value (eg, 1) between two neighboring A / D clocks.

In the case of U _{k + 4} of FIG. 3, at this time, data of the (k + 4) Ti clock position is not inferred from m _{k + 4} , but data of the (k + 4) Ti clock position is inferred from m _{k + 5} . do. To this end, the resample unit 110 needs a signal to mask data at the m _{k + 4} clock position. This mask signal is provided at NCO2 113d.

That is, when the NCO2 113d generates and outputs a mask signal at the m _{k + 4} clock position, the resample unit 110 does not infer the data of U _{k + 4 from} the data at the m _{k + 4} clock position. Inferred from the data of m _{k + 5} clock position, interpolated and output.

As such, the baseband signal output from the complex multiplier 108 is converted into a signal having a frequency of 21.52 MHz, which is twice the symbol frequency fs through the resample unit 110.

On the other hand, in the timing error detector 113b of the clock demodulator 113, the Gardner method uses a zero-crossing characteristic of data, and when viewed on the spectrum, the spectrum of two consecutive symbols overlaps. At this point you will have this information.

That is, the part where the spectrums of two consecutive symbols overlap is in the vicinity of the frequency fs / 2, and information necessary for obtaining timing error using the zero crossing characteristic of the data received in the Gardner method is located only here. Therefore, the clock demodulation unit 113 of FIG. 1 uses the pre-filter 113a, which is a band pass filter, to detect more accurate timing error in this part, that is, to obtain zero crossing information of the required signal.

However, such a digital TV system has a disadvantage in that its performance is remarkably degraded by the loss of information for obtaining timing errors when the fs / 2 frequency portion that brings timing information is greatly distorted.

In other words, by relying only on a certain frequency band for information on timing error, it can occur even if the band is lost by the ghost until the clock cannot be restored. Therefore, in such a situation, the clock demodulation algorithm of the digital TV receiver of FIG. 1 using the Gardner method not only degrades a lot of performance but also fails to recover an accurate clock, resulting in performance degradation of the entire system.

In addition, as shown in FIG. 2, when the signal located in the second IF 6MHz band passes through the carrier recovery unit 109 and the complex multiplier 108, the baseband VSB signal is generated. 109) contains residual phase errors that are not completely eliminated. Therefore, the clock demodulator 113 is affected by the residual phase error flowing in without being completely removed from the carrier recovery unit 109, which adversely affects the performance of the entire clock demodulator loop.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a clock demodulation device of a digital TV receiver which performs a clock demodulation after removing a residual phase error that is not completely removed from a carrier recovery unit using a nonlinear device. Is in.

Another object of the present invention is to perform clock demodulation by converting a baseband VSB signal into an Offset QAM (OQAM) signal, thereby performing accurate clock demodulation even when an fs / 2 frequency portion that obtains timing information by ghost is damaged. The present invention provides a clock demodulation device for a digital TV receiver.

It is still another object of the present invention to provide a digital TV receiver in which a clock demodulator recovers a clock at a stable position by always making a phase of a modulator without a feedback line formed in a process of converting a baseband VSB signal into an OQAM signal. The present invention provides a clock demodulation device.

1 is a block diagram of a general digital TV receiver

2 shows the spectrum of a passband I signal in the 6 MHz band.

3 is a diagram illustrating an example of resampling using an offset signal and a mask signal in the resampler of FIG. 1.

4 is a block diagram illustrating a digital TV receiver according to an embodiment of the present invention.

5 is a block diagram illustrating a digital TV receiver according to another embodiment of the present invention.

6 is a block diagram of a digital TV receiver of the present invention using a reset signal synchronized with a mask signal;

7 is a detailed block diagram of the reset unit of FIG. 6.

Explanation of symbols for main parts of the drawings

101: antenna 102: tuner

103: SAW filter 104: down converter

105: A / D converter 106,404: delay

107,405: Hilbert Converter 108,407: Complex Multiplier

109: carrier recovery unit 110,406: resample unit

400: clock demodulator 401,402,409,410: squarer

403: Adder 408,415: NCO

411: subtractor 412: bandpass filter

413 decimator 414 loop filter

The clock demodulation apparatus of the digital TV receiver according to the present invention for achieving the above object, after removing the residual phase error that is not completely removed in the carrier recovery unit using a nonlinear device, OQAM after removing the residual phase error It is characterized by converting into (Offset QAM) signal and performing clock demodulation. In particular, the reset signal synchronized with the first mask signal is used to reset the modulators without feedback lines (i.e., NCO and decimator to make the OQAM signal) in the process of turning the baseband VSB signal into an OQAM signal. have.

The digital TV receiver according to the present invention, which is implemented in hardware, receives a data transmitted by a VSB modulation scheme, samples the A / D clock, digitizes it, and then complex carriers generated through a carrier recovery process on a digitized passband VSB signal. Including a carrier recovery unit for multiplying into a baseband VSB signal, the clock demodulation unit is a residual phase error canceling unit that squares and adds the real and imaginary components of the VSB signal, respectively, and the VSB signal output from the residual phase error canceling unit. Is divided into signals of real component (I) and imaginary component (Q), and resampled by interpolating and outputting VSB I, Q signals divided by the phase divider using input offset and mask signals. And a VSB / OQAM converter for converting the VSB I, Q signals interpolated and output from the resampler into OQAM I, Q signals, and the OQAM I, Q signals. A timing error detection unit for detecting timing error information through band pass filtering and decimation after performing a type calculation; and a low band filtered timing error value after filtering only a low band signal component among the timing error information detected by the timing error detection unit A loop filter for estimating a symbol clock from the current A / D sample and calculating a time difference between the actual symbol sample, generating a mask signal indicating an offset signal and an A / D clock to be masked accordingly, and outputting the mask signal to the resampler And NCO.

The VSB signals squared by the residual phase error canceling unit may be real and imaginary components of the carrier-recovered baseband VSB signal.

The VSB signals squared by the residual phase error canceling unit may be real and imaginary components of the passband VSB I and Q signals before carrier recovery.

The VSB / OQAM conversion unit complex-multiplies the NCO generating a fixed oscillation frequency having a center frequency of 2.690559 MHz and the VSB I, Q signal output from the resampler at the output frequency of the NCO and converts it into an OQAM I, Q signal. It is characterized by consisting of a complex multiplier.

The timing error detector includes a squarer for squaring the OQAM I and Q signals converted by the VSB / OQAM converter, a subtractor for calculating a difference value between two squared signals output from the squarer, and an output frequency of the subtractor. And a decimator for decimating the output of the band pass filter and detecting timing error information.

And a reset unit generating a reset signal synchronized with the first mask signal generated by the loop filter and the NCO and providing the reset signal as a reset signal of the NCO of the VSB / OQAM converter and the decimator of the timing error detector.

The reset unit receives a system clock through a data input terminal, a mask signal generated by the loop filter and an NCO through an enable stage, and receives a clock that is not masked by a clock stage. The NCO and the timing of the VSB / OQAM converter And a D flip-flop for generating a reset signal of the decimator of the error detector.

A clock demodulation device for a digital TV receiver according to the present invention includes a residual phase error canceling unit that squares and adds a real component and an imaginary component of a baseband VSB signal, and a VSB signal output from the residual phase error canceler. A phase dividing unit for dividing I) and an imaginary component (Q) signal, a resampling unit for interpolating and outputting the VSB I, Q signals divided by the phase dividing unit using an input offset and a mask signal, and VSB / OQAM conversion that converts the VSB I, Q signal into OQAM I, Q signal by complex multiplying the VSB I, Q signal interpolated by the resampler and the fixed oscillation frequency having a center frequency of 2.690559 MHz output from the NCO. And a timing error detector for detecting timing error information through band pass filtering and decimation after performing nonlinear operation on the OQAM I and Q signals, and the other detected by the timing error detector. After filtering only the low-band signal components of the error information, the symbol clock is estimated from the low-band filtered timing error value to calculate the time difference between the current A / D sample and the actual symbol sample, and the offset signal and mask to be masked accordingly. A loop filter and an NCO for generating a mask signal indicating a / D clock and outputting the mask signal to the resampler, and a reset signal synchronized with the first mask signal generated by the loop filter and the NCO to generate a NCO and a NCO of the VSB / OQAM converter; And a reset unit for resetting the decimator for performing decimation of the timing error detection unit.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings illustrating the configuration and operation of the embodiment of the present invention, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, By the technical spirit of the present invention described above and its core configuration and operation is not limited.

FIG. 4 is a block diagram illustrating a digital TV receiver according to the present invention, except for the clock demodulator 400.

Therefore, the same reference numerals will be used for those having substantially the same configuration and function as the components in the above-described drawings in the embodiments of the present invention, and the parts necessary for understanding the operation according to the clock demodulation of the present invention. Only the description will be omitted, and descriptions of other parts will be omitted.

Referring to FIG. 4, the clock demodulator 400 includes first and second squarers 401 and 402, and first and second squarers that square the baseband VSB I and Q signals output from the complex multiplier 108, respectively. The adder 403, which removes the residual phase error that is not completely removed by the carrier recovery unit 109 by adding two signals output from 401 and 402, inverts the output of the adder 403 by 90 degrees and converts the signal into an imaginary component. The Hilbert transformer 405, the delayer 404 for delaying the output of the adder 403 by the processing time in the Hilbert transformer 405, the two outputs from the delayer 404 and the Hilbert transformer 405. Resample unit 406 for interpolating VSB I, Q signals VSB i (t) and VSB q (t) into 21.52 MHz digital signals using offset and mask signals, center frequency of 2.690559 MHz NCO 3 408, which generates a fixed oscillation frequency with A complex multiplier 407 and a complex multiplier 407 which demodulate the VSB I, Q signals output from the resample unit 406 and convert them into OQAM I, Q signals OQAM i (t) and OQAM q (t). A subtractor 411 for calculating a difference value between two outputs of the third and fourth squarers 409 and 410, and the third and fourth squarers 409 and 410, respectively. A band pass filter 412 for passing only a specific frequency band of the difference value output from 411, and a decimator for decimating the frequency component output from the band pass filter 412 to output timing error information ( 413), a loop filter 414 for filtering only low-band signal components among the timing error information output from the decimator 413, and a continuous symbol clock is estimated from the low-band filtered timing error value of the loop filter 414. Current A / D samples (ie, data sampled at 25 MHz) and actual symbol samples ( , Calculates a time difference between the data sampled at 21.52MHz) then consists of an offset to the difference value NCO2 (415) for outputting to said resampler (110, 406). In addition, when the offset value exceeds a preset reference value, the NCO2 415 may apply a mask signal to remove a clock input to the resampler 110 or 406 through the A / D converter 105. It generates and outputs to the resample unit (110, 406). That is, the mask signal contains position information of the A / D samples to be removed due to the low sampling frequency of the output with respect to the input of the resample units 110 and 406.

Here, the first, second squarers 401, 402, and the adder 403 correspond to a residual phase error remover that removes residual phase errors that are not removed by the carrier recovery unit 109, and a delayer 404. The Hilbert transformer 405 corresponds to a phase divider for dividing the signal from which the residual phase is removed into a real component and an imaginary component. In addition, the complex multiplier 407 and the NCO3 408 correspond to a VSB / OQAM converter for converting a VSB signal into an OQAM signal, and include a third and fourth squarers 409 and 410, a subtractor 411, and a band pass filter ( 412 and the decimator 413 correspond to a timing error detector.

In the present invention configured as described above, the baseband VSB I and Q signals output from the complex multiplier 108 are output to the resampler 110 through a delay and at the same time, the first and second squarers of the clock demodulator 400. Are output to 401 and 402, respectively. The first and second squarers 401 and 402 are nonlinear units, and the baseband VSB I and Q signals are squared and output to the adder 403, and the adder 403 adds two square signals to the delayer. 404 and the Hilbert transformer 405.

In this case, a signal obtained by squaring the VSB I and Q signals through the first and second squarers 401 and 402 and the adder 403, respectively, includes residual phase error components not completely removed by the carrier recovery unit 109. It is not. That is, even when the carrier recovery unit 109 fails to completely recover the carrier, the residual phase error is eliminated through the first and second squarers 401 and 402 and the adder 403, so that the delay unit 404 and Hilbert The signal output to the converter 405 does not include a residual phase error. This means that the timing error detection unit can operate independently of the residual phase error output from the carrier recovery unit 109, which also means that more stable clock demodulation can be performed.

Meanwhile, the VSB I and Q signals separated by the delay unit 404 and the Hilbert transformer 405 are output to the complex multiplier 407 via the resample unit 406. Since the operation of the resample unit 406 has been described in detail with reference to FIG. 1, detailed description thereof will be omitted.

The complex multiplier 407 has a fixed oscillation frequency having a VSB I, Q signal output from the resampler 406 at 21.52 MHz and a center frequency of 2.690559 MHz output from the NCO3 408. Multiply the baseband VSB I, Q signals by OQAM I, Q signals. That is, since the VSB I, Q signals are four times over-sampled by the first and second squarers 401 and 402, the clock demodulation is performed by converting the VSB I and Q signals into OQAM signals.

The OQAM I and Q signals (OQAM i (t) and OQAM q (t)) are each squared by the third and fourth squarers 409 and 410, which are nonlinear groups, and are then output to the subtractor 411 to obtain a difference value between the two square signals. Is computed. Instead of the squarers 409 and 410, a nonlinear group such as a quadratic square and an absolute value calculator may be used.

In this case, when the OQAM I, Q signals are squared in the third and fourth squarers 409 and 410, respectively, and a non-linear operation for calculating the difference between two square values is performed in the subtractor 411, symbol periods are included in the OQAM I and Q signals. In the T frequency portion, a tone including timing information is generated. This tone contains symbol frequency information for clock demodulation and the timing phase error of the received signal.

The tone generated in this manner is bandpass filtered by the bandpass filter 412 and decimated by a quadratic decimator 413 to detect a timing error value. The timing error value detected by the decimator 413 is output to the loop filter 414, and the loop filter 414 filters only the low band signal component among the timing error values output from the decimator 413 to NCO2. Output at 415. The NCO2 415 continuously estimates the symbol clock from the low-band filtered timing error value to determine the current A / D sample (ie, data sampled at 25 MHz) and the actual symbol sample (ie, data sampled at 21.52 MHz). After calculating the time difference of and outputs the offset that is the difference value to the resample unit (110,406). In this case, when the offset value exceeds a preset reference value, the NCO2 415 generates a mask signal to remove a clock input to the resamplers 110 and 406 through the A / D converter 105. Output to the resample unit (110,406). That is, the mask signal contains the position information of the A / D samples to be removed due to the low sampling frequency of the output with respect to the input of the resample unit (110,406), the resample unit (110,406) is the input of the mask signal If no A / D sample data is used for interpolation.

By configuring the clock demodulator by using the nonlinear device and the VSB / OQAM converter, the clock demodulator operates regardless of the residual phase error even though the carrier recovery unit does not completely remove the residual phase error. Further, even when the fs / 2 frequency portion is lost due to ghost or the like, accurate clock demodulation operation can be performed.

In one embodiment of the present invention, the baseband VSB I and Q signals are passed through the squarers 401 and 402 and the adder 403 to remove residual phase errors that the carrier recovery unit 109 cannot remove. For example, as shown in FIG. 5, the passband VSB I and Q signals may be passed through the squarers 401 and 402 and the adder 403 to remove residual phase errors that the carrier recovery unit 109 cannot remove. That is, when the VSB I and Q signals of the pass band are squared and added, carrier components including frequency and phase components are removed from the received signal, and thus the signals of the pass band may be used as they are.

4 and 5, the NCO3 408 for generating the OQAM signal has a center frequency of 2.690559 MHz, and as mentioned above, the carrier component is removed by squaring and adding the VSB I, Q signals. Use a fixed NCO with no feedback.

Thus, the NCO3 408 for generating the OQAM signal is not affected by a system-wide reset, which makes it impossible to adjust the initial phase value. In addition, if the multiplication decimator 413 also does not match the initial phase value, the clock demodulator 400 locks on both the correct sample and the two-sample delayed sample. That is, clock demodulation may be unstable when the initial phase of the NOC3 408 and the initial phase of the quadratic decimator 413 do not have a constant value for the reset of the entire system. In other words, when the initial phases of the NCO3 408 and the decimator 413 are not constant, the clocks have different locking points having a phase difference of 180 degrees.

In order to solve this problem, more stable clock demodulation can be performed by synchronizing initial phase values of the NCO3 408 and the decimator 413 to the mask signal generated by the NCO2 415. That is, the initial phase values of the NCO3 408 and the decimator 413 for generating the OQAM signal during the system-wide reset may have a constant phase value for the system-wide reset.

FIG. 6 is a block diagram illustrating a digital TV receiver of the present invention using a reset signal synchronized with the mask signal. The reset unit 500 is further added to FIGS. 4 and 5. The reset unit 500 receives a system reset signal, a mask signal, and an unmasked 25 MHz clock to reset the NCO3 408 and the decimator 413 to generate the OQAM signal. reset_n). That is, the NCO2 415 removes the corresponding A / D sample clock when the offset value is larger than the preset threshold, that is, does not use the A / D sample data to interpolate the sample data synchronized to 21.52 MHz. Generate a mask signal. In this case, the NCO2 415 receives rates of 25.0 MHz and 21.524476 MHz, and when reset, generates the first mask signal at a constant time for rates of 25.0 MHz and 21.524476 MHz regardless of clock demodulation.

Subsequently, as the clock is demodulated, the mask signal is generated according to the frequency offset and the phase offset of the clock demodulated signal.

Therefore, the reset unit 500 may have a constant initial phase by synchronizing the initial phases of the NCO2 408 and the decimator 413 to the first mask signal generated at a predetermined time after the system reset.

That is, since the first mask signal in the NCO2 415 is always generated after a predetermined time at the time of reset regardless of the clock demodulator, the reset unit 500 is the NCO2 408 and the decimator 413 to make the OQAM signal. By synchronizing the reset to the first mask signal, the NCO2 408 and decimator 413 for generating the OQAM signal at a constant time upon system reset have a constant initial phase.

In FIG. 6, the remaining blocks except for the NCO2 408 and the decimator 413, that is, the resample unit 406, the subtractor 411, the band pass filter 412, and the loop filter 414 are system reset signals. Is reset.

FIG. 7 is a detailed configuration diagram of the reset unit 500 and illustrates a D flip-flop as an example. Referring to FIG. 7, the system reset signal is input to the data input terminal d, the unmasked 25 MHz clock is input to the clock terminal, and the mask signal is input to the enable terminal. That is, the D flip-flop is enabled by the mask signal, and then outputs a system reset signal input to the D input terminal at the rising edge of the 25 MHz clock as a reset signal of the NCO2 408 and the decimator 413. Therefore, when the system is reset, the reset signal synchronized with the mask signal is output to the NCO2 408 and the decimator 413, which causes the NCO2 408 and the decimator 413 to have a constant initial phase. do.

As described above, according to the clock demodulation apparatus of the digital TV receiver according to the present invention, a residual phase error exists by performing a clock demodulation after removing a residual phase error that is not completely removed by a carrier recovery unit using a nonlinear device in a clock demodulator. Even if the clock demodulator is operated without being affected by the residual phase error, more stable clock demodulation is achieved.

In addition, the clock is demodulated by converting the VSB I, Q signal from which the residual phase error has been eliminated to the OQAM I, Q signal, so that the accurate clock can be corrected even when the fs / 2 frequency portion that causes timing information due to ghost is greatly distorted. Demodulation can be performed to improve the performance of the system as well as the performance of the clock demodulation algorithm.

By synchronizing the reset of the NCO2 and the decimator to the first mask signal to make the VSB signal into the OQAM signal, the initial phase value of the NCO and the decimator has a constant phase value for the system-wide reset during a system-wide reset. The demodulator can demodulate the clock at a more stable position.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (11)

Receives data transmitted by the residual sideband (VSB) modulation method, digitizes it by sampling the A / D clock, and multiplies the digitized passband VSB signal by the complex carrier generated by the carrier recovery process to convert the baseband VSB signal. In the clock demodulation device of the digital TV receiver provided with a carrier recovery unit, A residual phase error removal unit configured to add the squared real and imaginary components of the VSB signal, respectively; A phase dividing unit dividing the VSB signal output from the residual phase error removing unit into signals of a real component (I) and an imaginary component (Q); A resampler for interpolating and outputting the VSB I and Q signals divided by the phase divider using an offset and a mask signal input thereto; A VSB / OQAM conversion unit converting the VSB I, Q signals interpolated and output from the resampler into OQAM I, Q signals; A timing error detector which detects the timing error information through band pass filtering and decimation after performing the non-linear operation on the OQAM I and Q signals; And After filtering only the low-band signal components among the timing error information detected by the timing error detector, the symbol clock is estimated from the low-band filtered timing error value to calculate a time difference between the current A / D sample and the actual symbol sample. And a loop filter and an NCO for generating an offset signal and a mask signal indicating an A / D clock to be masked and outputting the mask signal to the resample unit. The method of claim 1, And a VSB signal each squared by the residual phase error canceling unit is a real component and an imaginary component of a carrier-recovered baseband VSB signal. The method of claim 1, And a VSB signal squared by the residual phase error canceling unit is a real component and an imaginary component of a passband VSB I, Q signal before carrier recovery. The method of claim 1, wherein the VSB / OQAM conversion unit An NCO generating a fixed oscillation frequency having a center frequency of 2.690559 MHz, And a complex multiplier for complex multiplying the VSB I, Q signals output from the resampler to the OQAM I, Q signals at the output frequency of the NCO. The method of claim 1, wherein the timing error detector A square unit that squares the OQAM I and Q signals converted by the VSB / OQAM converter, respectively; A subtractor for calculating a difference value between two square signals output from the square unit; A bandpass filter for passing only a specific band among the output frequencies of the subtractor, And a decimator for decimating the output of the band pass filter to detect timing error information. The method of claim 1, And a reset unit generating a reset signal synchronized with the first mask signal generated by the loop filter and the NCO and providing the reset signal as a reset signal of the NCO of the VSB / OQAM converter and the decimator of the timing error detector. Clock demodulation device for TV receivers. The method of claim 6, wherein the reset unit A system clock is input to a data input terminal, a mask signal generated from the loop filter and an NCO is input to an enable terminal, and a clock that is not masked to a clock terminal is input to the NCO of the VSB / OQAM converter and the timing error detector. A clock demodulation device for a digital TV receiver, characterized in that it comprises a D flip-flop for generating a reset signal of the decimator. 8. The apparatus of claim 7, wherein the unmasked clock input to the clock stage of the D flip-flop is 25 MHz. Receives data transmitted by the residual sideband (VSB) modulation method, digitizes it by sampling the A / D clock, and multiplies the digitized passband VSB signal by the complex carrier generated by the carrier recovery process to convert the baseband VSB signal. In the clock demodulation device of the digital TV receiver provided with a carrier recovery unit, A residual phase error canceling unit configured to add the squared real and imaginary components of the baseband VSB signal, respectively; A phase dividing unit dividing the VSB signal output from the residual phase error removing unit into signals of a real component (I) and an imaginary component (Q); A resampler for interpolating and outputting the VSB I and Q signals divided by the phase divider using an offset and a mask signal input thereto; VSB / OQAM converting the VSB I, Q signal into OQAM I, Q signal by complex multiplying the VSB I, Q signal interpolated by the resampler to a fixed oscillation frequency having a center frequency of 2.690559 MHz output from the NCO A conversion unit; A timing error detector which detects the timing error information through band pass filtering and decimation after performing the non-linear operation on the OQAM I and Q signals; After filtering only the low-band signal components among the timing error information detected by the timing error detector, the symbol clock is estimated from the low-band filtered timing error value to calculate a time difference between the current A / D sample and the actual symbol sample. A loop filter and an NCO for generating a mask signal indicating an offset signal and an A / D clock to be masked and outputting the mask signal to the resampler; And And a reset unit generating a reset signal synchronized with the first mask signal generated by the loop filter and the NCO, and resetting the decimator performing decimation of the NCO of the VSB / OQAM converter and the timing error detector. Clock demodulation device for digital TV receiver. The method of claim 9, wherein the residual phase error removing unit And a real component and an imaginary component of the passband VSB signal squared and added, respectively. The method of claim 9, wherein the reset unit A system clock is input to a data input terminal, a mask signal generated from the loop filter and an NCO is input to an enable terminal, and a 25MHz clock that is not masked to a clock terminal is input to the NCO of the VSB / OQAM converter and the timing error detector. Clock demodulation device for a digital TV receiver, characterized in that consisting of a D flip-flop for generating a reset signal of the decimator.