KR100448071B1 - Apparatus for controlling buffer memory in computer system - Google Patents

Abstract

The present invention relates to a buffer memory controller of a computer system, and more particularly, to an internal buffer memory according to the current data flow and the number of entries in a queue in a queue system used as a buffer connecting two components that generate and consume data. By partially activating and adaptively applying a bank of s, an efficient and low-power buffer system can be implemented, as well as the internal memory can be used as a scratch pad memory to increase the efficiency of the memory.

Description

Buffer memory controller of computer system {APPARATUS FOR CONTROLLING BUFFER MEMORY IN COMPUTER SYSTEM}

The present invention relates to a buffer memory controller of a computer system, and more particularly, to an internal buffer memory according to the current data flow and the number of entries in a queue in a queue system used as a buffer connecting two components that generate and consume data. The present invention relates to a buffer memory control device of a computer system that partially activates and adaptively applies a bank of to enable an efficient and low-power buffer system as well as use internal memory as a scratch pad memory.

As the demand for an embedded system consisting of a main processor and several functional components increases, there is a need for a method of efficiently buffering data between the processor and the I / O components.

In general, a buffering method uses a queue. The queue uses a first-in-first out (FIFO) in the form of a circular queue, and the processor uses an interrupt to store and read data.

Processors are generally slower than components that consume data, so the value of the status register, which represents the number of additional queues of data, can be made larger by using appropriate predictions, or by interrupts caused by overflows. In order to reduce the cost, the method of using extra memory space other than the buffer is mainly used, and there is a problem of increasing the power consumption for driving the memory as well as the problem of securing the extra memory space.

The present invention was created to solve the above problems, and an object of the present invention is to internalize the current data according to the flow of data and the number of entries in a queue in a queue system used as a buffer connecting two components that generate and consume data. The present invention provides a buffer memory controller of a computer system in which a bank of buffer memories is partially activated and adaptively applied to implement an efficient and low power buffer system as well as an internal memory as a scratch pad memory.

1 is a block diagram showing a buffer memory control apparatus of a computer system according to the present invention.

FIG. 2 is a conceptual diagram illustrating a method of providing a bank activation signal in an internal memory having a multi-bank type in the form of a circular queue by a bank controller in a buffer memory controller of a computer system according to the present invention.

-Explanation of symbols for the main parts of the drawings-

10 processor 20 buffer memory

30 Component 40: Output Latch

50: buffer controller 60: bank controller

The present invention for realizing the above object is to control the output latch to operate as a virtual queue and the data input and output to the buffer memory when transferring the data stored in the buffer memory to the consuming component or using the buffer memory as a scratch pad memory, Delay the operation of the processor or component in the event of overflow or underflow of the buffer memory, determine the active point according to the number of internal entries of the buffer memory and the number of required banks, and generate control signals to use the buffer memory as the scratch pad memory And a bank controller for partially activating a bank of the buffer memory in a circular cue form by an active point of the buffer controller.

Above, the operation delay time during overflow or underflow in the buffer controller is until the active point is reduced or increased.

In addition, the active point is characterized by indicating the usage of the queue expected in the current operating state.

In addition, the active point is reduced when an overflow occurs, and is increased when an underflow occurs.

The present invention thus achieved delays until an active point occurs when an overflow or underflow of the buffer memory occurs, and partially activates the buffer memory in the form of a circular queue according to the active point, thereby adaptively adapting to the number of data actually used. In addition to reducing power consumption by enabling, the internal buffer memory is used as scratch pad memory for direct access by the processor.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, this embodiment is not intended to limit the scope of the present invention, but is presented by way of example only.

1 is a block diagram showing an internal buffer memory control apparatus according to the present invention.

As shown here, when the data stored in the buffer memory 20 is transferred to the consuming component 30 or the buffer memory 20 is used as the scratch pad memory, the output latch 40 acting as a virtual queue and the buffer memory ( 20) to control the input and output of data, to delay the operation of the processor 10 or the component 30 in the event of overflow or underflow of the buffer memory 20, the number of internal entries of the buffer memory 20 and the required bank A buffer controller 50 which determines the active point Act_point according to the number and separates the output latch 40 to use the buffer memory 20 as the scratch pad memory, and an active point Act_point of the buffer controller 50. By the bank controller 60 which partially activates the bank of the buffer memory 20 in a circular cue format.

Therefore, when data (Data) is output from the main processor 10, the buffer controller 50 generates a rear address and stores the data in the buffer memory 20, and the current state of the status register Increase the number of entries Then, the component consuming the data 30 outputs the data stored in the buffer memory 20 by the front address together with the control signal from the buffer controller 50 through the output latch 40 to the desired bandwidth. According to the output.

At this time, the active point Act_point is an amount representing the capacity of the queue currently needed in the capacity of the entire buffer memory, and the bank controller 50 uses this value to activate the necessary bank in the buffer memory 20.

In addition, the buffer controller 50 generates a control signal that the main processor 10 can directly access the internal buffer memory 20 for the scratch pad memory, and separates the output latch 40 from the queue.

The operation of the buffer memory controller of the computer system according to the present invention will be described as follows.

First, it is an active point processed by the buffer controller 50.

The active point Act_point refers to the usage of the queue expected in the current operating state, that is, the working set. Therefore, it is different from the number of entries currently stored in the queue, and it means the expected queue usage among the total queue capacity. Therefore, if the active point is small, sufficient buffering is possible without using all of the internal buffer memory 20.

If the main processor 10 is fast and the queue overflows, the main processor 10 receives an interrupt IRQ and the active point decreases. This is because the component 30 that consumes data actually uses fewer data. Conversely, when the cue becomes empty, the active point is increased.

Secondly, in the buffer controller 50, when the queue overflows or unflows, an interrupt (IRQ) is interrupted to the main processor 10 or the other component 30 is held.

If an interrupt (IRQ) occurs because the queue is full, the main processor 10 enters the hold state and the hold state continues when the number of entries in the current queue decreases to the active point. In this case, when the queue is full and an overflow occurs, an interrupt (IRQ) is generated and the hold state until the active point decreases is compared with only when the queue is full. This is because interrupt (IRQ) occurs repeatedly and power consumption increases.

Similarly, if an underflow occurs because the queue is empty, the component 30 that consumes data is held, and the hold state continues until the number of entries in the queue increases to the active point.

When overflow or underflow occurs in this way, the component 30 which processes data in terms of power consumption actually repeats the operation with HOLD for a short time, rather than causing the internal bus to transition. This is because it is advantageous to operate and hold a longer time.

Thirdly, according to the active point, this part makes a signal for activating the bank to be used.

If the active point changes to a specific value and requires more space in the buffer memory 20 or less space in the buffer memory 20, the bank of the buffer memory 20 including a plurality of banks is partially divided. Will be activated. That is, the bank controller 60 additionally activates or deactivates the bank as if the data is added like a circular queue in the currently active bank.

You will usually allocate a bank to store enough entries between 1.5 and 2.5 times the active point. A method of allocating banks will be described with reference to the conceptual diagram of FIG. 2.

First, if Bank 0 and Bank 1 are currently active as in the case of (a), and if additional banks are needed, the second bank (Bank 2) is like a cue of four entries. Activate it. Therefore, as in the case of (b), the next rear point is not in the bank 0, as in (a), but in the second bank (Bank 2). If (b) attempts to activate fewer banks, bank 0 is deactivated as data is deleted from the queue. Therefore, the next rear point is in the first bank (Bank 1), not the bank 0 (Bank 0).

This activates only the banks you actually use, reducing power consumption.

Fourth, the main processor 10 directly provides a memory control signal to use the internal buffer memory 20 as the scratch pad memory.

In this case, the internal buffer memory 20 does not operate as a queue, but operates as a kind of static cache. And all banks are activated. In this state, the output latch 40 is disconnected from the internal buffer memory 20.

That is, when the buffer memory 20 operates as a queue, the data is read by the potential address generated by the buffer controller 50 such that the path of the data is 'B' and transferred to the component 30 through the output latch 40. However, when used as a scratch pad memory, since the main memory 10 controls the buffer memory 20 directly, the data path is transferred directly to the main processor 10 as shown in 'A'.

Therefore, when the hardware acceleration component 30 is not used in a portable terminal such as a personal digital assistant (PDA), the internal buffer memory used as a buffer can be used as a static cache, thereby allowing a non-cachable area on the system. Will have Modern handheld devices have an external DRAM interface with a cache inside, so static caching can be especially beneficial for applications that frequently use certain constants, such as digital signal processors (DSPs).

Fifth, the output latch 40 acts as a virtual queue.

The output latch 40 is connected to the internal buffer memory 20 when the internal buffer memory 20 operates as a queue, and is directly connected to the buffer controller 50 in the scratch pad memory state.

Therefore, when a queue access instruction occurs in the scratch pad memory state, the output latch 40 behaves like a virtual queue having one entry, and has the same software code as the scratch pad memory, the main processor 10, and other components 30. The interface function to connect the slow speed but all will be available.

As described above, the present invention adjusts the active point of the queue during the overflow or underflow of the buffer between the main processor and the consuming component to produce data, thereby activating internal memory as much as the entry of the queue to be used. There is an advantage to reduce.

In addition, the active point can be adaptively adjusted according to the data processing speed of the component that consumes and produces, thereby reducing the cost of interruption of the main processor.

In addition, since the main processor may use the internal buffer memory used as a buffer as the scratch pad memory, there is an advantage of increasing the memory usage efficiency.

Claims (6)

An output latch that acts as a virtual queue when passing data stored in the buffer memory to a consuming component or using an internal buffer as the scratch pad memory; Control the input and output of the buffer memory, delay the operation of the processor or component in the event of overflow or underflow of the buffer memory, determine the active point according to the number of internal entries of the buffer memory and the number of required banks and scratch the buffer memory. A buffer controller that separates the output latch for use as pad memory, A bank controller that partially activates a bank of buffer memories in circular cue form by the active point of the buffer controller. Buffer memory control device of a computer system, characterized in that consisting of. 2. The buffer memory controller of claim 1, wherein an operation delay time when an overflow occurs in the buffer controller is delayed until the number of entries decreases to an active point. The apparatus of claim 1, wherein an operation delay time when an underflow occurs in the buffer controller is delayed until the number of entries increases to an active point. 2. The buffer memory controller of claim 1, wherein the active point represents a usage of a queue expected in a current operating state. 2. The buffer memory controller of claim 1, wherein the active point decreases upon overflow. The apparatus of claim 1, wherein the active point increases when an underflow occurs.