KR100442495B1 - Internal step-down circuit, especially rapidly responding the internal voltage - Google Patents

Internal step-down circuit, especially rapidly responding the internal voltage Download PDF

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Publication number
KR100442495B1
KR100442495B1 KR1019960038387A KR19960038387A KR100442495B1 KR 100442495 B1 KR100442495 B1 KR 100442495B1 KR 1019960038387 A KR1019960038387 A KR 1019960038387A KR 19960038387 A KR19960038387 A KR 19960038387A KR 100442495 B1 KR100442495 B1 KR 100442495B1
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voltage
internal
internal voltage
pmos transistor
int
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KR1019960038387A
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KR19980020048A (en
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강동금
송승희
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주식회사 하이닉스반도체
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/59—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Dram (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

PURPOSE: An internal step-down circuit is provided to maintain a stable internal voltage by rapidly responding the internal voltage changed by the load in the dual power operating device. CONSTITUTION: An internal step-down circuit includes a comparator(10) and a plurality of PMOS transistors(Q11,Q12,Q13). The comparator compares the internal voltage(Vint) with the reference voltage(Vref). The PMOS transistor(Q11) controls the current of load by the output signal of the comparator. The PMOS transistor(Q13) discharges the internal voltage when the internal voltage is larger than the reference voltage. The source of the PMOS transistor(Q12) receives the internal voltage and outputs the voltage lowering by the threshold voltage through the source and the drain/ And, the lowered voltage is applied to the gate of the PMOS transistor(Q12).

Description

내부강압 회로Internal step-down circuit

본 발명은 내부강압 회로에 관한 것으로, 특히 이중전원으로 동작하는 디바이스에 있어서 부하에 의해 변동되는 내부전압에 대해 빠르게 응답함으로써 안정된 내부전압을 유지할 수 있도록 한 내부강압 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal voltage step-down circuit, and more particularly to an internal voltage step-down circuit capable of maintaining a stable internal voltage by rapidly responding to an internal voltage fluctuated by a load in a device operated by a double power source.

최근 디바이스의 미세화와 함께 동반되는 디바이스의 내압저하는 심각한 문제로 대두되고 있다.BACKGROUND ART [0002] In recent years, miniaturization of devices has accompanied a serious problem of lowering the breakdown voltage of devices.

따라서, 16메가급 디램에서는 이중전원 방식을 채택하여 사용하고 있다. 즉, 외부의 인터페이스 전원과 연결되는 외부전원을 디바이스내의 강압회로를 사용하여 디바이스 내압이 고려된 내부전원을 만들어 사용하고 있다.Therefore, the 16-megapixel DRAM uses a dual power supply. That is, an external power source connected to an external interface power source is formed by using a step-down circuit in the device to generate an internal power source in consideration of the device internal pressure.

종래의 내부강압 회로는 도1에 도시한 바와 같이, 내부전압(VINT)과 기준전압(VREF)을 비교하여 출력하는 비교기(1)와, 상기 비교기(1)의 출력신호에 의해 부하의 전류를 조절하여 공급하는 피모스 트랜지스터(Q1)로 구성되는데, 이와같은 종래 내부강압 회로의 동작에 대해 설명한다.As shown in FIG. 1, the conventional internal voltage step-down circuit includes a comparator 1 for comparing an internal voltage V INT with a reference voltage V REF and outputting the comparison result, And a PMOS transistor Q1 for regulating and supplying a current. The operation of such a conventional internal voltage-drop circuit will be described.

먼저, 내부전압(VINT)으로 구동되는 부하에 의해 과도한 부하전류(IL)가 흐르게 되어 내부전압(VIL)이 기준전압(VREF) 보다 작을 경우에는, 비교기(1)에서 저전위신호가 출력되고, 이에따라 피모스 트랜지스터(Q1)가 턴온되어 부하에 전류를 공급하여 내부전압(VINT)을 기준전압(VREF)에 근사하도록 유지한다.First, when the excessive load current I L flows due to the load driven by the internal voltage V INT and the internal voltage V IL is smaller than the reference voltage V REF , the comparator 1 outputs the low potential signal The PMOS transistor Q1 is turned on to supply a current to the load so as to keep the internal voltage V INT close to the reference voltage V REF .

한편, 기준전압(VREF) 보다 내부전압(VINT)이 클 경우에는, 피모스 트랜지스터(Q1)가 턴오프 되어 부하에 전류 공급을 중지하게 된다.On the other hand, when the internal voltage V INT is larger than the reference voltage V REF , the PMOS transistor Q1 is turned off to stop supplying the current to the load.

그러나, 상기와 같은 종래의 기술에 있어서 기준전압(VREF) 보다 내부전압(VINT)이 클 경우에는, 피모스 트랜지스터(Q1)가 턴오프 되어 부하에 전류 공급이 중지되고 내부회로의 방전에 의해서 내부전압(VINT)값을 유지하게 되므로, 안정된 내부전압(VINT)의 유지를 내부회로의 방전에만 의지해야 하는 문제가 있었다.However, when the internal voltage (V INT ) is larger than the reference voltage (V REF ) in the related art as described above, the PMOS transistor (Q1) is turned off to stop the current supply to the load, The internal voltage V INT is maintained, and therefore, there is a problem that the maintenance of the stable internal voltage V INT must be dependent on the discharge of the internal circuit.

본 발명은 상기와 같은 종래의 문제를 해결하기 위하여 창안된 것으로, 내부전압(VINT)이 기준전압(VREF) 보다 클 경우 이를 방전시키기 위한 피모스 트랜지스터와, 이 피모스 트랜지스터의 방전 개시를 위해 게이트 전압의 레벨을 조정하는 피모스 트랜지스터를 도입함으로써, 과도한 부하전류의 변동에 대해 빠른 응답속도를 지니게 하여 안정된 내부전압(VINT)을 유지할 수 있도록 한 내부강압 회로를 제공함에 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned conventional problems, and it is an object of the present invention to provide a PMOS transistor for discharging the PMOS transistor when the internal voltage V INT is larger than the reference voltage V REF , The present invention has an object to provide an internal voltage step-down circuit capable of maintaining a stable internal voltage (V INT ) with a rapid response speed to fluctuations of an excessive load current by introducing a PMOS transistor for adjusting the level of a gate voltage .

도1은 종래 내부강압 회로도.1 is a circuit diagram of a conventional internal voltage step-down circuit.

도2는 본 발명 내부강압 회로도.2 is a circuit diagram depicting the internal pressure of the present invention.

도3은 도1 및 도2의 시뮬레이션 결과특성도.Fig. 3 is a characteristic diagram of simulation results of Figs. 1 and 2; Fig.

*** 도면의 주요 부분에 대한 부호의 설명 ***DESCRIPTION OF THE REFERENCE SYMBOLS

10:비교기 20:방전부10: comparator 20: discharge unit

Q11～Q13:피모스 트랜지스터 IL:부하전류Q11 to Q13: PMOS transistor I L : Load current

CL:부하용량C L : Load capacity

상기와 같은 목적을 달성하기 위한 본 발명 내부강압 회로는 도2에 도시한 바와 같이, 내부전압(VINT)과 기준전압(VREF)을 비교하여 출력하는 비교기(10)와, 상기 비교기(10)의 출력신호에 의해 부하의 전류를 조절하여 공급하는 피모스 트랜지스터(Q11)와, 내부전압(VINT)이 기준전압(VREF) 보다 클 경우 높은 내부전압(VINT)을 방전시켜 기준전압(VREF)값에 근사시키는 방전부(20)로 구성된다.2, the internal down-converter includes a comparator 10 for comparing an internal voltage V INT with a reference voltage V REF and outputting the comparison result, ) when the PMOS transistor (Q11) for supplying a regulated current of the load by the output signal, the internal voltage (V INT) is greater than the reference voltage (V REF) by discharging a high internal voltage (V INT) voltage references of (V REF ).

또한, 상기 방전부(20)는 기준전압(VREF)에 접속되는 피모스 트랜지스터(Q12)와, 내부전압(VINT)에 접속되며 그 게이트가 상기 피모스 트랜지스터(Q12)의 게이트 및 드레인에 공통 접속되는 피모스 트랜지스터(Q13)로 구성된다.The discharging unit 20 includes a PMOS transistor Q12 connected to the reference voltage V REF and a PMOS transistor Q12 connected to the internal voltage V INT and having a gate connected to the gate and drain of the PMOS transistor Q12 And a PMOS transistor Q13 connected in common.

이와같이 구성한 본 발명의 동작 및 효과에 대해 좀 더 상세히 설명하면 다음과 같다.Hereinafter, the operation and effect of the present invention will be described in more detail.

먼저, 내부전압(VINT)으로 구동되는 부하에 의해 과도한 부하전류(IL)가 흐르게 되어 내부전압(VIL)이 기준전압(VREF) 보다 작을 경우에는, 종래와 동일하게 비교기(10)에서 저전위 신호가 출력되고, 이에따라 피모스 트랜지스터(Q11)가 턴온되어 부하에 전류를 공급하여 내부전압(VINT)을 기준전압(VREF)에 근사하도록 유지시킨다.When an excessive load current I L flows due to a load driven by the internal voltage V INT and the internal voltage V IL is lower than the reference voltage V REF , The PMOS transistor Q11 is turned on to supply a current to the load to keep the internal voltage V INT close to the reference voltage V REF .

한편, 내부전압(VINT)이 기준전압(VREF) 보다 클 경우에는, 피모스 트랜지스터(Q11)가 턴오프 되어 내부회로에 전류를 공급하지 않게 되고 방전부(20)에 의해 내부전압(VINT)을 방전시킴으로써 내부전압(VINT)의 변동에 빠르게 응답하게 된다.On the other hand, when the internal voltage V INT is larger than the reference voltage V REF , the PMOS transistor Q11 is turned off and no current is supplied to the internal circuit, and the internal voltage V INT ) in response to the variation of the internal voltage V INT .

즉, 방전개시를 위한 디바이스 즉, 피모스 트랜지스터(Q13)의 게이트 전압 레벨(노드A)이 문턱전압 만큼 클 경우에 온되어 방전될 수 있다.That is, when the device for starting discharge, that is, the gate voltage level (node A) of the PMOS transistor Q13 is as large as the threshold voltage, it can be turned on and discharged.

이때, 게이트 전압 레벨(노드A)은 기준전압(VREF)-피모스 트랜지스터(Q12)의 문턱전압(VTP)이므로 내부전압(VINT)값이 피모스 트랜지스터(Q13)의 게이트 전압 레벨(노드A) 보다 피모스 트랜지스터(Q13)의 문턱전압 만큼만 높으면 피모스 트랜지스터(Q13)가 턴온되고, 이에따라 높은 내부전압(VINT)이 종래에 비해 더 빠르게 방전되어 기준전압(VREF)값에 근사하게 된다.Since the gate voltage level (node A) is the threshold voltage (V TP ) of the reference voltage (V REF ) - the PMOS transistor Q12, the value of the internal voltage (V INT ) high, node a) than as much as the threshold voltage of the PMOS transistor (Q13) PMOS transistor (Q13) is turned on, yiettara high internal voltage (V INT) is more quickly discharged compared with the conventional approximate the value reference voltage (V REF) .

이와같은 본 발명의 시뮬레이션(Simulation) 결과를 종래와 비교하여 나타낸 도3에서와 같이, 본 발명에 의해서 내부전압(VINT)이 안정적으로 유지됨을 알 수 있다.As shown in FIG. 3, which is a comparison of the simulation result of the present invention with the conventional one, it can be seen that the internal voltage V INT is stably maintained by the present invention.

상술한 바와 같이, 본 발명은 이중전원으로 동작하는 디바이스에 있어서 부하에 의해 변동되는 내부전압에 대해 빠르게 응답함으로써 안정된 내부전압을 유지시킬 수 있는 효과가 있다.As described above, according to the present invention, a stable internal voltage can be maintained by rapidly responding to an internal voltage fluctuated by a load in a device operated by a dual power source.

또한, 내부전압(VINT)이 기준전압(VREF) 보다 클 경우 피모스 트랜지스터를 통해 빠르게 검출하고 방전하여 내부전압(VINT)의 레벨을 낮출 수 있으므로 저전력화를 이룰 수 있는 효과가 있다.Further, when the internal voltage V INT is higher than the reference voltage V REF , the level of the internal voltage V INT can be lowered by rapidly detecting and discharging the current through the PMOS transistor, thereby achieving low power consumption.

Claims (1)

내부전압(VINT)과 기준전압(VREF)을 비교하여 출력하는 비교기와, 상기 비교기의 출력신호에 의해 부하의 전류를 조절하여 공급하는 피모스 트랜지스터(Q11)와, 상기 내부전압(VINT)이 상기 기준전압(VREF) 보다 클 경우 그 내부전압(VINT)을 방전시키기 위한 피모스 트랜지스터(Q13)와, 상기 내부전압(VREF)을 소스에 인가받고 그의 문턱전압만큼 낮아진 전압을 소스 및 드레인의 공통접속점을 통해 출력하여 상기 피모스 트랜지스터(Q13)의 게이트에 인가하는 피모스 트랜지스터(Q12)로 구성하여 된 것을 특징으로 하는 내부강압 회로.And a comparator for outputting by comparing the internal voltage (V INT) with a reference voltage (V REF), and controlling the current of the load by the output signal to supply PMOS transistor (Q11) to the said comparator, the internal voltage (V INT ) is the lower voltage of the reference voltage (if higher than V REF) that the PMOS transistor (Q13) for discharging the internal voltage (V INT), being applied to the internal voltage (V REF) to the source as its threshold voltage And a PMOS transistor (Q12) which outputs the signal through a common connection point of a source and a drain and applies it to the gate of the PMOS transistor (Q13).
KR1019960038387A 1996-09-05 1996-09-05 Internal step-down circuit, especially rapidly responding the internal voltage KR100442495B1 (en)

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KR100723474B1 (en) * 2001-12-31 2007-05-30 삼성전자주식회사 Current mode comparator having hysteresis voltage

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0621377A (en) * 1992-07-02 1994-01-28 Mitsubishi Electric Corp Semiconductor storage device
KR940003535A (en) * 1992-08-28 1994-03-12 최근선 Disposable absorbent products
KR950024210A (en) * 1994-01-13 1995-08-21 김광호 Internal power supply voltage generation circuit of semiconductor memory device and method thereof
JPH0962390A (en) * 1995-08-30 1997-03-07 Toshiba Corp Semiconductor device
JPH1027027A (en) * 1996-07-09 1998-01-27 Mitsubishi Electric Corp Internal voltage dropping circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0621377A (en) * 1992-07-02 1994-01-28 Mitsubishi Electric Corp Semiconductor storage device
KR940003535A (en) * 1992-08-28 1994-03-12 최근선 Disposable absorbent products
KR950024210A (en) * 1994-01-13 1995-08-21 김광호 Internal power supply voltage generation circuit of semiconductor memory device and method thereof
JPH0962390A (en) * 1995-08-30 1997-03-07 Toshiba Corp Semiconductor device
JPH1027027A (en) * 1996-07-09 1998-01-27 Mitsubishi Electric Corp Internal voltage dropping circuit

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