KR100442145B1 - Method for improvement silicide by using argon, germanium, arsenic gas - Google Patents
Method for improvement silicide by using argon, germanium, arsenic gas Download PDFInfo
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- KR100442145B1 KR100442145B1 KR10-2001-0085764A KR20010085764A KR100442145B1 KR 100442145 B1 KR100442145 B1 KR 100442145B1 KR 20010085764 A KR20010085764 A KR 20010085764A KR 100442145 B1 KR100442145 B1 KR 100442145B1
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- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 74
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 70
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 38
- 229910052785 arsenic Inorganic materials 0.000 title claims abstract description 37
- 239000007789 gas Substances 0.000 title claims abstract description 30
- 229910052786 argon Inorganic materials 0.000 title claims abstract description 24
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 title claims abstract description 24
- 229910052732 germanium Inorganic materials 0.000 title claims abstract description 22
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 83
- 239000002184 metal Substances 0.000 claims abstract description 83
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 21
- -1 spacer nitride Chemical class 0.000 claims abstract description 9
- 230000008021 deposition Effects 0.000 claims abstract description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 27
- 239000010936 titanium Substances 0.000 claims description 27
- 229910052719 titanium Inorganic materials 0.000 claims description 27
- 150000002500 ions Chemical class 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 15
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 11
- 229910017052 cobalt Inorganic materials 0.000 claims description 9
- 239000010941 cobalt Substances 0.000 claims description 9
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 239000007943 implant Substances 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 description 8
- 229910021341 titanium silicide Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000006911 nucleation Effects 0.000 description 4
- 238000010899 nucleation Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 아르곤, 게르마늄, 비소 가스를 이용한 실리사이드 개선방법에 관한 것으로, 실리콘 기판 상에 액티브(active) 영역을 형성하며, 실리콘 기판 상에 다결정 전극과 스페이서 질화막으로 구성된 일반적인 게이트 구조 전면에 실리사이드 형성을 위한 첫 번째 금속막을 일반적인 증착 두께의 절반의 두께로 얇게 증착한 후, 증착된 금속막 상에 아르곤(Argon : Ar), 게르마늄(Germanium : Ge), 비소(Arsenic : As) 가스를 이온 주입한다. 이후, Ar, Ge, As 가스가 주입된 금속막 상에 두 번째 금속막을 임의의 두께를 이중으로 증착하여 게이트 선폭이 감소하더라도 연속적이고 균일한 금속 실리사이드를 형성할 수 있도록 하는 효과가 있다.The present invention relates to a silicide improvement method using argon, germanium, and arsenic gas, and forms an active region on a silicon substrate, and forms silicide on the entire gate structure including a polycrystalline electrode and a spacer nitride film on the silicon substrate. After the first metal film is thinly deposited to a thickness of half of the general deposition thickness, argon (Argon: Ar), germanium (Ge), and arsenic (Arsenic: As) gases are implanted on the deposited metal film. Subsequently, the second metal film is deposited on the metal film into which the Ar, Ge, As gas is injected, and a predetermined thickness is doubled to form a continuous and uniform metal silicide even if the gate line width is reduced.
Description
본 발명은 실리사이드 개선방법에 관한 것으로, 특히 0.25㎛ 이상의 로직 반도체 소자의 실리사이드에 의한 게이트 형성에 있어서, 금속막 사이 또는 금속막 전체에 아르곤(Argon : Ar), 게르마늄(Germanium : Ge), 비소(Arsenic : As) 가스를 이온 주입하여 게이트 위와 접합(junction) 사이의 브리지(bridge) 없이 후 열처리 과정에서 균일하고 연속적인 실리사이드를 형성하도록 하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for improving silicide, and in particular, in the formation of a gate by silicide of a logic semiconductor element of 0.25 µm or more, argon (Argon: Ar), germanium (German), or arsenic (between or between metal films) Arsenic: As) The present invention relates to a method of ion-implanting a gas to form a uniform and continuous silicide in a post-heat treatment process without a bridge between a gate and a junction.
통상적으로, 0.25㎛ 이상의 로직 반도체 소자는 상부 금속막과 하부 실리콘을 접합(junction)과 게이트 전극 위에서만 선택적으로 반응시키는 실리사이드 형성 공정으로 접촉 저항을 감소시켜 준다.Typically, logic semiconductor devices of 0.25 [mu] m or more reduce contact resistance in a silicide formation process in which the upper metal film and the lower silicon are selectively reacted only on the junction and the gate electrode.
그러나, 상술한 실리사이드 형성 공정은 소자의 고집적화에 따른 설계 한계로 접합(junction) 사이의 거리에 게이트 전극의 폭이 급격히 감소되어 불 균일하고 불연속적인 실리사이드를 형성함에 따라 자체면 저항 증가와 누설 전류 역시 증가하여 반도체 소자의 불량을 유발하는 원인이 되었다.However, the silicide formation process described above is a design limitation due to the high integration of the device, so that the width of the gate electrode is sharply reduced at the distance between the junctions to form a non-uniform and discontinuous silicide. Increasingly, it is a cause of failure of the semiconductor device.
즉, 도 1을 참조하면, 도 1은 종래 불연속적이고 불균일적으로 형성된 실리사이드에 대하여 도시한 도면으로서, 실리콘 기판(1) 상에 액티브(active) 영역(2)을 형성한 후, 다시 실리콘 기판(1) 상에 다결정 전극(5)과 스페이서 질화막(4)으로 구성된 일반적인 게이트 구조에서 게이트의 선폭(S1)이 감소함에 따라 액티브 영역(2) 상에 형성된 금속 실리 사이드(3)와 다결정 전극(5) 상에 형성된 금속 실리사이드(6)가 덩어리(agglomeration) 됨에 따라 불연속적이고 불 균일하게 형성된 실리사이드(6)를 볼 수 있는 것이다. 여기서, 실리사이드의 형성은 소자의 집적도 증가에 따른 게이트 선폭(S1)의 감소로 더욱 취약해 지는데, 특히 금속 중 티타늄 실리사이드의 경우에는 안정된 실리사이드 형태인 C54상이 불안정한 실리사이드 형태인 C49상에서의 상 전이로부터 형성되고, 게이트 선폭(S1)의 더욱 감소함에 따라 C49상에서 C54상의 핵 생성 자리가 거의 없게 되어 하나의 핵 생성 자리에서 C54상이 불 균일하고 불연속적으로 금속 실리사이드(3, 6)를 형성하게 되는 문제점이 있었다.That is, referring to FIG. 1, FIG. 1 is a view illustrating a conventional discontinuous and non-uniformly formed silicide, and after forming an active region 2 on the silicon substrate 1, the silicon substrate ( In the general gate structure including the polycrystalline electrode 5 and the spacer nitride film 4 on 1), the metal silicide 3 and the polycrystalline electrode 5 formed on the active region 2 as the line width S1 of the gate decreases. As the metal silicide 6 formed on the agglomerate becomes agglomerated, the discontinuous and non-uniformly formed silicide 6 can be seen. Here, the formation of silicide becomes more vulnerable due to the decrease in the gate line width (S1) as the device density increases. In particular, in the case of titanium silicide, the stable silicide C54 phase is formed from the phase transition in the unstable silicide C49 phase. In addition, as the gate line width S1 is further reduced, there are almost no nucleation sites on the C54 phase on the C49 phase, so that the C54 phase forms a non-uniform and discontinuous metal silicide (3, 6) at one nucleation site. there was.
또한, 일반적인 게이트 실리사이드 형성 방법은 다결정 실리콘 전극과 접합(junction) 영역 전면에 티타늄 또는 코발트의 금속막을 전면에 증착한 후, RTP의 열공정을 실시하여 다결정 전극과 접합 위에서만 실리사이드를 형성하고 실리콘 전극과 접합 사이가 연결되지 않도록 반응하지 않은 티타늄 또는 코발트를 세정 공정으로 제거해 준다.In addition, a general method of forming a gate silicide is to deposit a metal film of titanium or cobalt on the entire surface of a junction region with a polycrystalline silicon electrode, and then perform a thermal process of RTP to form silicide only on the junction with the polycrystalline electrode. Unreacted titanium or cobalt is removed by a cleaning process so that there is no connection between the bond and the junction.
그러나, 상술한 실리사이드 형성 공정은 소자의 고집적화에 따른 설계 한계로 접합(junction) 사이의 거리와 게이트 전극 폭의 급격한 감소로 인하여 불 균일한 실리 사이드를 형성함에 따라 자체 실리사이드의 저항 증가와 접합(junction)과 게이트 전극에서의 누설 전류를 증가시켜 반도체 소자의 불량을 유발하게 되는 문제점이 있었다.However, the silicide formation process described above is a design limitation due to the high integration of the device, resulting in an increase in resistance of the silicide and junction of self silicide due to the formation of an uneven silicide due to a sharp decrease in the distance between the junction and the gate electrode width. ) And a leakage current at the gate electrode increases, causing a defect of the semiconductor device.
따라서, 본 발명은 상술한 문제점을 해결하기 위해 안출된 것으로서, 그 목적은 게이트와 접합(junction)에 균일한 실리사이드를 형성하기 위해 금속막(예로, 티타늄, 코발트, 니켈) 사이 또는 금속막 전체에 아르곤(Argon : Ar), 게르마늄(Germanium : Ge), 비소(Arsenic : As) 가스를 이온 주입하여 게이트 위와 접합(junction) 사이의 브리지(bridge) 없이 후 열처리 과정에서 균일하고 연속적인 실리사이드를 형성하도록 하는 아르곤, 게르마늄, 비소 가스를 이용한 실리사이드 개선방법을 제공함에 있다.상술한 목적을 달성하기 위하여 본 발명에 따른 아르곤, 게르마늄, 비소 가스를 이용한 실리사이드 개선방법은 실리콘 기판 상에 액티브 영역을 형성하며 실리콘 기판 상에 다결정 전극과 스페이서 질화막으로 구성된 일반적인 게이트 구조 전면에 실리사이드 형성을 위한 금속막을 제1의 두께로 증착하는 단계와, 제1의 두께 금속막 상에 아르곤, 게르마늄, 비소 가스를 이온주입하는 단계와, 이온 주입된 제1의 두께 금속막 상부에 실리사이드 형성을 위한 금속막을 제2의 두께로 증착하는 단계를 포함하는 것을 특징으로 한다.또한, 상술한 목적을 달성하기 위하여 본 발명의 다른 실시 예에서 아르곤, 게르마늄, 비소 가스를 이용한 실리사이드 개선방법은 실리콘 기판 상에 액티브 영역을 형성하며 실리콘 기판 상에 다결정 전극과 스페이서 질화막으로 구성된 일반적인 게이트 구조 전면에 실리사이드 형성을 위한 금속막을 증착하는 단계와, 금속막 상에 아르곤, 게르마늄, 비소 가스를 이온주입하는 단계와, 이온 주입된 금속막 상에 질화 금속막을 증착하는 단계를 포함하는 것을 특징으로 한다.Accordingly, the present invention has been made to solve the above-described problems, and an object thereof is to provide a uniform silicide at a gate and a junction between a metal film (eg, titanium, cobalt, nickel) or the metal film as a whole. Argon (Ar), Germanium (Ge), and Arsenic (As) gases are ion implanted to form uniform and continuous silicides in the post-heating process without the bridge between the gate and the junction. The present invention provides a method for improving silicide using argon, germanium, and arsenic gas. According to the present invention, a method for improving silicide using argon, germanium, and arsenic gas forms an active region on a silicon substrate and To form silicide on the entire surface of a general gate structure composed of a polycrystalline electrode and a spacer nitride film on a substrate. Depositing a metal film to a first thickness, ion implanting argon, germanium, and arsenic gas onto the first thickness metal film, and depositing a metal film on the first thick metal film to form silicide. In addition, in order to achieve the above object, in another embodiment of the present invention, a method for improving silicide using argon, germanium, and arsenic gas may be performed on a silicon substrate. Depositing a metal film for silicide formation on the entire gate structure including a polycrystalline electrode and a spacer nitride film on a silicon substrate, ion implanting argon, germanium, and arsenic gas onto the metal film, And depositing a metal nitride film on the metal film.
도 1은 종래 불연속적이며 불균일적으로 형성된 실리사이드에 대하여 도시한 도면이고,1 is a view showing a conventional discontinuous and non-uniformly formed silicide,
도 2와 도 3은 본 발명에 따른 반도체 소자의 실리사이드에 의한 게이트 형성 방법에 대하여 도시한 도면이며,2 and 3 are views showing a gate forming method by silicide of a semiconductor device according to the present invention,
도 4 내지 도 6은 본 발명의 다른 실시 예에 따른 반도체 소자의 실리사이드에 의한 게이트 형성 방법에 대하여 도시한 도면이며,4 to 6 are diagrams illustrating a gate forming method by silicide of a semiconductor device according to another embodiment of the present invention.
도 7은 본 발명에 따른 RTP에 의한 열처리 공정으로 하부 실리콘 기판과 상부 금속막을 반응시켜 금속막 실리사이드를 도시한 도면이다.7 is a diagram illustrating a metal film silicide by reacting a lower silicon substrate and an upper metal film by a heat treatment process by RTP according to the present invention.
도 8은 티타늄을 이중으로 증착하고, 첫 번째로 증착된 티타늄 상에 Ar, Ge, As의 이온을 주입하여 실리사이드 형성에 대한 도면이며,FIG. 8 is a diagram of silicide formation by depositing a double titanium, and implanting ions of Ar, Ge, As on the first deposited titanium,
도 9는 티타늄 실리사이드를 형성하기 위한 Ar, Ge, As의 이온 주입된 금속막 상에 전체 티타늄 두께를 증착시킨 도면이다.FIG. 9 is a diagram in which the entire titanium thickness is deposited on an ion-implanted metal film of Ar, Ge, As to form titanium silicide.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
1 : 실리콘 기판 2 : 액티브 영역1: silicon substrate 2: active region
3, 6, 13, 14 : 금속 실리사이드 4 : 스페이서 질화막3, 6, 13, 14: metal silicide 4: spacer nitride film
5 : 다결정 전극 7 : 첫 번째 증착된 금속막5: polycrystalline electrode 7: first deposited metal film
8, 11, 15 : Ar, Ge, As 이온 주입 9 : 두 번째 증착된 금속막8, 11, 15: Ar, Ge, As ion implantation 9: Second deposited metal film
10 : 전체 두께의 금속막 12, 17, 21 : 질화 금속막10: metal film in full thickness 12, 17, 21: metal nitride film
16 : 두 번째 금속막16: second metal film
18 : 첫 번째로 증착된 금속막으로부터 형성된 금속 실리사이드 막18: metal silicide film formed from the first deposited metal film
19 : 두 번째로 증착된 금속막으로부터 형성된 금속 실리사이드 막19: metal silicide film formed from second deposited metal film
20 : 이온 주입된 금속막 22, 23 : 금속 실리사이드 막20: ion implanted metal film 22, 23: metal silicide film
S1 : 게이트 선폭S1: gate line width
이하, 첨부된 도면을 참조하여 본 발명에 따른 실시 예를 상세하게 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2 내지 도 9는 본 발명에 따른 반도체 소자의 실리사이드에 의한 게이트 형성 방법으로써, 게이트와 접합(junction)에 균일한 실리사이드를 형성하기 위하여 티타늄, 코발트, 니켈의 금속막 사이 또는 금속막 전체 표면에 아르곤(Argon : Ar), 게르마늄(Germanium : Ge), 비소(Arsenic : As) 가스를 이온 주입하여 후 열처리 과정에서 균일하고 연속적인 실리사이드를 형성하도록 하는 공정 과정을 도시한 도면이다.2 to 9 is a method of forming a gate by silicide of a semiconductor device according to the present invention, in order to form a uniform silicide at the junction with the gate between the metal film of titanium, cobalt, nickel or the entire surface of the metal film. Argon (Argon: Ar), germanium (Germanium: Ge), Arsenic (Arsenic: As) is a view showing a process for forming a uniform and continuous silicide in the post-heat treatment process by ion implantation.
즉, 도 2와 도 3은 본 발명에 따른 반도체 소자의 실리사이드에 의한 게이트 형성 방법으로써, 실리콘 기판(1) 상에 액티브(active) 영역(2)을 형성한 후, 다시 실리콘 기판(1) 상에 다결정 전극(5)과 스페이서 질화막(4)으로 구성된 일반적인 게이트 구조 전면에 실리사이드 형성을 위한 첫 번째 금속막(예로, 티타늄, 코발트, 니켈막)(7)을 일반적인 증착 두께의 절반인 100∼250Å의 두께로 얇게 증착한다.2 and 3 illustrate a method of forming a gate by silicide of a semiconductor device according to an embodiment of the present invention, and after forming an active region 2 on a silicon substrate 1, the silicon substrate 1 is again formed on the silicon substrate 1. The first metal film (eg, titanium, cobalt, nickel film) 7 for silicide formation on the entire gate structure composed of the polycrystalline electrode 5 and the spacer nitride film 4 at 100-250 kPa, which is half of the typical deposition thickness. Thinly deposited to the thickness of.
첫 번째 금속막(7)이 증착된 후, 증착된 금속막(7) 상에 Ar, Ge, As 가스를 이온 주입(8)한다. 여기서, 이온 주입 조건은 얇은 티타늄막 내에만 이온이 들어가도록 1∼10KeV의 에너지와 1e13∼5e14의 도스(dose) 조건으로 주입(implant)을 실시한다.After the first metal film 7 is deposited, Ar, Ge, As gases are ion implanted 8 on the deposited metal film 7. Here, the ion implantation conditions are implanted under energy conditions of 1 to 10 KeV and dose conditions of 1e13 to 5e14 so that ions enter only in the thin titanium film.
Ar, Ge, As 가스를 이온 주입(8)한 후, 도 3에 도시된 바와 같이, 주입된 금속막(7)상에 두 번째 금속막(9)을 100∼250Å의 두께를 이중으로 증착한다.After ion implantation 8 of Ar, Ge, As gas, as shown in FIG. 3, a second metal film 9 is deposited on the injected metal film 7 in a thickness of 100 to 250 kPa in double. .
도 4 내지 도 6은 본 발명의 다른 실시 예에 따른 반도체 소자의 실리사이드에 의한 게이트 형성 방법으로써, 실리콘 기판(1) 상에 액티브(active) 영역(2)을 형성한 후, 다시 실리콘 기판(1) 상에 다결정 전극(5)과 스페이서 질화막(4)으로 구성된 일반적인 게이트 구조 전면에 실리사이드 형성을 위한 전체 두께의 금속막(예로, 티타늄, 코발트, 니켈막)(10)을 200∼500Å의 두께를 한번에 증착한다.4 to 6 illustrate a method of forming a gate by silicide of a semiconductor device according to another exemplary embodiment, and after forming an active region 2 on the silicon substrate 1, the silicon substrate 1 is again formed. A total thickness of the metal film (for example, titanium, cobalt and nickel films) 10 for silicide formation on the entire gate structure composed of the polycrystalline electrode 5 and the spacer nitride film 4 on Deposit at once.
전체 두께의 금속막(10)이 증착된 후, 증착된 금속막(10) 상에 도 5에 도시된 바와 같이, Ar, Ge, As 가스를 이온 주입(11)한다. 여기서, 이온 주입 조건은200∼500Å의 두꺼운 티타늄막에 Ar, Ge, As 가스가 이온 주입(11)되도록 5∼50KeV의 높은 에너지를 이용하고, 많은 양의 이온이 주입되도록 1e14∼1e16의 하이 도스(high dose) 조건으로 주입(implant)을 실시한다.After the full thickness metal film 10 is deposited, Ar, Ge, As gases are ion implanted 11 as shown in FIG. 5 on the deposited metal film 10. Here, the ion implantation conditions are a high dose of 1e14 to 1e16 to use a high energy of 5 to 50 KeV to inject the Ar, Ge, As gas into the thick titanium film of 200 to 500 kW, and to implant a large amount of ions. Implants are performed under high dose conditions.
Ar, Ge, As 가스를 이온 주입(11)한 후, 도 6에 도시된 바와 같이, 주입된 금속막(10) 상에 질화 금속(티타늄)막(12)을 100∼300Å 정도 증착한다.After ion implantation 11 of Ar, Ge, As gas, as shown in FIG. 6, a metal nitride (titanium) film 12 is deposited on the implanted metal film 10 by about 100 to 300 kPa.
도 7은 RTP에 의한 열처리 공정으로 하부 실리콘 기판과 상부 금속막을 반응시켜 금속 실리사이드(13, 14)를 도시한 것으로, 액티브와 게이트 전극에만 형성하고, 반응하지 않은 일부 금속막과 질화 금속막(12)을 세정공정으로 제거하여 균일하고 연속적인 금속 실리사이드(13, 14)를 형성할 수 있는 것이다.FIG. 7 illustrates metal silicides 13 and 14 by reacting a lower silicon substrate and an upper metal film by a heat treatment process by RTP. The metal silicides 13 and 14 are formed only on the active and gate electrodes and are not reacted. ) May be removed by a washing process to form uniform and continuous metal silicides 13 and 14.
참고적으로, 도 8은 티타늄을 이중으로 증착하고, 첫 번째로 증착된 티타늄 상에 Ar, Ge, As 가스를 이온 주입하여 주입된 첫 번째 금속막(15) 위에 두 번째 금속(티타늄)막(16)을 형성되며, 그 위에 질화 금속막(17)을 형성하는 C49상의 실리사이드를 핵 생성 자리를 많이 만들어 준다.For reference, FIG. 8 shows a second metal (titanium) film (titanium) layer on the first metal film 15 that is deposited by double deposition of titanium and implanted with Ar, Ge, As gas on the first deposited titanium. 16), and the silicide on C49 forming the metal nitride film 17 thereon creates a lot of nucleation sites.
즉, 고온에서의 RTP에 의한 열처리로 작아지는 게이트 선폭(S1)으로 많은 C49상의 결정립계에서 안정된 C54상의 실리사이드, 즉 첫 번째로 증착된 금속막으로부터 형성된 금속 실리사이드 막(18)과 두 번째로 증착된 금속막으로부터 형성된 금속 실리사이드 막(19)이 연속적이고 균일하게 형성할 수 있게 한다. 이때, 이온 주입 조건은 이중으로 증착되는 티타늄의 경우에 하부 티타늄에만 이온이 남도록 낮은 에너지와 적은 도스(dose) 양을 주입하는 조건을 사용한다.That is, the silicide of C54 phase which is stable at the grain boundaries of many C49 phases due to the gate line width S1 reduced by the heat treatment by RTP at high temperature, that is, the metal silicide film 18 formed from the first deposited metal film and the second deposited The metal silicide film 19 formed from the metal film can be formed continuously and uniformly. In this case, the ion implantation conditions are used to inject a low energy and a small dose (doses) so that ions remain only in the lower titanium in the case of the titanium deposited in duplicate.
그리고, 도 9는 티타늄 실리사이드를 형성하기 위한 Ar, Ge, As 가스가 이온주입된 금속막(20) 상에 전체 티타늄 두께를 증착하며, 그 위에 질화 금속막(21)을 형성한 후, 티타늄 실리사이드 형성은 하부 실리콘 기판과 반응하여 형성된 금속 실리 사이드 막(23)인 티타늄의 반응과 동시에 이온 주입된 금속막 윗 부분에서 형성된 금속 실리사이드 막(22), 즉 티타늄 상부에 이온 주입된 부분에서도 반응하여 양쪽에서 초기 금속막 표면에 C49상의 불안정한 티타늄 실리사이드를 형성하게 되고 이러한 실리사이드 반응은 다음의 고온 RTP 열처리에 의해 많은 C49상의 결정립계에서 안정한 C54상을 연속적이고 균일하게 형성할 수 있다. 이때, 실리콘 이온 주입 조건은 도 8에 도시된 티타늄 두께 보다 두껍기 때문에 200∼500Å의 많은 이온이 금속막 전체에 주입되도록 많은 도스(dose) 양과 높은 에너지 조건을 선택한다.9 illustrates depositing the entire titanium thickness on the metal film 20 into which the Ar, Ge and As gas are ion-implanted to form the titanium silicide, and forming the metal nitride film 21 thereon, and then the titanium silicide Formation is simultaneously performed by the reaction of titanium, the metal silicide film 23 formed by reacting with the lower silicon substrate, and simultaneously with the metal silicide film 22 formed on the ion-implanted metal film, that is, the ion-implanted portion on the titanium. In the formation of the unstable titanium silicide of the C49 phase on the surface of the initial metal film, the silicide reaction can continuously and uniformly form a stable C54 phase at the grain boundaries of many C49 phases by the following high temperature RTP heat treatment. At this time, since the silicon ion implantation conditions are thicker than the titanium thickness shown in FIG. 8, a large amount of dose and a high energy condition are selected so that a large amount of ions of 200 to 500 kW are implanted into the entire metal film.
또한, 도 8과 도 9에서의 실리콘 이온 주입은 티타늄막 내의 결정 결함을 많이 형성하고 이로 인한 티타늄막 내의 내부 에너지를 증가시켜 초기에 C49상의 형성을 용이하게 하여 작은 결정립의 C49상의 실리사이드를 형성할 수 있는 것이다.In addition, the silicon ion implantation in FIGS. 8 and 9 forms a large number of crystal defects in the titanium film, thereby increasing the internal energy in the titanium film, thereby facilitating the formation of the C49 phase initially to form silicides of the C49 phase of small grains. It can be.
그러므로, 본 발명은 게이트와 접합(junction)에 균일한 실리사이드를 형성하기 위해 금속막(예로, 티타늄, 코발트, 니켈) 사이 또는 금속막 전체에 Ar, Ge, As 가스를 이온 주입하여 RTP에 의한 열처리 공정에서 초기에 형성되는 불안정한 실리사이드 형태인 C49상의 핵 생성 자리를 많이 형성시켜 작은 결정립의 C49상을 만들어 줌에 따라 0.18㎛ 이상의 고집적 소자에서 게이트 선폭이 작아지더라도 750∼850℃의 고온에서의 RTP 공정에 의해 C49상의 많은 결정립계에서 안정할 뿐만 아니라, 저항이 작은 C54상이 핵 생성되어 접합(junction)과 게이트 전극 상에 균일하고 연속적인 C54상의 티타늄 실리사이드를 형성시킬 수 있는 효과가 있다.Therefore, the present invention provides a heat treatment by RTP by ion implanting Ar, Ge, As gas between a metal film (for example, titanium, cobalt, nickel) or the entire metal film to form uniform silicide at the junction with the gate. The formation of many nucleation sites on the C49 phase, which is an unstable silicide form initially formed in the process, creates a small grain C49 phase. In addition to being stable at many grain boundaries of the C49 phase, the C54 phase having a low resistance is nucleated to form a uniform and continuous titanium silicide on the junction and the gate electrode.
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| US4683645A (en) * | 1985-06-28 | 1987-08-04 | Northern Telecom Limited | Process of fabricating MOS devices having shallow source and drain junctions |
| JPH08330253A (en) * | 1995-06-02 | 1996-12-13 | Texas Instr Inc <Ti> | Method of forming silicide on polysilicon line |
| KR19990075831A (en) * | 1998-03-25 | 1999-10-15 | 김영환 | Manufacturing Method of Semiconductor Device |
| KR20000048088A (en) * | 1998-12-11 | 2000-07-25 | 가네꼬 히사시 | Semiconductor device and method for manufacturing same |
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| US4683645A (en) * | 1985-06-28 | 1987-08-04 | Northern Telecom Limited | Process of fabricating MOS devices having shallow source and drain junctions |
| JPH08330253A (en) * | 1995-06-02 | 1996-12-13 | Texas Instr Inc <Ti> | Method of forming silicide on polysilicon line |
| KR19990075831A (en) * | 1998-03-25 | 1999-10-15 | 김영환 | Manufacturing Method of Semiconductor Device |
| KR20000048088A (en) * | 1998-12-11 | 2000-07-25 | 가네꼬 히사시 | Semiconductor device and method for manufacturing same |
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