KR100422583B1 - Phase Comparator for Semiconductor Memory Device and its Method - Google Patents

Abstract

An object of the present invention is to provide a phase comparator for a semiconductor memory device which is resistant to voltage variations of the semiconductor memory device by extending the lock-in range after the first lock-in.

In order to achieve the above object, the phase comparator for a semiconductor memory device of the present invention receives a reference clock signal and a phase comparison input clock signal as inputs, detects that the reference clock signal and the phase comparison input clock signal are input, and confirms the input. Input confirmation pulse generating means for generating a pulse; Shift left control signal generating means for receiving the reference clock signal, the phase comparison input clock signal and the input confirmation pulse as inputs for generating a shift left control signal using the reference clock signal and the phase comparison input clock signal; The reference clock signal, the phase comparison input clock signal, and the reference clock signal to generate a shift light control signal using the first unit time delayed phase comparison input clock signal having the unit time delayed by the phase comparison input clock signal and the reference clock signal. Shift light control signal generating means for receiving an input confirmation pulse as an input; The second unit time to generate an extended shift write control signal using the second unit time delayed phase comparison input clock signal having delayed the phase comparison input clock signal by a predetermined unit time, the reference clock signal, and the input confirmation pulse; Expansion shift control signal generating means for receiving a delayed phase comparison input clock signal, the reference clock signal, and the input confirmation pulse as inputs; The phase comparison input clock signal and the unit to generate an extended shift left control signal using the unit time delayed reference clock signal which delays the phase comparison input clock signal and the reference clock signal by a predetermined unit time and the input confirmation pulse; Expansion shift left control signal generation means for receiving a time delayed reference clock signal and the input confirmation pulse; And using the first lock-in signal as a control signal, selects and outputs a shift control signal generated at the output end of the shift left control signal generating means and the output end of the shift light control signal generating means before the first lock-in. After the lock-in, the output end of the shift left control signal generating means selects and outputs the control signal for shift generated at the output end of the extended shift left control signal generating means and the output end of the extended shift right control signal generating means, and the shift. And an output end of the light control signal generating means, an output end of the extended shift left control signal generating means and an output end of the extended shift light control signal generating means as inputs.

Description

Phase Comparator for Semiconductor Memory Device and its Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparator for a semiconductor memory device and a control method thereof. Specifically, the present invention relates to a delay locked loop that is insensitive to voltage changes by varying the lock-in range before and after the lock-in of the phase comparator. It is about.

In general, a clock is used as a reference for timing operation in a system or a circuit, and may be used to ensure faster operation without an error. When a clock input from the outside is used internally, a time delay (clock skew) is generated by an internal circuit. A DLL is used to compensate for this time delay so that the internal clock has the same phase as the external clock. have.

One important factor for DLLs is that they require low jitter, which is still required for future semiconductor memory devices that are becoming low voltage and fast. On the other hand, DLL has the advantage of being less affected by noise than conventional phase locked loop (PLL), so it is widely used in synchronous semiconductor memory including DDR Double Data Rate Synchronous DRAM (SDRAM). The DLL is the most widely used, for example, to specifically look at the problems of the prior art.

1 is a block diagram of a register-controlled DLL of a general DDR SDRAM.

The register-controlled DLL of a general DDR SDRAM has a first clock buffer for generating an internal clock signal (fall_clk) generated in synchronization with a falling edge of the external clock signal (clk) by inputting an external clock inversion signal (/ clk). 110, a second clock buffer 120 for generating the internal clock signal rise_clk generated in synchronization with the rising edge of the external clock signal clk by using the external clock signal clk, and the external clock signal. The internal clock signal (rise_clk) generated in synchronization with the rising edge of (clk) is divided into 1 / n (n is a positive integer, and typically n = 8) to delay monitoring clock signal (dly_in) and reference clock signal ( com_ref) outputs a clock divider 400, a first delay line 210 that inputs an internal clock signal fall_clk generated in synchronization with the falling edge of the external clock signal clk, and an external clock signal ( The internal clock signal (rise_clk) generated in synchronization with the rising edge of clk) Output of the second delay line 220, the third delay line 230 to which the delay monitoring clock signal dly_in is input, and the first, second and third delay lines 210, 220 and 230, respectively. A shift register 240 for determining the delay amount, a first DLL driver 310 for driving the output ifclk of the first delay line 210 to generate the DLL clock fclk_dll, and a second delay line A second DLL driver 320 for generating the DLL clock rclk_dll by driving the output irclk of 220 and an output feedback_dly of the third delay line 230 are inputted, so that the clock feedback_dly is inputted. A phase comparator for comparing phases using a delay model 500 configured to undergo the same delay condition as the actual clock path, and a phase comparison input signal cmp_in and a reference clock signal cmp_ref which are outputs of the delay model 500. And the shift direction of the shift register 240 in response to the control signal ctrl output from the phase comparator 260. And a shift controller 250 for outputting the shift control signals SR and SL and a delay lock signal dll_lockb indicating that delay lock is performed.

In this case, the delay model 500 includes a dummy clock buffer, a dummy output buffer, and a dummy load in order to have a delay time equal to the delay time occurring in the path of the actual clock, and is also called a replica circuit. The first, second and third delay lines 210, 220, 230, the shift register 240, the shift controller 250, and the phase comparator 260 delay the external clock signal clk as necessary. The control unit 200 is called.

The delay model 500 includes a dummy clock buffer, a dummy output buffer, and a dummy load to compensate for the time when the actual clock is delayed by the clock buffer, the output buffer and the load, and the external clock signal clk is an internal clock. Since the signal is not synchronized with the signal, the remaining delay for synchronizing the external clock signal clk with the internal clock signal is performed by the delay controller 200.

2 (a) is a detailed circuit diagram of a phase detector according to the prior art, which detects that two clock signals, a reference clock signal cmp_ref and a phase comparison input clock signal cmp_in, are input to generate an input confirmation pulse. A shift left control signal is generated using an input confirmation pulse generator 261 that receives (cmp_ref) and a phase comparison input clock signal (cmp_in) as a input, and a reference clock signal (cmp_ref) and a phase comparison input clock signal (cmp_in). The unit time-delayed phase comparison of the reference clock signal cmp_ref, the phase comparison input clock signal cmp_in, and the shift left control signal generator 262 and the phase comparison input clock signal cmp_in In order to generate the shift light control signal using the input clock signal cmp_ind and the reference clock signal cmp_ref, the reference clock signal cmp_ref, the phase comparison input clock signal cmp_in, and the input confirmation pulse The shift light control signal generation unit 264 that accepts as an input.

The shift light generator 264 includes a unit delay time unit 263 including one inverter and one NAND gate to delay the phase comparison input clock signal cmp_in by one unit delay time.

Figure 2 (b) is an output waveform diagram of a phase comparator according to the prior art.

If the rising edge of the reference clock signal cmp_ref is behind the rising edge of the phase comparison input clock signal cmp_in and the rising edge of the phase comparison input clock signal cmp_ind delayed, the output terminal of the shift light control signal generator 264 (rsh2) is transferred to the "H" state to generate the shift light control signal ((1) of FIG. 2 (b)), and the rising edge of the reference clock signal cmp_ref is rising of the phase comparison input clock signal cmp_in. When the edge and the unit time delayed phase comparison input clock signal cmp_ind are ahead of the rising edge, the output terminal lsh1 of the shift left control signal generator 262 transitions to the "H" state to generate a shift left control signal. On the other hand, when the rising edge of the reference clock signal (cmp_ref) is behind the rising edge of the phase comparison input clock signal (cmp_in), and ahead of the rising edge of the phase comparison input clock signal (cmp_ind) delayed unit time, both output terminals (lsh1, rsh2) transitions to the "L" state and locks in.

On the other hand, the clock output from the DLL is used during the read operation, the DRAM consumes a lot of current during the read operation, resulting in a voltage drop. The voltage drop lengthens the transistor, The DLL will change the lock-in position. It may move as little as one unit delay, but may move by more unit delays depending on the magnitude of the change in voltage. DLLs operate to more accurately set lock-in positions for changed environments (voltage, temperature, etc.), but if the lock-in positions change a lot, the opposite is true. . This is because the time that the DLL detects the phase and thus changes the lock-in position is much longer than the time that the voltage changes. In other words, the newly locked-in voltage has a different value from the voltage detected when the phase is detected, which causes a serious problem that the data output access time tAC is changed.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a phase comparator for a semiconductor memory device which is resistant to voltage fluctuations in a semiconductor memory device by extending the lock-in range after the first lock-in.

Another object of the present invention is to provide a method for controlling a phase comparator for a semiconductor memory device, which is resistant to voltage fluctuations in the semiconductor memory device by extending the lock-in range after the first lock-in.

1 is a block diagram of a register-controlled DLL of a general DDR SDRAM;

2a is a detailed circuit diagram of a phase detector according to the prior art;

2b is an output waveform diagram of a phase comparator according to the prior art,

3A is a detailed circuit diagram of a phase detector according to a first embodiment of the present invention;

3b is an output waveform diagram of a phase comparator according to the present invention;

4A is a circuit diagram for signal selection before and after initial lock-in of a phase comparator according to the present invention;

4B is an exemplary view of a circuit diagram for signal selection of FIG. 4A.

5 is a circuit diagram for designating an initial value of a phase comparator according to the present invention;

6 is a detailed circuit diagram of a phase detector according to a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: clock buffer 200: delay control unit

210: first delay line 220: second delay line

230: third delay line 240: shift register

250: shift controller 260: phase comparator

261: input confirmation pulse generator 262: shift left control signal generator

263: unit time delay unit 264: shift light control signal generation unit

265: first phase comparison input clock signal delay unit

265-1: Second phase comparison input clock signal delay unit

266: extended shift light control signal generator

267: first reference clock signal delay unit

267-1: second reference clock signal delay unit

268: extended shift left control signal generator

300: DLL driver 400: clock divider

500: delay model

A phase comparator for a semiconductor memory device of the present invention for achieving the above object receives a reference clock signal and a phase comparison input clock signal as an input, detects that the reference clock signal and the phase comparison input clock signal has been input, and confirms the input Input confirmation pulse generating means for generating a pulse; Shift left control signal generating means for receiving the reference clock signal, the phase comparison input clock signal and the input confirmation pulse as inputs for generating a shift left control signal using the reference clock signal and the phase comparison input clock signal; The reference clock signal, the phase comparison input clock signal, and the reference clock signal to generate a shift light control signal using the first unit time delayed phase comparison input clock signal having the unit time delayed by the phase comparison input clock signal and the reference clock signal. Shift light control signal generating means for receiving an input confirmation pulse as an input; The second unit time to generate an extended shift write control signal using the second unit time delayed phase comparison input clock signal having delayed the phase comparison input clock signal by a predetermined unit time, the reference clock signal, and the input confirmation pulse; Expansion shift control signal generating means for receiving a delayed phase comparison input clock signal, the reference clock signal, and the input confirmation pulse as inputs; The phase comparison input clock signal and the unit to generate an extended shift left control signal using the unit time delayed reference clock signal which delays the phase comparison input clock signal and the reference clock signal by a predetermined unit time and the input confirmation pulse; Expansion shift left control signal generation means for receiving a time delayed reference clock signal and the input confirmation pulse; And using the first lock-in signal as a control signal, selects and outputs a shift control signal generated at the output end of the shift left control signal generating means and the output end of the shift light control signal generating means before the first lock-in. After the lock-in, the output end of the shift left control signal generating means selects and outputs the control signal for shift generated at the output end of the extended shift left control signal generating means and the output end of the extended shift right control signal generating means, and the shift. And an output end of the light control signal generating means, an output end of the extended shift left control signal generating means and an output end of the extended shift light control signal generating means as inputs.

Further, the extended shift light control signal generating means of the present invention includes a predetermined time delay means for delaying the phase comparison input clock signal by a predetermined unit delay time.

In addition, the predetermined time delay means of the present invention, characterized in that the input terminal is connected between the two inverters connected in series with the line of the phase comparison input clock signal and the series connected two inverters, characterized in that the output terminal is composed of one inverter floating It is done.

In addition, the predetermined time delay means of the present invention is characterized by consisting of one inverter and one NAND gate.

In addition, the extended shift left control signal generating means of the present invention is characterized in that it comprises a predetermined time delay means for delaying the reference clock signal by a predetermined unit delay time.

In addition, the predetermined time delay means of the present invention, characterized in that the input terminal is connected between the two inverters connected in series with the line of the phase comparison input clock signal and the series connected two inverters, characterized in that the output terminal is composed of one inverter floating It is done.

In addition, the predetermined time delay means of the present invention is characterized by consisting of one inverter and one NAND gate.

In addition, the phase comparator for the semiconductor memory device of the present invention is behind the rising edge of the phase comparison input clock signal delayed by the unit time delay than the rising edge of the reference clock signal, and the phase comparison input is higher than the rising edge of the reference clock signal delayed by the unit time. If the rising edge of the clock signal is ahead, it is characterized in that the lock-in.

In addition, the phase comparator for the semiconductor memory device of the present invention is behind the rising edge of the phase comparison input clock signal delayed by the unit time delay than the rising edge of the reference clock signal, and the phase comparison input is higher than the rising edge of the reference clock signal delayed by the unit time. When the rising edge of the clock signal is advanced, it is characterized in that the state of the output terminal of the extended shift light control signal generating means and the output terminal of the extended shift left control signal generating means.

In addition, the control method of the phase comparator for semiconductor memory device of the present invention selects a shift control signal generated at the output end of the shift left control signal generating means and the output end of the shift light control signal generating means before the first lock-in. Outputting the first step; And a second step of selecting and outputting a shift control signal generated at an output end of the extended shift left control signal generating means and an output end of the extended shift light control signal generating means after the first lock-in. .

Further, in the second step of the present invention, the rising edge of the phase comparison input clock signal delayed by the unit time delayed from the rising edge of the reference clock signal, and the rising edge of the phase comparison input clock signal compared to the rising edge of the reference clock signal delayed by the unit time. Is preceded, it comprises a third step of generating a lock-in signal.

Further, in the second step of the present invention, the rising edge of the phase comparison input clock signal delayed by the unit time delayed from the rising edge of the reference clock signal, and the rising edge of the phase comparison input clock signal compared to the rising edge of the reference clock signal delayed by the unit time. Is preceded, it is characterized in that it comprises a third step of transitioning the state of the output terminal of the extended shift light control signal generating means and the output terminal of the extended shift left control signal generating means.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

FIG. 3 (a) is a detailed circuit diagram of a phase detector according to a first embodiment of the present invention, in which an input confirmation pulse generator 261 of the prior art of FIG. 2 (a) and a shift left control signal are generated for first lock-in. In addition to including the components of the portion 262 and the shiftlight control signal generator 264, the apparatus further includes components to provide an extended lock-in range after the initial lock-in.

That is, the extended shift light control signal is obtained using the unit time delayed phase comparison input clock signal cmp_inld, the reference clock signal cmp_ref, and the input confirmation pulse cmp_pulse, which delays the phase comparison input clock signal cmp_in by a unit time. Extended shift light control that accepts the unit time delayed phase comparison input clock signal (cmp_inld), the reference clock signal (cmp_ref), and the input confirmation pulse (cmp_pulse) as the input to delay the phase comparison input clock signal (cmp_in) by a unit time. Extended shift left using the unit time delayed reference clock signal cmp_refld and the input confirmation pulse cmp_pulse in which the signal generator 266 and the phase comparison input clock signal cmp_in and the reference clock signal cmp_ref are delayed by a unit time. A unit time delayed reference clock signal (cmp_refld) in which the phase comparison input clock signal (cmp_in) and the reference clock signal (cmp_ref) are delayed by a unit time to generate a control signal; Determine acceptance pulse (cmp_pulse) as an input force further includes an extended shift left control signal generating unit 268. The

The extended shift light control signal generator 266 includes two inverters connected in series and one inverter in which an output stage is floated to act as a capacitor therebetween in order to delay the phase comparison input clock control signal cmp_in by a unit delay time. And a first phase comparison input signal delay unit 265 configured, and the extended shift left control signal generation unit 268 serves as a capacitor between two inverters connected in series to delay the reference clock signal by a unit delay time. And a first reference clock signal delay unit 267 composed of one inverter having the output terminal floated.

3 (b) is an output waveform diagram of the phase comparator according to the present invention.

The rising edge of the phase comparison input clock signal cmp_inld is delayed by the unit time delayed from the rising edge of the reference clock signal cmp_ref ((1) of FIG. 3 (b)), and the rising edge of the reference clock signal cmp_refld delayed by the unit time. If the rising edge of the phase comparison input clock signal cmp_in is earlier, the output terminal rsh_ac of the extended shift light control signal generator 266 and the output terminal lsh_ac of the extended shift left control signal generator 268 are in an "L" state. Transitions to lock-in. Referring to Figure 3 (b) it can be seen that the range of the lock-in is extended from one unit delay time to two unit delay time according to the prior art.

FIG. 4 (a) is a circuit diagram for signal selection before and after the first lock-in of the phase comparator according to the present invention, and FIG. 4 (b) is a detailed diagram of the circuit diagram for signal selection in FIG. 4 (a).

Before the first lock-in using the first lock-in signal as a control signal in the multiplexer, an output terminal lsh1 of the shift left control signal generator 262 and an output terminal rsh2 of the shift light control signal generator 264 are generated. The control signal is selected, and after the first lock-in, the control signal generated at the output terminal lsh_ac of the extended shift left control signal generator 268 and the output terminal rsh_ac of the extended shift light control signal generator 266 is selected. Do it.

5 is a circuit diagram for designating an initial value of the phase comparator 260 according to the present invention.

Since the DLL is locked in by delaying the external clock, the initial state of the DLL is shift write. Also, since the DLL is not initially locked in, lock_in is in the "L" state. The reset bar signal used to specify the initial value is active in the "L" state when it is a reset DLL in a power-up or extended mode register set, and when in a disabling DLL or self-refresh mode. This is a signal that is operated.

FIG. 6 is a detailed circuit diagram of a phase detector according to a second embodiment of the present invention. Most of the configurations are the same as those of the first embodiment of FIG. 3 (a), and only one inverter, such as a unit time delay unit 263, is shown. The difference is that a single NAND gate is used to construct a circuit for delaying unit time.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains, and the foregoing embodiments and the accompanying drawings. It is not limited to.

According to the present invention, it is possible to provide a delay locked loop that is resistant to a voltage change occurring in a semiconductor memory device. Thus, the position of the clock output from the delay locked loop moves less during a read operation with a large voltage change, and a change width of data is reduced. In addition, there is an advantageous effect that the data output access time tAC is also improved.

Claims (12)

Input confirmation pulse generating means for receiving a reference clock signal and a phase comparison input clock signal as an input, detecting that the reference clock signal and the phase comparison input clock signal have been input, and generating an input confirmation pulse; Shift left control signal generating means for receiving the reference clock signal, the phase comparison input clock signal and the input confirmation pulse as inputs for generating a shift left control signal using the reference clock signal and the phase comparison input clock signal; The reference clock signal, the phase comparison input clock signal, and the reference clock signal to generate a shift light control signal using the first unit time delayed phase comparison input clock signal having the unit time delayed by the phase comparison input clock signal and the reference clock signal. Shift light control signal generating means for receiving an input confirmation pulse as an input; The second unit time to generate an extended shift write control signal using the second unit time delayed phase comparison input clock signal having delayed the phase comparison input clock signal by a predetermined unit time, the reference clock signal, and the input confirmation pulse; Expansion shift control signal generating means for receiving a delayed phase comparison input clock signal, the reference clock signal, and the input confirmation pulse as inputs; The phase comparison input clock signal and the unit to generate an extended shift left control signal using the unit time delayed reference clock signal which delays the phase comparison input clock signal and the reference clock signal by a predetermined unit time and the input confirmation pulse; Expansion shift left control signal generation means for receiving a time delayed reference clock signal and the input confirmation pulse; And Using the first lock-in signal as the control signal, before the first lock-in, the shift control signal generated at the output end of the shift left control signal generating means and the output end of the shift light control signal generating means is selected and output, and the first lock-in signal is output. And after the output stage of the shift left control signal generating means selects and outputs a shift control signal generated at the output end of the extended shift left control signal generating means and the output end of the extended shift light control signal generating means, and the shift light. Shift control signal selection means for receiving an output end of the control signal generating means, an output end of the extended shift left control signal generating means, and an output end of the extended shift light control signal generating means as inputs. Phase comparator for a semiconductor memory device comprising a. The method of claim 1, wherein the extended shift light control signal generating means And a predetermined time delay means for delaying the phase comparison input clock signal by a predetermined unit delay time. The method of claim 2, wherein the predetermined time delay means, 2. The phase comparator of claim 1, wherein an input terminal is connected between the two inverters connected in series with the line of the phase comparison input clock signal and one inverter connected between the two inverters connected in series. The method of claim 2, wherein the predetermined time delay means, A phase comparator for a semiconductor memory device, comprising one inverter and one NAND gate. The method of claim 1, wherein the extended shift left control signal generating means, And a predetermined time delay means for delaying the reference clock signal by a predetermined unit delay time. The method of claim 5, wherein the predetermined time delay means, 2. The phase comparator of claim 1, wherein an input terminal is connected between the two inverters connected in series with the line of the phase comparison input clock signal and one inverter connected between the two inverters connected in series. The method of claim 5, wherein the predetermined time delay means, A phase comparator for a semiconductor memory device, comprising one inverter and one NAND gate. The method according to any one of claims 1 to 7, When the rising edge of the phase comparison input clock signal delayed by the unit time delays behind the rising edge of the reference clock signal, and the rising edge of the phase comparison input clock signal precedes the rising edge of the unit time delayed reference clock signal. A phase comparator for a semiconductor memory device, characterized in that the printing. The method according to any one of claims 1 to 7, If the rising edge of the phase comparison input clock signal delayed by the unit time is lower than the rising edge of the reference clock signal, and the rising edge of the phase comparison input clock signal precedes the rising edge of the unit time delayed reference clock signal. And a phase comparator for shifting the state of the output end of the shift light control signal generating means and the output end of the extended shift left control signal generating means. A first step of selecting and outputting a shift control signal generated at an output end of the shift left control signal generating means and at an output end of the shift light control signal generating means before the first lock-in; And A second step of selecting and outputting a shift control signal generated at the output end of the extended shift left control signal generating means and at the output end of the extended shift light control signal generating means after the first lock-in; Control method of a phase comparator for a semiconductor memory device comprising a. The method of claim 10, wherein the second step, A lock-in signal is generated when the rising edge of the phase comparison input clock signal is delayed by the unit time delayed from the rising edge of the reference clock signal, and the rising edge of the phase comparison input clock signal is earlier than the rising edge of the reference clock signal delayed by the unit time. Third step to let Control method of a phase comparator for a semiconductor memory device comprising a. The method of claim 10, wherein the second step, The extended shift light control signal when the rising edge of the phase comparison input clock signal is delayed by a unit time delay than the rising edge of the reference clock signal, and the rising edge of the phase comparison input clock signal is ahead of the rising edge of the reference clock signal which is delayed by a unit time. A third step of transitioning the output stage of the generating means and the output stage of the extended shift left control signal generating means; Control method of a phase comparator for a semiconductor memory device comprising a.