KR100420098B1 - Radio frequency element using Micro Electro Mechanical System and Method of manufacturing the same - Google Patents

Abstract

A piezoelectric drive high frequency switch using a micro electromechanical system includes a silicon substrate having an insulating layer laminated thereon for electrical insulation or a substrate in which an IC using a metal material of refractory material is embedded, and a signal to be transmitted and formed on the insulating layer. A first signal line connected to a first external signal terminal serving as an input terminal or an output terminal of the first signal line, and a second external signal terminal serving as an input terminal or an output terminal of the signal to be transmitted, and switching a signal through physical contact with the first signal line At least one piezoelectric driver including a second signal line, a membrane, a lower electrode, a piezoelectric element, and an upper electrode to drive and switch the second signal line, and a support part connecting the second signal line and the piezoelectric driver to a substrate. Consists of

Description

Radio frequency element using Micro Electro Mechanical System and Method of manufacturing the same

The present invention is limited to the technical limitations on the temperature of the conventional micro electro mechanical system (MEMS), for example, a high temperature process of 1000 ° C. or higher is required in the heat treatment process for stress relief of polysilicon. The present invention relates to a radio frequency device using a microelectromechanical system for achieving integration with a considered IC circuit device, and a method of manufacturing the same.

The metal wiring of the basic IC circuit is not compatible with the high temperature process (above 500 ℃) required by existing MEMS technology because aluminum is used as the main material. In addition, in the case of a CMOS circuit element used as an IC circuit, deterioration of device characteristics due to diffusion at high temperature (900 ° C) between an n-type well and a p-type well is a limitation of current IC circuit technology.

Looking at the integration technology developed by Sandia National Laboratories of America to overcome this problem, the IC circuit device is subsequently fabricated after the MEMS device using the high temperature process is manufactured prior to the trench technology. Proposed technology.

It is possible to overcome the limitations of the high temperature process by this technique, but there are additional technical difficulties as follows.

First, there is a spatial limitation that the manufacturing area of the MEMS device and the IC circuit device must be formed separately. This limitation can be applied in the development of unit devices, but not in the development of an array of devices in which space is limited or in the development of a multipurpose function technology having multiple devices.

Second, in order to form a MEMS device in a space formed by etching a substrate with trench technology and subsequently to form an IC circuit device, the space must be stabilized again at a high temperature. This process is very demanding and makes an IC circuit device. For this purpose, the planarization process of the substrate is a technical limitation.

Third, since the IC circuit process, which is a subsequent process, includes a high temperature process (for example, an activation heat treatment used in implantation) in the IC manufacturing process, it is possible to use a material whose physical properties are deteriorated under the high temperature process even in the selection of a MEMS device. There are no restrictions. Therefore, no piezoelectric material or other sensor material can be used for the MEMS device.

RF devices, variable capacitance capacitors, RF filters, inductors, antennas, and the like in the RF field using the existing MEMS technology are mainly researched in the wireless communication and defense fields. In particular, RF switches and variable capacitance capacitors are receiving attention in the wireless communication field.

Currently, semiconductor switches such as field effect transistor (FET) or pin (PIN) diodes are widely used as RF switches. However, the semiconductor switches have problems such as high power loss when operating and not fully insulated, and researches on MEMS switches have been actively conducted to compensate for the problems of the semiconductor switches. .

The development of RF switches using MEMS can achieve miniaturization and low cost, provide a large dynamic range between on-state and off-state impedances, especially low insertion loss of less than 0.5dB at tens of gigahertz (GHz). In recent years, attention has been increased due to excellent switch characteristics such as insertion loss and high electrical isolation of 30 to 40 dB.

The driving mechanisms used for the RF switch using MEMS are various, such as electromagnetic, magnetic, piezoelectric, electrostatic, and the like. Most of these methods use the electrostatic force, and the beam moves from side to side and up and down, and this method is a direct contact switch and a capacitive switch depending on whether DC current can flow. It is divided into (capacitive switch).

Conventional electrostatic force MEMS switches include cantilever switches, membrane switches, tunable capacitor switches, and the like.

1 is a cross-sectional view of a cantilever switch using a general electrostatic force.

Referring to FIG. 1, a simple operation principle of the cantilever switch 100 using electrostatic force is that when the voltage is applied to the upper electrode 105, the cantilever 104 is prevented by the electrostatic force between the upper electrode 105 and the lower electrode 102. The attractive force acts on the lower electrode 102 and the cantilever 104 is bent.

Then, the signal lines 106 are connected to each other by the contact metal 107 under the cantilever 104. This is the on-state of the switch, and in the off-state, when the voltage applied to the upper electrode 105 is zero, the attraction force between the cantilever 104 and the lower electrode 102 disappears and the cantilever is released by the spring restoring force of the cantilever 104. 104 is raised to be off-state away from the contact metal 107 connecting the two signal lines 106.

However, the above-mentioned electrostatic force RF switch has a stiction due to surface charge between electrodes caused by the electrostatic force switching method, and welding caused by high current flow between the contact metal and the signal line. In addition, there are problems of self acutation in which the cantilever is bent downward due to the generation of unwanted electrostatic force by the RF signal applied to the signal line in the off-state.

To solve these problems, it is necessary to make a cantilever with a high stiffness that is not affected by stiction and self-driving, which requires a driving voltage of 10 to 100 volts. Therefore, the current RF MEMS switch using the electrostatic force is not applied in the commercial wireless communication system requiring a power supply of less than 5 volts, has been limited application in the defense field.

Variable capacitance capacitor is a capacitor that can change capacitance, and is mainly used for adjusting communication frequency.

Currently, a trimmer using a ceramic as a dielectric is used as a variable capacitor used in general. However, there is a limitation in minimizing the size even when using such a bulk ceramic dielectric, there is a disadvantage that the on-chip of the element including the bulk-type variable capacitance capacitor is impossible.

Recently, as the next generation wireless mobile communication system using RF and millimeter-wave bands is rapidly increasing, the necessity of an integrated (IC) variable capacitance capacitor capable of on-chip of devices is increasing. Research into the integration of variable capacitance capacitors includes chemical approaches to improve the characteristics of ferroelectrics and physical approaches to control gaps or areas of dielectric layers using MEMS devices with micron-level operation.

Integrated variable capacitance capacitor using MEMS technology is compatible with CMOS process technology, can achieve mass production and low price through batch process, and also has insertion loss (compared to the integrated circuit diode varactor which is a general IC variable capacitance capacitor). It is characterized by excellent performance and low power consumption, such as low insertion loss, wide capacitance change, and linear change.

Such an integrated variable capacitance capacitor may be applied to a voltage controlled oscillator (VCO), a band pass filter (BPF), a matching circuit, and the like.

A semiconductor diode varactor is mainly used for a voltage controlled oscillator circuit in the conventional RF field, and recently, a variable capacitance capacitor of an electrostatic force driving method manufactured by MEMS technology has been studied, but has the following problems.

2 is a configuration of a voltage controlled oscillator circuit using a semiconductor varactor integrated in a silicon wafer according to the prior art, and the voltage controlled oscillator circuit uses the voltage control characteristic of a p-n junction diode reverse capacitance.

The varactor has a problem in that the loss of V _CO caused by the varactor increases as the frequency increases, because the Q value is low because the series resistance is large, and the range of the variable capacitance value does not exceed 50% of the capacitance value before applying voltage. have. In addition, DC power loss is inevitable in order to operate the varactor, and RF characteristics are deteriorated due to deterioration of the device by bias application.

3 is a view showing a variable capacitor implemented by the conventional MEMS technology, (a) is a plan view, (b) is a cross-sectional view, the structure of aluminum by Darrin J. Young of Berkeley University, etc. A flat plate type variable capacitor is shown as a material.

The device is fabricated using a typical semiconductor process that is compatible with CMOS on a silicon wafer, wherein photoresist (PR) is deposited as a sacrificial layer, aluminum is deposited as a structural layer, patterned and etched. Since the sacrificial layer was removed, a flat variable capacitor having four spring supporting members was implemented. The device may change the capacitance value by changing the distance between both ends of the plate due to the electrostatic force caused by the potential difference applied between the lower electrode and the upper plate.

Equation for this is as follows.

----- (One)

----- (2)

Where C is the capacitance value, ε ₀ is the dielectric constant in vacuum, A is the area of the plate, x is the spacing between the lower and upper electrode plates, Fc is the electrostatic force, and Vc is the voltage applied between the two plates. The equation for the restoring force by the spring is as follows.

----- (3)

Where Ks is the spring constant and Δx is the displacement from the initial position.

The planar variable capacitor has been reported to have a relatively small capacitance value of about 2 to 2.5 pF at a frequency of about 900 MHz and relatively insensitive to mechanical noise. As a result, compared with the semiconductor varactor diode, it has a high Q value and a small phase noise, so it can be seen that there is an effect of improving the performance when applied to a voltage controlled oscillator circuit.

However, the planar variable capacitor of Darrin J. Young has some disadvantages as follows.

First, when driven by electrostatic force, a support spring is required to provide restoring force. However, when the rigidity of the support spring is too small, sufficient restoring force may not be provided between the plate and the lower electrode to overcome the sticking by residual electrostatic force or surface charging, so that the upper plate may not be restored to its original position. Conversely, if the stiffness of the support spring is increased too much, the voltage required to drive the flat capacitor becomes too large (50V or more), and in this case, the power is large, and thus it is difficult to apply to a portable wireless communication device.

Second, the area occupied by the actuator is relatively large compared to the capacitor, and the electrode spacing is not finely adjusted.

Third, the tuning range that can be implemented due to insufficient displacement of the upper plate due to the characteristics of the device using the electrostatic force is less than 15% of the initial capacitance value.

In 1995, a study on switching diaphragms based on MEMS technology using an electrostatic drive method was published by Goldsmith et al., But this method also has an upper electrode when the gap size is smaller than 77% of the original level. There is a limitation that the plate collides with the lower electrode plate.

As a way to secure this, Hue et al. At the University of Colorado proposed a driver consisting of a polysilicon thin film and an arm consisting of a composite of thick thin films. Attempts have been made to adjust the gap using an electro-thermal actuator that is moved back and forth by the difference in thermal expansion caused by. However, this structure has a disadvantage in that the size of the driver is larger than that of the capacitor, and the driving control is not easy.

Tables 1 and 2 below show the characteristics of the piezoelectric drive switch and the variable capacitor in comparison with the electrostatic force driving method.

Piezoelectric Drive Switch Electrostatic force switch Driving voltage (V) 3v Switching speed 10 to 100 ㎲ 100㎲-100㎳ Stiction X O Influence of self-driving X O

<Piezoelectric Drive Switch vs. Electrostatic Force Switch>

Piezo Drive Variable Capacitors Electrostatic Force Variable Capacitors Columbia University Berkeley University Manufacturing method MEMS / Piezoelectric Thin Film (PZT) MUMPs / Polysilicon MEMS / Aluminum Tuning voltage (V) 0 to 3 0 to 4 0 to 3 Cmax./Cmin. More than 3 1.38 1.15 Q factor 6 or more 9.3@1.9GHz 60@1.0 GHz

<Comparison of Piezoelectric Variable Capacitors and Electrostatic Force Variable Capacitors>

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to be compatible with IC circuit elements and to integrate MEMS devices directly on the IC circuit elements. MEMS Processing, hereinafter referred to as SMP).

Another object of the present invention is to provide a structure and driving method using a piezoelectric material for a new RF MEMS device that is compatible with the IC circuit device in a stable process and a manufacturing process accordingly.

It is still another object of the present invention to provide a structure of a piezoelectric drive MEMS variable capacitance capacitor having a low driving voltage and a high tuning range and a method of manufacturing the same, compared to the conventional electrostatic force MEMS plate type variable capacitance capacitor.

In particular, in the present invention, due to the problem that the power loss in the operation of the conventional semiconductor switches as described above is large, complete isolation is not achieved, and a high driving voltage of about 10 to 100 volts of the electrostatic force RF switch using MEMS technology is used. In order to solve the problem that the communication system can not be used, the structure of the RF MEMS switch using a low voltage piezoelectric drive method and a method of manufacturing the same.

1 is a cross-sectional view of a cantilever switch using the electrostatic force of the prior art.

2 is a block diagram of a voltage controlled oscillator circuit using a semiconductor varactor according to the prior art.

3 is a three-dimensional view of a variable capacitance capacitor implemented using a conventional microelectromechanical system.

4 shows a first embodiment of an RF switch according to the invention;

5A and 5B are sectional views taken along the line A-A 'of the first embodiment of the RF switch according to the present invention;

6a to 6h are manufacturing process diagrams of the first embodiment of the RF switch according to the present invention;

Figure 7 shows a second embodiment of the RF switch according to the present invention.

8 shows a third embodiment of an RF switch according to the invention;

9 shows a fourth embodiment of an RF switch in accordance with the present invention;

10 is a plan view of a variable capacitance capacitor according to the present invention.

FIG. 11 is a cross-sectional view taken along line BB ′ of the variable capacitance capacitor of FIG. 10. FIG.

<Explanation of symbols for the main parts of the drawings>

200: RF switch 201: substrate

202: insulating layer 203: first signal line

204: support portion 205: second signal line

206: membrane 207: lower electrode

208: piezoelectric element 209: upper electrode

210: air bridge 700: variable capacitance capacitor

701: substrate 702: insulating layer

703: lower parallel electrode plate 704: support

705: upper parallel electrode plate 706: membrane

707: lower electrode 708: piezoelectric element

709: upper electrode 710: external visor pad

711: common electrode pads 712, 713: air bridge

SMP according to the present invention is a standardized manufacturing design and manufacturing process technology of unit processes for manufacturing MEMS unit devices. The SMP is also a low temperature MEMS process technology compatible with IC circuit devices and a manufacturing design and manufacturing process technology that enables monolithic integration directly into IC circuit devices.

SMP according to the present invention is configured as follows.

SMP1: Manufacturing process and structure design technology of membrane that can control the stress by itself and make a structural area for manufacturing MEMS devices.

SMP2: Manufacturing process and structure design technology of piezoelectric and electrode materials that provide mechanical displacement for fabricating MEMS devices.

SMP3: Manufacturing process and structure design technology of sacrificial layer that provides free space (air gap or space) for free movement in manufacturing MEMS devices.

SMP4: Manufacturing process and structure design technology of air bridge for electrical connection between structurally separated elements in manufacturing MEMS devices.

SMP5: Planarization technology of MEMS devices.

SMP6: Manufacturing process and structure design technology of refractory metals for integrating MEMS devices directly into IC circuits.

Hereinafter, the six SMPs according to the present invention will be described in detail.

SMP1 has a structure in which a stress-controlled membrane layer is deposited on the planarized surface using the planarization technique mentioned in SMP5. As shown in FIG. 6E, the structure can prevent the uniformity of the cantilever type structure that can be generated due to the difference in stress concentration and bending step generated in the layer deposited on the bent phase where the planarization process is not performed.

According to the experimental results, the degree of uniformity in the cantilever-type structure connected horizontally and flatly in the above-mentioned support part is 30 times in the area of 70x 50mm when the initial bending state of the drive part composed of multilayer thin films is adjusted horizontally (0 °). It can be adjusted within 0.02 ° in 50,000 experimental cantilevers (unit length: 100mm). The membrane layer is formed of silicon nitride (SiNx) to have a thickness of about 1000 to 8000 kPa using low pressure chemical vapor deposition (LPCVD). The silicon nitride deposited by the above method can control the stress of the silicon nitride layer from compression to tensile strength by adjusting the supply amount of the supplying gas to be supplied and controlling the deposition temperature (from 3 × 10 ⁹ (tensile) to 8 × 10 ⁹ dyn). / cm ² ). This technique is used to control the stress of the cantilever, referred to as the drive consisting of multilayer thin films. At this time, the deposition temperature of silicon nitride is 750-850 degreeC, and the refractive index of a silicon nitride film is adjusted to about 1.98-2.1.

In the SMP2 process, an upper electrode layer 307 and a lower electrode layer 305 formed of platinum (Pt), tantalum (Ta) or titanium (Ti), which improve the orientation of the crystal direction of the piezoelectric material, are formed (FIG. 6E). Reference). The deposition of the electrode material is carried out by a sputtering method, at the same time performing a heat treatment of about 200 ~ 300 ℃ at the time of deposition, in particular, when forming the lower electrode tantalum or titanium introduced into the adhesive layer is rapid thermal treatment of oxygen atmosphere (RTA) By heat treatment by annealing method, the orientation of the crystal direction of the platinum electrode and the piezoelectric layer can be improved. This is very important in applications for displacement drive using piezoelectric properties. As the orientation in the crystal direction is improved, the piezoelectric characteristics are improved.

The piezoelectric layer is formed to have a thickness of about 0.1 to 1 μm using a piezoelectric material such as PZT (PbZrTiO ₃ ) or PLZT (PbLaZrTiO ₃ ). The piezoelectric layer is formed using a sol-gel method, a sputtering method, or a chemical vapor deposition (CVD) method, and then crystallized by a rapid heat treatment method. In the piezoelectric material deposition method, a nuclear seed layer is introduced to minimize the inconsistency of the lattice parameter between the platinum and the piezoelectric material, thereby improving nucleation and improving the characteristics of the piezoelectric material. RTA) allows a perovskite structure without secondary phase. This nucleation layer uses PT (PbTiO ₃ ) as a material having crystallinity similar to that of the piezoelectric layer to be deposited. In case of manufacturing by Sol-gel method, it consists of annealing process at 200 ℃ ~ 400 ℃ and below 700 ℃ which is drying condition for removing solvent. The temperature at the time of deposition of the piezoelectric material is adjusted to 300 ° C. to 400 ° C., followed by a heat treatment at 700 ° C. or lower through rapid heat treatment.

This process is a process technology used to form the upper electrode or the lower electrode in the present invention as a process technology for etching the electrode material. High density plasma type etching equipment using chloride gas (Cl ₂ , BCl ₃ ) as main etching gas and mixed gas using inert gas (Ar or He) Etch at low pressure (<10 mTorr) using. The etching rate of this process is 900-1500 kW / min, and the mixing ratio of chloride gas / inert gas is (10-30 sccm) / (110-140 sccm). And etching uniformity is adjusted to 3% or less.

In the present invention, the piezoelectric element 208 is formed as a process technology for etching the piezoelectric material. Fluorinated gases (SF ₆ , CF ₄ , CHF ₃ ) as the main etching gases and of mixed gases using mixed gases using inert gases (Ar or He), or chlorinated gases ( Etching is performed at low pressure (10 mTorr or less) using a high density plasma type etching equipment using Cl ₂ , BCl ₃ ) as the main etching gas and a mixed gas using an inert gas (Ar or He). In the case of using fluorinated gas, the etching rate of this process is 2500-3500 Pa / min, and the mixing ratio of fluorine gas / inert gas is (20-40 sccm) / (30-60 sccm). And etching uniformity is adjusted to 3% or less. In the case of using chlorine gas, the etching rate of this process is 2200-3200 kW / min, and the mixing ratio of chlorine gas / inert gas is (20-40 sccm) / (0-20 sccm). And etching uniformity is adjusted to 3% or less.

In the SMP3 process, a sacrificial layer is formed by depositing polycrystalline silicon (polysilicon) material at a thickness of about 1.0 to 3 μm using a low pressure chemical vapor deposition (LPCVD) method on a portion where an air gap is to be formed. The deposition temperature is 600 ° C. to 700 ° C. and the adjusted sacrificial layer has a stress of 2 × 10 ⁹ dyn / cm ² or less (tensile on silicon wafer). The sacrificial layer thus formed is removed using a xenon fluoride (XeF ₂ ) vaporization etching process to form an air gap at the position of the sacrificial layer. Xenon fluoride (XeF ₂ ) is solid at room temperature and atmospheric pressure. However, it sublimates at low pressure or a little high temperature to become a gas. This property is used to vaporize using xenon fluoride under low pressure atmosphere. The vaporized xenon fluoride and polysilicon are reacted in a vaporized state and removed by vaporizing them with xenon gas and silicon fluoride gas. During the etching, the process may be performed by an etching method of continuously supplying vaporized xenon fluoride and by supplying vaporized xenon fluoride with a predetermined time interval. This process is very stable in the case of silicon oxide film and is almost impossible to etch and is stable with many materials (aluminum, gold, oxide and nitride), and is suitable for removing metal components such as silicon or tungsten.

In the SMP4 process, air bridges are used for the electrical connection of elements that are structurally separated from the MEMS. In one embodiment of the present invention, when the upper electrode and the common electrode are connected, an air bridge ensures insulation with other adjacent layers by using air having excellent insulation, and makes metal contact. This makes it possible. This technique is similar to the via contact used in semiconductor processes. However, in the case of using another insulator by the conventional method such as in the semiconductor process, the insulation and dielectric constant of the piezoelectric material is better than the conventional dielectric film (dielectric film) is used to cause the degradation of the properties of the piezoelectric material. In addition, the topology generated on the surface causes a decrease in the properties of the dielectric film, which causes several stepped stepped structures upon deposition of the applied dielectric film. In the case of depositing a metal film after etching for via contact directly on top of this, a lot of over etching is required to remove side wall metal between unwanted bends. However, an air bridge using photoresist is air-insulated and can be completely insulated, and because it deposits contact metal in the state of temporary surface planarization by photoresist, it is stepped. There is no step structure. As a result, metal etching is a planarized planar process, which does not require a lot of overetching.

In the SMP5 process, an additional process is introduced before the planarization process that is generally used to obtain the optimum planarization by minimizing the surface area of the material to be planarized before the planarization process discussed in the present invention (see FIG. 6C).

The uniformity of the planarization process may be improved by the method described below by minimizing the surface area of the material for planarizing the structure as shown in FIG. 6C through the photolithographic process and the etching process before the planarization process. In addition, although not shown in the drawings, the space in which each device is located and the arrangement between the spaces are very important design techniques in the planarization process. Uniformity can be improved by forming a dummy structure having the same structure as a space in which an element is located. At this time, the dummy structure is composed of a material to be flattened during the planarization process.

In the case of chemical mechanical polishing (CMP) during the planarization process, the initial polishing rate can be relatively increased because the structure of the above-mentioned form is minimized by minimizing the cross section of the material to be polished (the above-mentioned dry etching is not performed). In this case, it takes a lot of time because the sacrificial layer remains on the front of the substrate.)

In addition, the surface of the sacrificial layer is planarized by an etching-back process using a spin on glass (SOG) or a spin on polymer (SOP) method. The thickness of the spin on glass and the polymer layer is the same principle. The thickness of the layer to be removed by etching back can be made relatively thin, thereby reducing the etching back process time.

This structural improvement is common to both processes, and by minimizing the process time of both processes, the process time or the thickness of the layer is increased when the uniformity of polishing or etching of equipment performing the two processes is maintained. Cumulative thickness deviation is increased. For example, if the uniformity of the two process equipment is 1%, the uniformity is always 1% when the thickness of 3,000 and 90,000 is performed, but the accumulated thickness deviation is 30 and 900. This structure and process technology can maximize the uniformity of the polishing or etching back.

In the SMP6 process, it is composed of tungsten (W), titanium (Ti), titanium nitride (TiN) or titanium nitride (TiON), which are metal materials of refractory materials, and is deposited by sputtering or chemical vapor deposition (CVD). The thickness of the film is 3000 kPa to 7000 kPa. This film consists of an adhesive film, a metal film, and a diffusion barrier film. The adhesive film improves structural stability and electrical performance by improving the adhesion between the above-mentioned metal film and an oxide film or a silicon substrate (when manufacturing a MOS). The diffusion barrier layer removes silicon (Si) diffusion between tungsten and other thin films to reduce the occurrence of undesired solid reaction during the high temperature process in the subsequent process to prevent the degradation of electrical performance. Titanium (Ti) is used as the adhesive film and the thickness is about 100 to 700Å, and titanium nitride or titanium nitride is used as the diffusion barrier and the thickness is about 300 to 1000Å. In addition, tungsten (W) is used as the main metal for the electrical connection. The overall stacking order is Ti-TiN-W-TiON, Ti-TiN-W-TiN, or Ti-TiON-W-TiON.

Such metals allow for thermal ranges in subsequent processes to enable the fabrication of MEMS devices. In addition, in the manufacture of integrated single-chip, the film made of metal material of refractory material is used as the metal lead of the IC circuit element, enabling the direct integration of the device using the new MEMS process described in the present invention onto the IC circuit element.

Dry etching of refractory metal materials is carried out using a mixed gas using fluoride gas (SF ₆ , CF ₄ , CHF ₃ ) as the main etching gas, and etching is performed at low pressure (10 mTorr or less) using a high density plasma type etching equipment. Perform. This etching process performs etching to have a smoothly inclined metal cross section by adjusting the above-mentioned gas and the RF source power of the equipment. In addition, after the etching process, a heat treatment is performed to control the stress of the metal film and to alloy between the metals. The heat treatment process temperature is performed at 400 ℃ to 500 ℃, nitrogen (N ₂ ) and oxygen (O ₂ ) is used as the atmosphere control gas.

The piezoelectric drive RF MEMS switch of the present invention using the SMP technique described above,

A silicon substrate in which an insulating layer for electrical insulation is laminated or a substrate in which an IC using a metal material of a refractory material is embedded;

A first signal line formed on the insulating layer and connected to a first external signal terminal which is an input terminal or an output terminal of a signal to be transmitted;

A second signal line connected to a second external signal end serving as an input end or an output end of the signal to be transmitted and capable of switching a signal through physical contact with the first signal line;

At least one piezoelectric driver configured to drive and switch the second signal line, and to stack a membrane, a piezoelectric element, a lower electrode, and an upper electrode; an air bridge for applying a driving voltage to the piezoelectric driver; And a support part connecting the second signal line and the piezoelectric driver to the substrate, wherein the piezoelectric driver is applied to the substrate when the voltage is applied to the upper electrode and the lower electrode disposed above and below the piezoelectric element through the air bridge. And the switch is turned OFF when the voltage is shorted, and the first signal line and the second signal line are physically in contact with each other to be turned on to switch. The piezoelectric drive RF MEMS switch according to the present invention is also switched. As another embodiment of

A silicon substrate in which an insulating layer for electrical insulation is laminated or a substrate in which an IC using a metal material of a refractory material is embedded;

A signal line formed on the insulating layer, the signal line comprising an input terminal and an output terminal of a signal to be transmitted;

A contact metal capable of switching the signal through physical contact with an input or output terminal of the signal to be transmitted;

At least one piezoelectric driver including a membrane, a piezoelectric element, a lower electrode, and an upper electrode to drive and switch the contact metal;

It consists of a support part which connects the said piezoelectric drive part to a board | substrate.

In the RF switch according to the present invention, a bias is applied to the lower electrode as a driving signal, and the upper electrode is connected to the common electrode, thereby generating an electric field between the upper and lower electrodes. The piezoelectric elements stacked between the upper and lower electrodes by this electric field cause deformation. Accordingly, the piezoelectric driver is inclined at a predetermined angle so that the second signal line or the contact metal positioned at the lower end of the piezoelectric driver performs a non-contact switching state between the first signal line or the signal input terminal and the output terminal.

In addition, the variable capacitance capacitor according to the present invention,

A substrate in which an insulating layer is laminated to prevent electrical loss through the substrate, or a substrate in which an IC using a metal material of a refractory material is embedded;

A lower parallel electrode plate formed on the insulating layer;

An upper parallel electrode plate forming a capacitor by maintaining a predetermined gap through the lower parallel electrode plate and an air gap;

Two or more piezoelectric driving parts attached to the upper parallel electrode plate and having a stacked structure of a membrane, a lower electrode, a piezoelectric element, and an upper electrode; And,

And a supporting part connecting the piezoelectric driving part to the substrate, wherein the piezoelectric element moves in a vertical direction by a voltage applied to the upper electrode and the lower electrode, thereby moving the upper parallel electrode plate vertically. The capacitance is varied by adjusting the gap of the parallel electrode plate.

In the variable capacitor according to the present invention, a bias is applied to the lower electrode as a driving signal and the upper electrode is connected to the common electrode, thereby generating an electric field between the upper and lower electrodes. The piezoelectric elements stacked between the upper and lower electrodes by this electric field cause deformation. Accordingly, the piezoelectric driver is inclined at a predetermined angle, and thus the capacitance is controlled by adjusting the air gap between the lower parallel electrode plate disposed at the lower end of the piezoelectric driver and the upper parallel electrode plate connected to the piezoelectric driver.

Hereinafter, RF elements according to the present invention will be described in detail with reference to the accompanying drawings. First, the structure and manufacturing method of the RF switch will be described, and then the structure of the variable capacitor and the manufacturing method thereof will be described in detail.

4 is a plan view of a first embodiment of an RF switch according to the present invention, and FIGS. 5A and 5B are cross-sectional views taken along line AA ′ of FIG. 4.

As shown in FIGS. 4, 5A, and 5B, the first embodiment of the RF switch 200 according to the present invention may be configured to electrically open and close the first external signal line 213 and the second external signal line 214. The first signal line 203 and the second signal line 214 electrically connected to the external signal line 213, the second signal line 205 electrically connected to the second signal line 214, the electric substrate 201, and the first signal line 203 And a piezoelectric driver 250 that electrically opens and closes the second signal line 205 by physical contact.

The piezoelectric driver 250 has a stacked structure of a membrane 206, a lower electrode 207, a piezoelectric element 208, and an upper electrode 209, and the piezoelectric driver 250 and the second signal line 205 are supported. 204 is connected to and supported by the substrate.

The first signal line 203 is connected to the first external connection line 213 through the first via hole 210. The second external signal line 214 is formed of the same metal layer as the second signal line 205.

The upper electrode 209 in the piezoelectric driver 250 is connected to an external common power line 217 through an air bridge 211, and the lower electrode 207 is connected to an external bias power source through the air bridge 212. It is connected to the line 216 to perform an electrical switching role.

5A and 5B are diagrams illustrating an operating principle of the RF switch 200 according to the first embodiment of the present invention.

As illustrated, in the RF switch 200 according to the present invention, the second signal line 205 located under the driving unit 250 is controlled by the stress control within the driving unit 250 in the initial state in which the sacrificial layer 302 is removed. It is in electrical contact with the signal line 203 and is electrically connected.

When a constant voltage is applied to the upper electrode 209 and the lower electrode 207 located above and below the piezoelectric element 208 to turn off the switch, the driving unit 250 causes the displacement to move upward as shown in FIG. 5B to be parallel to the substrate 201. As a result, the second signal line 205 may be physically separated from the first signal line 203 to obtain an electrical opening.

Hereinafter, a method of manufacturing an RF switch according to a first embodiment of the present invention will be described in detail with reference to the accompanying drawings.

6A to 6H show a manufacturing process diagram of the RF switch according to the first embodiment of the present invention.

6A is a cross-sectional view taken along the line AA ′ of FIG. 5 showing a state after the formation of the first signal line 203 in the RF switch according to the present invention.

As shown, after the cleaning, the insulating layer 202 is formed on the silicon substrate or the substrate 201 in which the IC using the metal material of the refractory material is embedded. In this case, the insulating layer 202 may be formed by using a low pressure vapor deposition (LPCVD) method, a dry or wet oxidation method, or an oxide, such as a low temperature oxide (LTO) or a thermal oxide film. It is formed to a thickness of about 12000 kPa. The insulating layer 202 prevents the silicon substrate from being damaged during subsequent processing and maintains electrical isolation between the silicon substrate 201 and the first signal line 203 described later. Subsequently, after forming the first signal layer (not shown) on the insulating layer 202, the first signal layer is patterned to form the first signal line 203. The above process uses the SMP6 process described above, and is intended to form a signal line having thermal stability, and is patterned by a photolithography method and forms the first signal line 203 by dry etching referred to in SMP6. The first signal line 203 is an input terminal or an output terminal of a signal to be transmitted.

6B is a cross-sectional view taken along line AA ′ of FIG. 4 illustrating a state after depositing a support layer 301 for forming a support 204 to be described later in the RF switch according to the present invention.

As shown, the support layer 301 is formed on the insulating layer 202 including the first signal line 203. The support layer 301 is formed using a low pressure chemical vapor deposition (LPCVD) method or an atmospheric pressure chemical vapor deposition (APCVD) method to form a thickness of about 1 to 2 μm. As the oxide, a silicon oxide film (BPSG) doped with boron (B) and phosphorus (P) or a silicon oxide film (PSG) doped with phosphorus (P) is used. The film is deposited at about 350 ° C to about 450 ° C. At this time, the refractive index of the film is about 1.42 to about 1.47. The oxide film should serve as a polishing stop film in chemical mechanical polishing to be used in the surface planarization process, which will be discussed in a subsequent process, or an anti-etching film during etching back using a method using spin on glass (SOG) or spin on polymer (polymer). play a role, and removing technique fluoride xenon (XeF ₂₎ vaporization, and perform the etching film role in the etching process, and a stable stress control during stress control of the laminated film (mutil-layer) for use in removing the sacrifice layer in the final step In this case, the stress of the membrane is adjusted to be 2 × 10 ⁹ dyn / cm ² or less.

The oxide film 301 is patterned by a photolithography method and etched by dry etching. This is a process for forming a portion of the support layer 301 in which the air gap 215 will be formed in a subsequent process. In this case, the dry etching is performed under a mixed gas of fluorine gas (SF ₆ , CF ₄ , CHF ₃ ) and an inert gas and using a reactive ion etching (RIE type) etching equipment under a pressure of 300 to 2000 mTorr. In the etching process, the photoresist is adjusted during patterning by a photolithography method to have a smooth inclined surface, thereby performing etching to have a smoothly controlled inclined oxide film cross section during the etching process.

Subsequently, the sacrificial layer 302 is deposited on the insulating layer 202, the first signal line 203, and the support (not shown), that is, the entire surface of the substrate 201. It is formed by the SMP3 method.

6C is a cross-sectional view taken along line AA ′ of FIG. 4 illustrating a state in which a sacrificial layer 302 is patterned by a photolithography method and etched by dry etching in an RF switch according to the present invention. This process has a structure that improves the planarization process as described in SMP5.

The above patterning and dry etching is carried out in a similar manner as described in the previous process. This illustrates the cross section before performing the planarization process. The subsequent process, the planarization process, is carried out as described in SMP5.

FIG. 6D shows a cross-sectional view showing a state after depositing the second signal layer 303 for forming the second signal line (not shown).

The second signal layer 303 is deposited on top of the planarized sacrificial layer 302 and on the support 204, wherein the second signal layer 303 is formed by depositing in the manner described in SMP6.

6E illustrates a cross-sectional view of the RF switch according to the present invention after the deposition of the second signal layer 303 and the formation of the upper electrode layer 307 by the above-described continuous deposition process.

Referring to the detailed process for each layer, the membrane layer 304 by the method described in SMP1 to form a membrane (not shown) of a piezoelectric driver (not shown) on top of the second signal layer 303. Deposit. Subsequently, the lower electrode layer 305, the piezoelectric layer 306, and the upper electrode layer 307 are sequentially formed by the method described in SMP2.

6F illustrates the formation of the upper electrode 209 to the second signal line 205 through patterning and etching of the upper electrode layer 307 to the second signal layer 303 using the photolithographic method step by step. Indicates the state.

Specifically, the upper electrode layer 307, the piezoelectric layer 306, and the lower electrode layer 305 of FIG. 6E are etched by the etching method described in SMP2 to etch the upper electrode 209, the piezoelectric element 208, and the lower electrode 207. ), A bias line 215, and an external bias power line 216 are formed. Subsequently, the membrane layer 304 and the second signal layer 303 of FIG. 6E are sequentially etched to form a membrane 206 to complete the piezoelectric driver, and the second signal line 205 and the second external connection signal line 214 are etched. To form. Finally, although not shown in FIG. 4, as shown in FIG. 4, the support part 204 is patterned and etched in a square shape so that a part of the first signal line 203 is exposed to form the first via hole 210. .

At this time, the formation of the membrane 206 and the first via hole 210 is performed using a mixed gas of fluorine gas (SF ₆ , CF ₄ , CHF ₃ ) and an inert gas as an etching gas and 300 using a reactive ion etching type etching equipment. Performed under a pressure of -2000 mTorr, the second signal line 205 is formed using the etching process described in SMP6.

FIG. 6G illustrates an air bridge 211 between the upper electrode 209 and an external common power line (not shown) using metal in a portion of the second via hole 219 formed in the RF switch according to the present invention. 4 is a cross-sectional view taken along line AA ′ of FIG. 4, which is omitted in the drawing. However, the first external connection line 213 is formed by using a metal in the formation portion of the first via hole 210 of FIG. 4. Form simultaneously.

In other words, referring to FIGS. 6G and 4, for the electrical connection between the upper electrode 209 and the external bias power line 216 and between the lower electrode 207 and the bias line 215, an SMP4 process is used. Air bridges 211 and 212 in the form of legs suspended in the air are formed.

6H is a cross-sectional view illustrating a state after removing a sacrificial layer using the sacrificial layer removing technique described in SMP3. In the figure, reference numeral 212 denotes an air bridge formed after the sacrificial layer is removed.

7 is a plan view illustrating an RF switch according to a second embodiment of the present invention. Referring to FIGS. 7 and 5A, the RF switch 400 according to the second embodiment of the present invention may include a second signal line 405. It has a structure having two piezoelectric driving units 450 and 450 on the left and right sides of the structure. In this structure, the signal loss is less toward the driving unit and the interference noise due to the bias is smaller than that of the first embodiment.

In the structure of the first embodiment of FIG. 5A, when the switch is in the on-state and a signal comes into the second signal line 205 through the first signal line 203, the induced current is directed to the lower electrode 207 on the thin membrane 206. This induced current leads to power loss, and in order to prevent this, in the second embodiment, the driving units 450 and 450 are designed not to overlap the second signal line 405. Therefore, the structure of the RF switch according to the second embodiment can prevent the signal from being lost toward the driver.

8 and 9 show RF switches 500 and 600 according to the third and fourth embodiments of the present invention having modified structures of the first and second embodiments shown in FIGS. 4 and 7.

The piezoelectric actuators 550 and 650 of the RF switch according to the third and fourth embodiments may include contact metals 506 and 606, membranes 507 and 607, lower electrodes 508 and 608, and piezoelectric elements 509 and 609. And the upper electrodes 510 and 610, and the contact metals 506 and 606 of the piezoelectric driving units 550, 650 and 650 are connected to the first signal lines 503 and 603 and the second signal lines according to the deformation caused by the bias applied. Contacts 504 and 604 and is configured to perform an electrical switching role.

The manufacturing process of the RF switches according to the second, third, and fourth embodiments of the present invention shown in FIGS. 7 to 9 is the same as the manufacturing process of the RF switch according to the first embodiment and will not be described separately.

10 is a plan view of a variable capacitance capacitor according to the present invention, and FIG. 11 is a cross-sectional view taken along line BB ′ of FIG. 10.

As shown, the variable capacitance capacitor 700 according to the present invention is a silicon substrate 701 or a substrate containing an IC using a metal material of the refractory material formed on top of the insulating layer 702 to prevent electrical loss; A lower parallel electrode plate 703 made of refractory metal, an upper parallel electrode plate 705 made of refractory metal positioned vertically with the lower parallel electrode plate 703 and an air gap 715 interposed therebetween, and Two or more piezoelectric drivers 750 for moving the parallel electrode plate 705 up and down to change capacitance, and a support part 704 for supporting the piezoelectric drivers 750 connected to the upper parallel electrode plate 705. It is made, including.

Although not shown in the drawings, a via hole for connecting the lower parallel electrode plate 703 and the lower terminal line is formed in the support part 704, and the lower parallel electrode plate 703 has an air bridge through the via hole formed in the support part. It is a metal that is formed during manufacturing and is connected to the lower terminal line.

The piezoelectric driver 750 includes a piezoelectric element 708, a lower electrode 707 and an upper electrode 709 for applying a voltage difference across both ends of the piezoelectric element 708, and a membrane 706 for structural support. The upper balance electrode plate is connected to the external upper terminal line 716 through the upper terminal line 714 positioned below the piezoelectric driver 750, and the lower electrode 707 of each piezoelectric driver 750 is externally biased. The upper electrode 709 of each piezoelectric driver 750 is connected to the common electrode pad 711 through each air bridge 712.

The variable capacitor 700 according to the present invention uses air as a dielectric between the upper parallel electrode plate 705 and the lower parallel electrode plate 703. When a bias is applied to the lower electrode 707 of each piezoelectric driver 750 and a common electrode is applied to the upper electrode 709, the piezoelectric element 708 contracts in a direction perpendicular to the electric field. As a result, the four piezoelectric driving units 750 are inclined at a predetermined angle. As a result, the upper parallel electrode plate 705 moves up and down, and thus the capacitance changes as the gap between the parallel electrode plates changes.

In the method of manufacturing a variable capacitor according to the present invention, first, an insulating material is deposited on a silicon substrate 701 to form an insulating layer 702. Subsequently, after forming the lower parallel electrode plate 703, the support part 704 is formed. Subsequently, a sacrificial layer is formed to form an air gap. Formation of each structure described above is the same as the manufacturing process of the above-described RF switch.

Next, a planarization process is performed by using a technique used in the manufacturing process of the RF switch, and the lower parallel electrode plate 703, the membrane layer, the lower electrode layer, the piezoelectric layer, and the upper electrode layer are sequentially deposited and then etched in the reverse order. The upper electrode 709, the piezoelectric element 708, the lower electrode 707, and the membrane 706 are formed. At this time, the method of forming each is the same as the case of the above-described RF switch.

Finally, an air bridge is formed using the SMP4 process between the upper electrode 209 and the common electrode line, and between the lower terminal line and the lower parallel electrode plate, and the sacrificial layer is removed by the process described in SMP3. Complete 700).

According to the present invention, it is possible to provide a comprehensive standard MEMS process (hereinafter referred to as SMP) which is compatible with IC circuit elements and can integrate MEMS elements directly on the IC circuit elements.

In addition, according to the present invention can reduce the size of the device, reduce the production cost, eliminate the difficulty of packaging such as mechanical fine-tuning, minimize the occurrence of parasitic circuits, and the device according to the connection between each functional device It is possible to prevent deterioration of characteristics.

The piezoelectric drive RF switch described in the present invention has excellent switching characteristics such as low insertion loss of less than 0.5 dB and high electrical isolation of 30 to 40 dB at tens of gigahertz (GHz), and can be operated at a low driving voltage to enable portable wireless. Applicable in communication systems.

In addition, as described above, the piezoelectric drive type integrated variable capacitance capacitor of the present invention can secure a linear capacitance change due to the piezoelectric drive type, reduce noise components with a substrate, and secure a Q value of 10 or more. Can be. In addition, the driving unit is located in the same area as the capacitor has the effect of reducing the area there is an effect that can contribute to the miniaturization of the RF band wireless communication mobile system.

Claims (14)

A silicon substrate in which an insulating layer is laminated for electrical insulation, or a substrate in which an IC using a metal material of a refractory material is embedded; A first signal line formed on the insulating layer and connected to a first external signal terminal which is an input terminal or an output terminal of a signal to be transmitted; A second signal line connected to a second external signal end serving as an input end or an output end of the signal to be transmitted, and capable of switching a signal through physical contact with the first signal line; At least one piezoelectric driver having a stacked structure of a membrane, a lower electrode, a piezoelectric element, and an upper electrode to drive and switch the second signal line; An air bridge for applying a driving voltage to the piezoelectric driving unit; A support part connecting the second signal line and the piezoelectric driver to the substrate; When a voltage is applied to the upper electrode and the lower electrode positioned above and below the piezoelectric element through the air bridge, the piezoelectric driving part is parallel with the substrate, and the switch is turned off. When the voltage is not applied, the first signal line And the second signal line is physically in contact with the piezoelectric drive high frequency switch using the micro electromechanical system, characterized in that for switching. A substrate in which an insulating layer is laminated to prevent electrical loss through the substrate, or a substrate in which an IC using a refractory metal material is embedded; A lower parallel electrode plate formed on the insulating layer; An upper parallel electrode plate for forming a capacitor by maintaining a predetermined gap through the lower parallel electrode plate and an air gap; Two or more piezoelectric driving parts attached to the upper parallel electrode plate and having a stacked structure of a membrane, a lower electrode, a piezoelectric element, and an upper electrode; An air bridge for applying a voltage to the upper electrode and the lower electrode; A support part connecting the piezoelectric driver to the substrate; The piezoelectric element is moved in the vertical direction by the voltage applied to the upper electrode and the lower electrode, thereby changing the capacitance by adjusting the gap between the upper and lower parallel electrode plates by moving the upper parallel electrode plate up and down. Variable capacitance capacitors using microelectromechanical systems. Providing a substrate in which an IC is built using a silicon substrate or a metal material of a refractory material, Forming an insulating layer on the substrate; Forming a first signal layer on the insulating layer and then patterning the first signal layer to form a first signal line serving as an input terminal or an output terminal of a signal to be transmitted; Forming a support layer on the insulating layer including the first signal line; Depositing a sacrificial layer over the entire surface of the insulating layer, the first signal line and the support upper substrate; Planarizing the sacrificial layer; Forming a second signal layer over the planarized sacrificial layer and over the support; Sequentially forming a membrane layer, a lower electrode layer, a piezoelectric layer, and an upper electrode layer on the second signal layer; Patterning the upper electrode layer, the piezoelectric layer, and the lower electrode layer to form an upper electrode, a piezoelectric element, a lower electrode, a bias line, and a common electrode line; Forming a membrane by sequentially etching the membrane layer and the second signal layer to complete a piezoelectric driving part, and forming a second signal line and a second external connection signal line; Forming a first via hole by patterning and etching the support part in a rectangular shape so that a part of the first signal line is exposed; Forming an air bridge in the form of a bridge floating in air for electrical connection between the upper electrode and the common electrode line and between the lower electrode and the bias line; A method of manufacturing a piezoelectric drive high frequency switch using a microelectromechanical system comprising the step of removing the sacrificial layer. 4. The piezoelectric driven high frequency switch of claim 3, wherein the membrane layer is a silicon nitride (SiNx) layer formed to have a thickness of about 1000 to 8000 Pa by a low pressure chemical vapor deposition (LPCVD) method. Manufacturing method. The microelectromechanical system according to claim 3, wherein the upper electrode layer and the lower electrode are formed by sputtering of platinum (Pt), tantalum (Ta) or titanium (Ti) at a deposition temperature of 200 to 300 ° C. Method for manufacturing a piezoelectric drive high frequency switch using. The method of claim 5, wherein tantalum or titanium introduced into the adhesive layer when the lower electrode is formed is rapidly thermally treated in an oxygen atmosphere. The piezoelectric driving high frequency using a micro electromechanical system according to claim 3, wherein the piezoelectric layer is formed to a thickness of 0.1 to 1 탆 using PZT (PbZrTiO ₃ ) or PLZT (PbLaZrTiO ₃ ) and crystallized by a rapid heat treatment method. Method of manufacturing a switch. The method of manufacturing a piezoelectric drive high frequency switch using a microelectromechanical system according to claim 7, wherein the nucleation layer is shaped to minimize the inconsistency of crystal lattice between platinum and the piezoelectric material. The microelectromechanical system according to claim 3, wherein the sacrificial layer is formed by depositing a polycrystalline silicon material on a portion where an air gap is to be formed by using a low pressure chemical vapor deposition method with a thickness of about 1.0 to 3 µm. Method of manufacturing piezoelectric drive high frequency switch using. 10. The method of claim 9, wherein the removing of the sacrificial layer is performed by a xenon fluoride (XeF ₂ ) vaporization etching process. 4. The piezoelectric drive of the piezoelectric drive high frequency switch according to claim 3, wherein the air bridge is formed such that there is no stepped structure by depositing a connecting metal in a state where temporary surface planarization is performed by photoresist. Manufacturing method. 4. The piezoelectric drive high frequency according to claim 3, wherein the metal material of the refractory material is tungsten (W), titanium (Ti), or titanium nitride (TiN) and titanium nitride oxide (TiON). Method of manufacturing a switch. The method of claim 12, wherein the metal material of the refractory material is stacked in order of Ti-TiN-W-TiON, Ti-TiN-W-TiN, or Ti-TiON-W-TiON. Method of manufacturing piezoelectric driven high frequency switch. The method of claim 11 or 12, wherein the metal material of the refractory material using a fluorinated gas (SF ₆ , CF ₄ , CHF ₃ ) as an etching gas, the etching is performed at low pressure using a high-density plasma type etching equipment. A method of manufacturing a piezoelectric drive high frequency switch using a micro electromechanical system characterized in that.