KR100416799B1 - UTOPIA interfacing method between two slave mode devices - Google Patents

Abstract

The present invention discloses a utopian interface method between slave mode elements among asynchronous transfer mode (hereinafter, referred to as ATM) elements.

In this utopia interface method, a first (OCA) signal indicating that there is a cell to transmit from a transmitting ATM element is input in an active state and a second (ICA) indicating that there is a cell to receive from a receiving ATM element. When a signal is input in an active state, the interface circuit outputs an active third (ORDENB) signal to the transmitting ATM element such that the transmitting ATM element transmits cell data, and the receiving ATM element transmits cell data. A first step of outputting an active fourth (IWRENB) signal to the receiving ATM device to receive a signal; and transmitting the first and second cell data from the transmitting ATM device to the receiving ATM device. If any one of the signals transitions to a non-active state, the interface circuitry sends the third and fourth signals such that all words of the cell data are transmitted. A second step of maintaining an active state, and after all words of the cell data have been transmitted, the interface circuit transitions the third signal to a non-active state and transitions the fourth signal to a non-active state And a third step of stopping cell data transfer between ATM elements.

Description

Utopia interface method between slave mode devices {UTOPIA interfacing method between two slave mode devices}

The present invention relates to a utopian interface method for matching between two devices operating in a slave mode among asynchronous transfer mode (hereinafter, referred to as ATM) devices.

In general, an Internet access system for connecting an Internet-enabled terminal to the Internet includes a multi-modem subscriber line access multiplexer (M-DSLAM) for multiplexing data by connecting to a user terminal through a plurality of subscriber lines; Synchronous Digital Hierarchy (SDH) transmission system that converts the data converged by this multimodem concentrator into an STM-1 level optical link, and a network access server (NAS) that connects the optical link to the Internet. Server). The M-DSLAM carries Asynchronous Transfer Mode (ATM) data on the STM-1 optical link and transmits it to the SDH transmission system. The M-DSLAM network interface unit (NIU) Network Interface Unit) consists of a plurality of ATM chips.

Each ATM chip is divided into two operation modes according to the direction of the read-enable signal. When the read-enable signal is an output, it is a master mode device. When the read-enable signal is an input, it is a slave mode device. The interface between one master mode device and one slave device is mainly achieved by the Universal Test Operations PHY Interface for ATM (UTOPIA) interface.

When designing one ATM device, if any two ATM chips need to be connected, the two ATM chips can be connected directly to the utopia interface if one operates in master mode and the other in slave mode. However, when both ATM chips to be connected operate only in slave mode, there is a problem in that two ATM devices cannot be connected to the utopia interface.

It is an object of the present invention to provide a method of utopia interface between two ATM devices operating in slave mode.

In accordance with an aspect of the present invention, there is provided a method for interface between a slave mode device and a utopia interface in an interface circuit for matching between two ATM devices to perform cell data transfer between two ATM devices operating in the same mode. A first (OCA) signal indicating that there is a cell to transmit from the transmitting ATM element is input in an active state and a second (ICA) signal indicating that there is a cell to receive from the receiving ATM element is input in an active state If so, the interface circuit outputs an active third (ORDENB) signal to the transmitting ATM element such that the transmitting ATM element transmits cell data, and the receiving side causes the receiving ATM element to receive cell data. A first step of outputting an active fourth (IWRENB) signal to an ATM element; and receiving ATM from the transmitting ATM element If any one of the first and second signals transitions to a non-active state while cell data is being transmitted to the device, the interface circuitry causes the third signal to transmit all words of the cell data. And a second step of maintaining a fourth signal in an active state, and after all the words of the cell data have been transmitted, the interface circuit transitions the third signal to a non-active state and the fourth signal to a non-active state. And a third step of stopping the transfer of cell data between the two ATM elements.

1 is a diagram illustrating a utopia interface circuit between slave mode devices according to an embodiment of the present invention;

2 and 4 and 5 is an operation timing diagram of the utopia interface circuit according to an embodiment of the present invention,

3 is an operational state diagram of a utopia interface circuit according to an embodiment of the present invention.

※ Explanation of code about main part of drawing ※

11: utopia interface circuit 12: RCMP

13: ATLAS

Hereinafter, with reference to the accompanying drawings will be described a utopia interface method between the slave mode device of the present invention.

1 is a diagram illustrating a utopia interface circuit between slave mode devices according to the present invention. This slave mode element-to-device utopia interface circuit 11 is implemented using a field programmable gate array (FPGA). ATM devices operating only in the slave mode include RCMP and ATLAS, which are manufactured by PMC. In FIG. 1, a circuit for interfacing between the RCMP 12 and the ATLAS 13 is shown as an example. The utopia interface between RCMP 12 and ATLAS 13 is a 16-bit, 27 word interface with data.

The RCMP 12 includes an RCMP_OCA signal output terminal which becomes active when there is a cell to be transmitted in the transmission buffer, an RCMP_ORDENB signal input terminal which is input when the cell can be transmitted, and 16-bit transmission cell data and its A terminal for outputting parity information (ODAT OPRTY), an OSOC signal output terminal for notifying transmission start of a cell, and an OFCLK signal input terminal for receiving a utopia clock signal. On the other hand, the ATLAS 13 has an ATLAS_ICA signal output terminal which becomes active when there is a cell to receive in the reception buffer, an ATLAS_IWRENB signal input terminal which is input in an active state when cell reception is possible, 16-bit received cell data and its parity. And a terminal for inputting information (IDAT IPRTY), an ISOC signal input terminal for receiving a signal indicating start of reception of a cell, and an IFCLK signal input terminal for receiving a utopia clock signal.

The utopia interface circuit 11 includes an output cell available (OCA) terminal connected to the RCMP_OCA signal output terminal of the RCMP, an ORDENB (Output Read Enable Block) terminal connected to the RCMP_ORDENB signal input terminal of the RCMP, and a UTP_CLK terminal to which a utopia clock signal is input. And an ICA (Input Cell Available) terminal connected to the ATLAS_ICA signal output terminal of ATLAS, and an IWRENB (Input Write Enable Block) terminal connected to the ATLAS_IWRENB signal input terminal of ATLAS.

The utopia interface circuit 11 first outputs the RCMP_ORDENB signal for cell transmission to the RCMP 12 when the RCMP_OCA signal and the ATLAS_ICA signal, which are the outputs of the RCMP 12 and the ATLAS 13, become active. The ATLAS_IWRENB signal for cell reception is output to (13). The RCMP then outputs an ATM cell through the ODAT OPRTY terminal while outputting the OSOC signal to ATLAS. Then, when the RCMP_OCA signal of the RCMP 12 or the ATLAS_ICA signal of the ATLAS 13 transitions to a non-active state, the utopia interface circuit 11 first transitions the RCMP_ORDENB signal to the non-active state and then the ATLAS_IWRENB. Transmit the signal to a non-active state to stop the transmission.

The operation of the utopia interface circuit described above will be described with reference to the timing diagram of FIG. 2 and the state diagram of FIG. 3 as follows. The utopia interface circuit receives OCA and ICA signals and outputs ORDENB and IWRENB signals to match between the two slave mode devices.

OCA transitions to active 'high' state in idle (IDLE state) (at least one of OCA and ICA is in a non-active 'low' state and outputs ORDENB and IWRENB signals in a non-active 'high' state) If the ICA transitions to the active 'high' state and the CA value, which is the OR value of the OCA and ICA, becomes active 'high', in step 1, the utopia interface circuit first transitions the ORDENB signal to the active 'low' state and then In step 2, the IWRENB signal is output to the active 'low' state. Then, data cell transmission is performed between RCMP and ATLAS from step 2.

Then, when the OCA (and / or ICA) transitions to the non-active 'low' state and the CA value becomes the non-active 'low' state, the ORDENB signal and the IWRENB signal are activated to transmit four more words thereafter. It keeps in the "low" state (step 3, step 4, step 5). If the CA value stays in a non-active 'low' state until step 5, RCMP has no cell data to transmit, so in step 6, W (27) is transmitted and the ORDENB signal is sent to the RCMP in a non-active 'high' state. Transmit by sending. In the next step, the IWRENB signal is transmitted to ATLAS in a non-active 'high' state, and the process proceeds to standby.

If the CA value transitions to the active 'high' state during the steps 3 to 5, the CA value becomes the active 'high' state during the data cell transmission as shown in the timing diagram of FIG. This active 'high' state is because the RCMP has cell data to transmit and ATLAS can receive data, so the ORDENB and IWRENB signals remain active 'low' immediately after the transmission of the previous data cell. The transmission of the next data cell is started.

4 shows a utopia when the RCMP sends a single cell data and the OCA transitions to a non-active 'low' state and then transitions back to an active 'high' state before the cell data transmission is completed and continuously transmits two cell data. The operation timing diagram of the interface circuit is shown.

First, when the OCA signal is input from the RCMP into the active 'high' state and the ICA signal is input from the ATLAS into the active 'high' state, the ORDENB signal is transitioned to the active 'low' state and output, and then the IWRENB signal is active 'low'. It outputs by transitioning to 'state. When one cell data is transmitted and RCMP transitions the OCA signal into a non-active 'low' state, the utopia interface circuit monitors the OCA signal state and moves the ORDENB signal and the IWRENB signal active 'low' until four more words are transmitted. Keep it

Then, if the OCA signal transitions to the active 'high' state before the remaining four words are transmitted, the utopia interface circuitry recognizes that the RCMP has cell data to transmit to the ATLAS and puts the ORDENB and IWRENB signals into the active 'low' state. Keep going. The RCMP then transfers all remaining words of the previous cell data, followed immediately by the next cell data, which outputs the SOC signal as active 'high' at the start of cell data transfer.

5 is an operation timing diagram of the utopia interface circuit when the RCMP continuously transmits two cell data.

First, when the OCA signal is input from the RCMP into the active 'high' state and the ICA signal is input from the ATLAS into the active 'high' state, the ORDENB signal is transitioned to the active 'low' state and output, and then the IWRENB signal is active 'low'. It outputs by transitioning to 'state. The RCMP outputs the RCMP_OCA signal in an active 'high' state when there is cell data to be transmitted. If there is another cell data to be transmitted even though one cell data is transmitted, the RCMP_OCA signal is kept in an active 'high' state. In addition, ATLAS outputs an ATLAS_ICA signal in an active 'high' state if cell data can be received, and maintains an ATLAS_ICA signal in an active 'high' state if one cell data can be received even after receiving one cell data. The utopia interface circuit then keeps the ORDENB and IWRENB signals active 'low', then the RCMP sends one cell data to ATLAS, then outputs the SOC signal as active 'high' and immediately returns the next cell data. Then send.

As described above, according to the present invention, a Utopia interface is possible between ATM devices operating in the same mode, so that cell data transmission between the two devices can be performed.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (2)

An interface method in an interface circuit for matching between two ATM devices such that cell data transfer is performed between two ATM devices operating in the same mode. A first (OCA) signal indicating that there is a cell to transmit from the transmitting ATM element is input in an active state and a second (ICA) signal indicating that there is a cell to receive from the receiving ATM element is input in an active state If so, the interface circuit outputs an active third (ORDENB) signal to the transmitting ATM element such that the transmitting ATM element transmits cell data, and the receiving side causes the receiving ATM element to receive cell data. Outputting an active fourth (IWRENB) signal to the ATM device; If any one of the first signal and the second signal transitions to a non-active state while cell data is being transferred from the transmitting ATM element to the receiving ATM element, the interface circuit may be configured to perform the cell data transfer. Maintaining the third signal and the fourth signal in an active state so that all words are transmitted; After all words of the cell data have been transmitted, the interface circuit transitions the third signal to a non-active state and the fourth signal to a non-active state to stop cell data transfer between the two ATM elements. Utopia interface method between the slave mode device, characterized in that it comprises a third step. 2. The interface circuit of claim 1, wherein if the non-active signal of the first signal and the second signal transitions back to the active state while all the words of the cell data are transmitted in the second step, the interface circuit is configured to perform the operation of the cell data. And a fourth step of maintaining and outputting the third signal and the fourth signal in an active state even if all the words are transmitted.