KR100416596B1 - 반도체 소자의 연결 배선 형성 방법 - Google Patents
반도체 소자의 연결 배선 형성 방법 Download PDFInfo
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- KR100416596B1 KR100416596B1 KR10-2001-0025573A KR20010025573A KR100416596B1 KR 100416596 B1 KR100416596 B1 KR 100416596B1 KR 20010025573 A KR20010025573 A KR 20010025573A KR 100416596 B1 KR100416596 B1 KR 100416596B1
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- layer
- forming
- etching
- interlayer insulating
- etch
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title description 2
- 239000010410 layer Substances 0.000 claims abstract description 267
- 238000005530 etching Methods 0.000 claims abstract description 106
- 238000000034 method Methods 0.000 claims abstract description 95
- 239000011229 interlayer Substances 0.000 claims abstract description 77
- 239000011241 protective layer Substances 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000010949 copper Substances 0.000 claims description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 16
- 229910052802 copper Inorganic materials 0.000 claims description 16
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 16
- 239000007864 aqueous solution Substances 0.000 claims description 14
- 239000003989 dielectric material Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 238000001039 wet etching Methods 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 239000000243 solution Substances 0.000 claims description 8
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 7
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 229910052710 silicon Inorganic materials 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- 238000002161 passivation Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 230000009977 dual effect Effects 0.000 description 11
- 239000000463 material Substances 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 238000004380 ashing Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 239000012495 reaction gas Substances 0.000 description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 5
- 229910052799 carbon Inorganic materials 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910001873 dinitrogen Inorganic materials 0.000 description 3
- 229910001882 dioxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000013459 approach Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 210000004185 liver Anatomy 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
Description
Claims (18)
- 반도체 기판 상에 형성된 하부 도전층 상에 제1식각 종료층을 형성하는 단계;상기 제1식각 종료층 상에 제1층간 절연층을 형성하는 단계;상기 제1층간 절연층 상에 제2식각 종료층을 형성하는 단계;상기 제2식각 종료층 상에 제2층간 절연층을 형성하는 단계;상기 제1식각 종료층을 식각 종료점으로 하여 상기 제2층간 절연층, 상기 제2식각 종료층 및 상기 제1층간 절연층 순차적으로 식각하여 상기 하부 도전층 상에 정렬되는 비아홀을 형성하는 단계;상기 비아홀 내에 상기 비아홀의 바닥에 결과적으로 드러나는 상기 제1식각 종료층 부분을 덮어 보호하는 보호층을 하이드로실세스퀴옥산(HSQ)층으로 형성하는 단계;상기 제2식각 종료층을 식각 종료점으로 하여 상기 비아홀에 인접하는 상기 제2층간 절연층 부분을 식각하여 상기 비아홀에 연결되는 트렌치를 형성하는 단계;상기 보호층을 제거하는 단계;상기 비아홀의 바닥에 위치하는 상기 제1식각 종료층 부분을 제거하는 단계; 및상기 비아홀 및 상기 트렌치를 채우며 상기 하부 도전층에 전기적으로 연결되는 상부 도전층을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 연결 배선 형성 방법.
- 제1항에 있어서, 상기 하부 도전층은구리층을 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 연결 배선 형성 방법.
- 제1항에 있어서, 상기 제1식각 종료층은실리콘 질화물층 또는 실리콘 탄화물층으로 이루어진 것을 특징으로 하는 반도체 소자의 연결 배선 형성 방법.
- 제1항에 있어서, 상기 제1층간 절연층은저유전물로 이루어지는 것을 특징으로 하는 반도체 소자의 연결 배선 형성 방법.
- 제4항에 있어서, 상기 저유전물은탄소가 도핑된 실리콘 산화물(SiOC)인 것을 특징으로 하는 반도체 소자의 연결 배선 형성 방법.
- 제1항에 있어서, 상기 제2식각 종료층은실리콘 질화물층 또는 실리콘 탄화물층으로 이루어진 것을 특징으로 하는 반도체 소자의 연결 배선 형성 방법.
- 제1항에 있어서, 상기 제2층간 절연층은저유전물로 이루어지는 것을 특징으로 하는 반도체 소자의 연결 배선 형성 방법.
- 제7항에 있어서, 상기 저유전물은탄소가 도핑된 실리콘 산화물(SiOC)인 것을 특징으로 하는 반도체 소자의 연결 배선 형성 방법.
- 삭제
- 삭제
- 제1항에 있어서, 상기 보호층을 형성하는 단계는상기 제2층간 절연층 상에 상기 비아홀을 채우는 상기 보호층을 형성하는 단계; 및상기 보호층을 에치 백하여 상기 보호층의 상측 표면이 상기 제2층간 절연층의 상측 표면보다 낮게 하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 연결 배선 형성 방법.
- 제11항에 있어서, 상기 에치 백은레지스트 현상액(resist developer)을 이용하는 습식 식각으로 수행되는 것을 특징으로 하는 반도체 소자의 연결 배선 형성 방법.
- 제12항에 있어서, 상기 현상액은테트라메틸 암모늄 하이드록사이드(tetramethyl ammonium hydroxide) 수용액을 포함하는 것을 특징으로 하는 반도체 소자의 연결 배선 형성 방법.
- 제11항에 있어서, 상기 에치 백은희석된 HF 용액을 이용하는 습식 식각으로 수행되는 것을 특징으로 하는 반도체 소자의 연결 배선 형성 방법.
- 제1항에 있어서, 상기 보호층을 제거하는 단계는레지스트 현상액(resist developer)을 이용하는 습식 식각으로 수행되는 것을 특징으로 하는 반도체 소자의 연결 배선 형성 방법.
- 제15항에 있어서, 상기 현상액은테트라메틸 암모늄 하이드록사이드(tetramethyl ammonium hydroxide) 수용액을 포함하는 것을 특징으로 하는 반도체 소자의 연결 배선 형성 방법.
- 제1항에 있어서, 상기 보호층을 제거하는 단계는희석된 HF 용액을 이용하는 습식 식각으로 수행되는 것을 특징으로 하는 반도체 소자의 연결 배선 형성 방법.
- 제1항에 있어서, 상기 상부 도전층은구리층을 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 연결 배선 형성 방법.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0025573A KR100416596B1 (ko) | 2001-05-10 | 2001-05-10 | 반도체 소자의 연결 배선 형성 방법 |
US10/081,661 US6828229B2 (en) | 2001-05-10 | 2002-02-22 | Method of manufacturing interconnection line in semiconductor device |
JP2002135872A JP3830419B2 (ja) | 2001-05-10 | 2002-05-10 | 半導体素子の連結配線形成方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR10-2001-0025573A KR100416596B1 (ko) | 2001-05-10 | 2001-05-10 | 반도체 소자의 연결 배선 형성 방법 |
Publications (2)
Publication Number | Publication Date |
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KR20020085722A KR20020085722A (ko) | 2002-11-16 |
KR100416596B1 true KR100416596B1 (ko) | 2004-02-05 |
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Family Applications (1)
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KR10-2001-0025573A KR100416596B1 (ko) | 2001-05-10 | 2001-05-10 | 반도체 소자의 연결 배선 형성 방법 |
Country Status (3)
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US (1) | US6828229B2 (ko) |
JP (1) | JP3830419B2 (ko) |
KR (1) | KR100416596B1 (ko) |
Families Citing this family (33)
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JP2004014841A (ja) * | 2002-06-07 | 2004-01-15 | Fujitsu Ltd | 半導体装置及びその製造方法 |
CN100352036C (zh) * | 2002-10-17 | 2007-11-28 | 株式会社瑞萨科技 | 半导体器件及其制造方法 |
JP4606713B2 (ja) | 2002-10-17 | 2011-01-05 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US6833320B2 (en) * | 2002-11-04 | 2004-12-21 | Intel Corporation | Removing sacrificial material by thermal decomposition |
US6917108B2 (en) * | 2002-11-14 | 2005-07-12 | International Business Machines Corporation | Reliable low-k interconnect structure with hybrid dielectric |
KR100459733B1 (ko) * | 2002-12-30 | 2004-12-03 | 삼성전자주식회사 | 이중 캡핑막을 갖는 반도체 소자의 배선 및 그 형성 방법 |
JP4454242B2 (ja) | 2003-03-25 | 2010-04-21 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
US7309448B2 (en) * | 2003-08-08 | 2007-12-18 | Applied Materials, Inc. | Selective etch process of a sacrificial light absorbing material (SLAM) over a dielectric material |
US6916697B2 (en) * | 2003-10-08 | 2005-07-12 | Lam Research Corporation | Etch back process using nitrous oxide |
EP1673801B1 (en) * | 2003-10-15 | 2014-04-09 | Brewer Science, Inc. | Developer-soluble materials and methods of using the same in via-first dual damascene applications |
US7138707B1 (en) * | 2003-10-21 | 2006-11-21 | Amkor Technology, Inc. | Semiconductor package including leads and conductive posts for providing increased functionality |
KR100529673B1 (ko) * | 2003-12-24 | 2005-11-17 | 동부아남반도체 주식회사 | 듀얼-다마신 패턴을 이용한 반도체 소자의 제조 방법 |
KR100593737B1 (ko) | 2004-01-28 | 2006-06-28 | 삼성전자주식회사 | 반도체 소자의 배선 방법 및 배선 구조체 |
KR100621541B1 (ko) | 2004-02-06 | 2006-09-14 | 삼성전자주식회사 | 듀얼다마신 배선 형성방법 및 듀얼다마신 공정에서 보호막제거용 식각액 |
KR100655774B1 (ko) * | 2004-10-14 | 2006-12-11 | 삼성전자주식회사 | 식각 저지 구조물, 이의 제조 방법, 이를 포함하는 반도체장치 및 그 제조 방법 |
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JP2002353310A (ja) | 2002-12-06 |
JP3830419B2 (ja) | 2006-10-04 |
KR20020085722A (ko) | 2002-11-16 |
US20020168849A1 (en) | 2002-11-14 |
US6828229B2 (en) | 2004-12-07 |
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