KR100413520B1 - Asynchronous transfer mode cell multiple link control apparatus and method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous transmission mode cell multilink control apparatus and a control method thereof, comprising: a transmission path selection table storing a relationship between address information of a transmission processor to transmit cell data and a transmission node of a processor corresponding to the address information; A storage unit, a reception path selection table storage unit for storing a relationship between address information of a receiving processor to receive cell data and a receiving node of a processor corresponding to the address information, and an internal cell storing cell data for communication between the processors. A memory may be implemented to perform internal communication between processors, thereby efficiently utilizing an ATM user network interface communication link of a standard cell transmission standard, thereby maximizing the efficiency of using the communication link.

Description

Asynchronous transfer mode cell multiple link control apparatus and method for controlling same

The present invention relates to an asynchronous transmission mode cell multilink control apparatus and a control method thereof, and more particularly, to a cell multilink control apparatus and its control implemented to perform internal communication between processors using communication path nodes registered in a table. It is about a method.

1 is a diagram illustrating a structure of a conventional ATM switching system. The ATM switch 11 is connected to the subscriber 12 or the ATM cell multiplexer 15 through an inter-module interface (IMI) link, and the plurality of processors 161-16m through the ATM cell multiplexer 15. This is connected.

Conventionally, when the cell multiplexer 15 communicates with each other by directly connecting to the ATM switch 11 link, when a cell is received from the processor link, the cell multiplexer 15 is transferred to the switch link via the cell multiplexer 15 and then the ATM switch. In step 11, the switching path information of the cell header is retrieved, and the cell is transmitted from the ATM switch 11 to the cell multiplexer 15 again. Then, the cell multiplexer 15 may retrieve the path information of the cell header, transmit the cell to the corresponding processor link, and transmit the cell to the target processor to communicate with each other. In this case, since it is a non-standard extended ATM cell (64 bytes) that contains switch path information rather than the standard ATM cell standard (53 bytes), a lot of overhead is inherently generated regardless of the traffic. Had. In addition, when a failure occurs in the ATM switch 11 or when the switch path information is incorrect, normal communication is difficult to perform, and the communication path is complicated, so that loss of communication data often causes reliability and stability of the communication information. It is difficult to provide high quality communication service because it has a disadvantage that cannot be secured.

An object of the present invention is to provide an apparatus and a control method for a cell multi-link implemented to perform internal communication between processors in an ATM switching system.

1 is a diagram illustrating a structure of a conventional ATM switching system.

2 is a diagram showing the structure of an ATM switching system according to the present invention.

FIG. 3 is a block diagram showing an embodiment of the cell multilink control apparatus 25 shown in FIG.

FIG. 4 is a flowchart illustrating an operation of the cell multilink control apparatus shown in FIG. 3.

5A and 5B show the contents of the reception path selection table and the transmission path selection table, respectively.

6 is a block diagram illustrating an embodiment of a cell multilink control apparatus in an ATM switching system according to the present invention.

According to another aspect of the present invention, there is provided a cell data transmission processing apparatus including a plurality of processors, a cell multilink control apparatus for controlling transmission and reception of cell data, including address information of a transmission processor to transmit cell data and the A transmission path selection table storage unit which stores a relationship with a transmission node of a processor corresponding to the address information; A reception path selection table storage unit for storing a relationship between address information of a reception processor to receive cell data and a reception node of a processor corresponding to the address information; An internal cell memory configured to store cell data for communication between the processors; When cell data is transmitted from an arbitrary processor, a transmission path address is detected from the header information of the cell data, the transmission path node corresponding to the destination is determined from the transmission path address with reference to the transmission path selection table storage unit, and the transmission is performed. A transmitting cell controller for storing the cell data in the internal cell memory when a path node is another processor; And reading a cell data stored in the internal cell memory, detecting a reception path address from the header information of the read cell data, and referring to a reception path selection table storage unit, a reception path node corresponding to a destination processor from the reception path address. And a receiving cell control unit for determining and transmitting the cell data to a processor corresponding to the receiving path node.

In the cell data transmission processing method according to the present invention for achieving the above object, in the cell multi-link control apparatus that is matched with a plurality of processors to control the transmission and reception of cell data, in the method for processing the transmission of cell data, Detecting a transmission path address from the header information of the cell data when cell data is transmitted by the processor of the processor, and determining a transmission path node corresponding to a destination from the transmission path address with reference to a transmission path selection table; If the transmission path node is another processor, storing the cell data in an internal cell memory; Reading cell data stored in the internal cell memory; Detecting a reception path address from the header information of the read cell data, and determining a reception path node corresponding to a destination processor from the reception path address with reference to a reception path selection table; And transmitting the cell data to a processor corresponding to the processor reception path node.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram showing the structure of an ATM switching system according to the present invention. Asynchronous transfer mode interface module (AIM) devices 221-22m are connected to subscribers 231-23m via a User Network Interface (UN), for example, 1 A port of a high speed optical line of the physical layer of the AIM device 221 is connected to the cell multilink controller 25. The cell multilink controller 25 physically matches a plurality of low speed processor 261-16n ports in an ATM standard cell transmission standard format, and multiplexes and demultiplexes cells for the matched plurality of communication links. To perform.

The cell multilink controller 25 is a processor 261-26n subordinate to the cell multilink controller 25 to reduce the load on the UNI link of the AIM device 221 and increase the transmission efficiency of the communication link. Provides communication between

FIG. 3 is a block diagram showing an embodiment of the cell multilink control apparatus 25 shown in FIG.

Receives cell data from a user network interface (UNI) link of the AIM device 30 and stores the cell data for communication between the receiving cell memory 31 and the subordinate processors 381-38n and 39 therein. The internal cell memory 32 is provided.

When cell data is transmitted from an arbitrary processor, the transmitting cell control unit 35 detects a transmission path address from header information of the cell data, and corresponds to a destination processor from the transmission path address with reference to the transmission path selection table storage unit 36. The transmission path node to be determined. If the transmission path node is an AIM device, cell data is transmitted to the AIM device 30 by processing the ATM layer signal, and when the transmission path node is another processor, the cell data is stored in the internal cell memory 32.

The receiving cell controller 33 selectively reads the cell data stored in the receiving cell memory 31 or the internal cell memory 32, detects the receiving path address from the header information of the read cell data, and stores the receiving path selection table. With reference to section 34, a reception path node corresponding to a destination processor is determined from a reception path address, and the cell data is transmitted to a processor corresponding to the reception path node.

The transmission path selection table storage unit 36 stores a relationship between address information of a transmission processor to transmit cell data and a transmission node of a processor corresponding to the address information, and the reception path selection table storage unit 34 stores cell data. Stores the relationship between the address information of the receiving processor to receive the receiving node of the processor corresponding to the address information. 5A and 5B show the contents of the reception path selection table and the transmission path selection table, respectively. In FIG. 5A, for example, if the VPI (Virtual Path ID) detected in the received cell data is 001, the receiving node of the processor becomes 2, which means that the dependent processor 2 382 becomes.

FIG. 4 is a flowchart illustrating an operation of the cell multilink control apparatus shown in FIG. 3. When cell data is received from the UNI link of the AIM device (421), it is stored in the receiving cell memory (423). On the other hand, when cell data is transmitted (411) by an arbitrary subordinate processor, the transmission path address is detected from the header information of the cell data (413), and the transmission path node corresponding to the destination is determined from the transmission path address with reference to the transmission path selection table. Determine (415).

If the transmission path node is an AIM device (43), the cell data transmitted from the subordinate processor processes the ATM layer signal (471) and transmits the data to the AIM device through the UNI link (473). If the transmission path node is another slave processor (communication between slave processors), the cell data is stored separately in the internal cell memory (451).

Referring to a process of transmitting cell data to a subordinate processor, first, cell data stored in a receiving cell memory or an internal cell memory is selectively read (452), and then a reception path address is detected from the header information of the read cell data (453). In step 454, a reception path node corresponding to the destination processor is determined from the reception path address with reference to the reception path selection table, and cell data is transmitted to the processor corresponding to the processor reception path node (455).

A communication process between the AIM device and the processor will be described with reference to FIG. 4. When cell data is received from the UNII link of the AIM device (421), the cell data is stored in the receiving cell memory 423, and the receiving cell controller reads the cell data in the receiving cell memory (452) to the target processor. Transmit (453-455). On the other hand, when cell data is transmitted from an arbitrary processor to an AIM device, the transmission path node is identified from the cell data transmitted from the arbitrary processor (411-415), and if the transmission path node is an AIM processor (43), the cell. The data is processed by the ATM layer and then transmitted to the AIM device (471, 473).

Next, the communication process between the processors will be described. If a transmission path node is another processor (43), the transmission path node is identified from the cell data transmitted from an arbitrary processor (43). In operation 451. The receiving cell controller reads the cell data in the internal cell memory (452) and transmits the cell data to another target processor (453-455).

6 is a block diagram illustrating an embodiment of a cell multilink control apparatus in an ATM switching system according to the present invention. Cell multilink controller 65 for physically matching a plurality of processors using a single port of a User Network Interface (UN) link of an ATM standard cell standard, and performing a function of multiplexing and demultiplexing a plurality of matched communication links. Is shown.

The cell multilink controller 65 has an internal cell switch FIFO 74 to perform cell switching functions between the processors 661-676, 890, and to perform cell transmission from the processors 661-676, 890. And a transmission path selection table storage unit 80, and a reception path selection table storage unit 77 for cell reception to the processors 661-676, 890, and registered in each table. Use the information separately.

The cell multilink controller 65 includes a transmission path selection table storage unit 80, an internal cell switch FIFO (Internal Cell Switch First In First Out) 74, a reception path selection table storage unit 77, and the like. In the case of communication between the processors 661-676 and 890, which are dependent on the cell multilink controller 65, can directly communicate with each other without passing through the UNI link between the ATM switch and the AIM device. Provide a way.

Internal cell switch FIFO of the cell multilink controller 65 when any of the processors 661-676, 890 that are dependent on the cell multilink controller 65 communicate with the AIM device 62 or the ATM switch. Instead of using 74, the path of the ATM layer signal processing unit 72 of the cell multilink control apparatus 65 is used in accordance with the cell transmission path selection information registered in the table of the transmission path selection table storage unit 80. Perform communication. Receive path selection table of cell multilink controller 65 when AIM device 62 or ATM switch communicates with any of the processors 661-676, 890 that are dependent on cell multilink controller 65. The present invention provides a method of performing communication with the desired processors 661-676 and 890 using cell reception path selection information registered in a table of the storage unit 77. As such, it is possible to perform cell transmission or cell reception between the processors 661-676, 890 and with the AIM device 62 or ATM switch.

Therefore, due to the above-described method, the amount of control data for the communication link of limited speed can be properly distributed, thereby increasing the utilization value of the system communication link and improving the communication service quality. The communication path table information of the transmission path selection table storage unit 80 and the reception path selection table storage unit 77 in the link control device 65 can be changed as necessary, so that a plurality of cells in the cell multilink control device 65 can be changed. It has the advantage of flexible control of communication path.

Referring back to FIG. 6, FIG. 6 is matched to allow for the communication of 17 or 666 low speed processors 6610-676 individually or simultaneously using one UNI link of the high speed AIM device 62. That is, 17 processors including a local processor 890 and 16 subordinate processors 661-676 are matched with one UNI link.

The cell multilink controller 65 is matched with a UNI link 63 capable of transmitting and receiving cells in ATM standard cell specification format, and a photoelectric conversion for matching with the UNI link 63 of the AIM device 62 with an optical cable. An element 71, an ATM layer signal processing unit 72 for processing an ATM layer of an ATM standard cell standard and matching the ATM physical layer, and a reception cell FIFO for temporarily storing cell data received from the ATM layer signal processing unit 72; (73) is provided.

The photoelectric conversion element 71 transmits and receives an optical signal through the UNI link 63 and transmits and receives a serial electric signal through the ATM layer signal processing unit 72. The ATM layer signal processing unit 72 performs ATM layer processing on the serial electric signal received from the photoelectric conversion element 71, converts the processed ATM layer signal into parallel cell data units, and stores the same in the receiving cell FIFO 73. Further, the parallel ATM cell data received through the transmission FIFO selector 75 is processed by the ATM layer, and then converted into a serial electric signal for transmission to the photoelectric conversion element 71.

The internal cell switch FIFO 74 is a cell multilink controller (not connected via the UNI switch of an ATM switch or an AIM device in case of intercommunication of the processors 661-676, 890 that are dependent on the cell multilink controller 65). 65) In order to switch the cells inside and transmit them to the destination processor, the cells 661-676 and 890 temporarily store the cells to be transmitted to each other.

The cell multilink controller 65 includes a receive FIFO selector 76 and a receive FIFO selector 76 for selecting one of the receive cell FIFO 73 and the internal cell switch FIFO 74 to process the receive cell. And a receiving cell processing control unit 78 for processing the incoming cell and storing the cell in the processor receiving cell FIFOs 811 to 827.

The receiving cell control processing unit 78 periodically monitors the cell data storage state with respect to the receiving cell FIFO 73 and the internal switch FIFO 74 and stored in the FIFO memory 73 or 74 selected by the receiving FIFO selector 76. Read the cell data, and if the read cell data is a valid cell, extract the receiving processor address information by searching the virtual path ID (VPI) area of the ATM cell header, and extract the received receiving processor address information from the receiving path. The data is transmitted to the selection table storage unit 77. The reception path selection table storage unit 77 transfers the cell transmission path information corresponding to the reception processor address to the reception cell control processing unit 78 by referring to the information registered in the internal table. In addition, the reception cell control processing unit 78 notifies the processor link controllers 851-866 that the cells have been stored while storing the data of each cell in the processor reception cell FIFOs 811-827.

The reception path selection table storage unit 77 receives the destination processor using the VPI information of the ATM cell received through the AIM device 62 or the internal cell switch FIFO 74 of the ATM switch or the cell multilink controller 65. The link selection information is transmitted to the receiving cell control processing unit 78.

The processor receiving cell FIFOs 811-827 temporarily store the cells introduced from the receiving cell control processing unit 78, and the processor link controllers 851-866 store the cells stored in the corresponding processor receiving cell FIFOs 811-826. The cell data is read and transmitted to the corresponding physical layer matching elements 871-886. The physical layer matching element (871-886) transmits and receives a cell flowing from the corresponding processor link controller (851-866) to the processor (661-676), the processor transmit cell FIFO (831-846) When the cell is sent from the processors 661-676, the cell is temporarily stored via the corresponding physical layer matching element 871-886 and the corresponding processor link controller 851-866.

Each processor link controller 851-866 receives a valid signal for the cell from the processor receive cell control processor 78 to each processor receive cell FIFO 811-827, and each processor receive cell FIFO 811-827. Read and count the cells in units of cells, and if there is no error, transmit the cell data to the corresponding physical layer matching element (871-886), and transmit the cell transmitted through the corresponding physical layer matching element (871-886). After storing in the cell FIFOs 831-846, the transmitting cell control processing unit 79 notifies that the cell has been stored.

Each physical layer matching element 871-886 converts a cell received from each processor link controller 851-866 into a serial data format, and then transmits the cell to the physical layer link of the corresponding processor 661-676. Serial cell data sent from the processors 661-676 and entered into each physical layer link is converted into parallel cell data, and then transmitted to the corresponding processor link controllers 851-866.

The transmit cell control processing unit 79 reads the cell stored in the processor transmit cell FIFOs 831-846 and transmits it to the internal cell switch FIFO 74, which is a processor path dependent on the cell multilink controller 65, or an AIM path. It is determined whether to transmit to the ATM layer signal processor 72.

The transmitting cell control processing unit 79 receives the validity of the cell data stored in each of the processor transmission cell FIFOs 831-846 from each of the processor link controllers 851-866. ), Periodically read the cell stored in the processor transmit cell FIFO (831-846), retrieve the virtual path ID (VPI) region of the read ATM cell data header, extract the sender processor address information, and extract The transmission processor address information is transmitted to the transmission path selection table storage unit 80.

When the transmission path selection table storage unit 80 transfers the cell transmission path information corresponding to the transmission processor address to the processor transmission cell control processing unit 79 by referring to the information registered in the internal table, the transmission cell control processing unit 79 Is a cell delivered to the processors 661-676, 890 dependent on the cell multilink controller 62, or a cell delivered to the AIM device 62. The transmit cell control processor 79 stores the cell by selecting the internal switch FIFO 74 by the transmit FIFO selector 75 when the cell is delivered to the subordinate processors 661-676 and 890. If the cell is to be transmitted, the transmit FIFO selector 75 selects the ATM layer signal processor 72 to control the cell to be transmitted.

The transmission path selection table storage unit 80 transmits the transmission link selection information of the cell transmission destination processor to the processor transmission cell control processing unit 79 by using the VPI information of the cell received from the processor transmission cell FIFOs 831-847. . The transmission FIFO selector 75 selectively transmits the cell to the internal cell switch FIFO 74 or the ATM layer signal processor 72 according to the transmission link selection information of the cell transmission destination processor.

On the other hand, the cell multilink controller 65 includes a local processor 890, the local processor 890 is a monitoring and failure state for each component configured in the cell multilink controller 65, failure A recovery function may be performed, and a maintenance function may be performed, such as initializing information on a transmission / reception path between the reception path selection table storage unit 77 and the transmission path selection table storage unit 80. In addition, a processor transmit cell FIFO 847 for temporarily storing a transmission cell of the local processor 890 and a processor receiving cell FIFO 827 for temporarily storing a cell received by the local processor 890.

The asynchronous transmission mode cell multilink controller 65 configured as described above operates as follows. Using one UNI-link of the high-speed AIM device 62, 17 low-speed processors can communicate individually or simultaneously. That is, the cell is processed from the UNI link 63 of the AIM device 62 and received by the local processor 890 to perform the corresponding operation or transmit the cell to the 16 subordinate processors 661-676. do. In addition, a cell received from each of the processors 661-676 and 890 is multiplexed and transmitted to the AIM device 62, or transmitted to an internal cell switch FIFO 74 of the cell multilink controller 65. Subordinate to the link control device 65 to transmit to the processors (661-676, 890) to perform communication.

Hereinafter, an operation performed according to the transmission mode of cell data by the apparatus shown in FIG. 6 will be described in more detail.

First, a case in which the AIM device 62 communicates to any processor (eg, processor 1 661) will be described. When the optical signal of the ATM standard cell standard is input through the photoelectric conversion element 71 of the cell multilink control device 65 from the UNI link 63 of the AIM device 62, the photoelectric conversion element 71 transmits the optical signal in series. The signal is converted into signal data and sent to the ATM layer signal processing unit 72. The ATM layer signal processor 72 retrieves serial data, converts the retrieved data into 8-bit parallel data, stores the received data in the receiving cell FIFO 73 in units of standard ATM cells, and informs the receiving cell control processor 78 of the data. The receiving cell control processing unit 78 reads data from the receiving cell FIFO 73 in units of ATM cells. At this time, the receiving cell control processing unit 78 has an arbiter therein so as to periodically select the receiving cell FIFO 73 and the internal cell switch FIFO 74 alternately so that the arbiter uses the receiving FIFO selector 76 to receive the receiving cell FIFO. Either 73 or internal cell switch FIFO 74 is selected.

When the VPI information of the ATM header area is retrieved from the cell unit data read from the receiving cell FIFO 73, the extracted information is converted into a processor receiving path address and transmitted to the receiving path selection table storage unit 77 to select the receiving path. The table storage unit 77 reads the information on the reception path node corresponding to the destination from the reception path address registered in advance, and sends it to the processor reception cell control processing unit 208. In this example, reference is made to the reception cell selection table information of FIG. 5A, and corresponds to a case where the reception path address (VPI) of the destination processor 661 is 000. The processor reception node is 1, which is the first link, processor 1 661. Will send the cell.

Then, the receiving cell control processing unit 78 checks the information of the receiving path node, stores the corresponding ATM cell in the corresponding processor receiving cell FIFO 811, and then signals that one cell has been stored in the processor link controller 851. Informed by. The processor link controller 851 which receives the signal counts data in the cell unit from the processor receiving cell FIFO 811 and reads the data in the cell unit, and transmits the cell to the physical layer matching element 871 if there is no error. The physical layer matching element 871 converts the parallel cell data into serial data and transmits the same to the processor 661 to communicate.

In contrast to the above process, a case in which a processor (eg, processor 2 662) communicates with the AIM device 62 will be described below.

When an ATM cell is sent from an arbitrary processor 662 and enters through a physical layer matching element 871 of the cell multi-link control device 65, the physical layer matching element 871 converts serial data into parallel data and processes the processor. Send to link controller 851. The processor link controller 851 counts data, stores the data in the processor transmission cell FIFO 831 in units of cells, and informs the transmission cell control processing unit 79 of the stored signal. Data is read from the transmitting cell FIFO 831 in units of cells. At this time, the transmitting cell control processing unit 79 includes an arbiter therein to periodically arbitrate 17 processor transmitting cell FIFOs 831 to 847 to alternately select one of the 17 processor transmitting cell FIFOs 831.

The transmission cell control processing unit 79, which reads cell data from the processor transmission cell FIFO 831, retrieves the VPI information of the ATM header area, converts the extracted information into a processor transmission path address, and transmits a transmission path selection table storage unit ( 80). The transmission path selection table storage unit 80 reads the transmission path node information corresponding to the destination from the transmission path address registered to the mobile station, and sends it to the transmission cell control processing unit 80 after reading.

In this example, as a result of referring to the transmission cell selection table information 80 of FIG. 5B, the reception path address (VPI) for the AIM device 62 which is the destination processor is 150. The processor reception node is 2, and the transmission FIFO is received. The selector 75 selects the ATM layer signal processing unit 72.

The transmitting cell control processing unit 79 checks the information of the transmission path node, and if the destination processor address and the node correspond to the AIM device 62, selects the ATM layer signal processing unit 72 through the transmitting FIFO selector 75 and ATM. After processing the ATM layer, the layer signal processor 72 converts the parallel cell data into a serial electric signal and transmits the same to the photoelectric conversion element 71. The photoelectric conversion element 201 converts an electrical signal into an optical signal and transmits the electrical signal to the AIM device 62 through the optical line.

For communication between the processors 661-676 and 890, for example, when the processor 2 662 transmits a cell to the processor 1 661, the cell transmitted from the processor 2 662 may be a cell multilink controller. The cell is transmitted to the transmitting cell control processor 79 via the corresponding link of 65). The transmission cell control processing unit 79 checks the information of the transmission path node using the processor transmission cell selection table 80 of FIG. 5B and confirms that the destination processor address and the node correspond to the processor 1 661 device.

The transmit cell control processor 79 selects the internal cell switch FIFO 74 through the transmit FIFO selector 75 and stores data transmitted from the processor 2 662 in the internal cell switch FIFO 74 in units of cells. The stored signal is informed to the reception cell control processing unit 78. The receiving cell control processing unit 78 then reads the data from the internal cell switch FIFO 74 in units of ATM cells.

The VPI information of the ATM header area is retrieved from the data of the cell unit read from the internal cell switch FIFO 74, and the extracted information is converted into a processor reception path address and transmitted to the reception path selection table storage unit 77. The reception path selection table storage unit 77 reads the reception path node information corresponding to the destination from the reception path address registered to the destination path, and sends the received path control table to the reception cell control processor 78. The receiving cell control processor 78 checks the information of the receiving path node, stores the ATM cell in the receiving cell FIFO 811 of the processor 1 661 corresponding to the destination processor, and then processes the signal indicating that one cell is stored. Notified to link controller 851. The processor link controller 851 which receives the signal counts the data of the cell unit from the processor receiving cell FIFO 811 and reads the data of the cell unit, and transmits the cell to the physical layer matching element 871 if there is no error. The physical layer matching element 871 converts the parallel cell data into serial data and transmits the same to the processor 1 661.

On the other hand, when the local processor 890 communicates with any processor (e.g., processor 2 (662)), the same manner as described above. For example, when the local processor 890 transmits control communication information and stores it in the processor cell transmission FIFO 847 which is its path, the transmission cell control processing unit 79 performs the above-described transmission cell processing, and then internal cell transmission FIFO. If the cell is stored at 74, the reception cell control processor 78 may perform the reception cell processing process and transmit control communication information to the target processor 2 662.

According to the present invention, even when communicating between processors dependent on the cell multilink controller 62, the AIM device 62 or the ATM switch is not used without using the internal cell switch FIFO 74. Interprocessor communication may be performed. This can be freely adjusted using the transmission FIFO selector 75 in the transmission cell control processing unit 79. As described above, the present invention has various functions, ATM standards, and the like, and has many features, such as being applicable to various communication systems.

The invention can also be embodied as computer readable code on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like, and may also be implemented in the form of a carrier wave (for example, transmission over the Internet). Include. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

The best embodiments have been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the asynchronous transfer mode cell multilink control apparatus according to the present invention is an Asynchronous Transfer Mode Interface Module (AIM) apparatus for communication between processors in an Asynchronous Transfer Mode (ATM) switching system having a distributed structure. A port of optical fiber, which is a physical layer link, and a plurality of processors physically match each other, and provide a function of multiplexing and demultiplexing cells using a cell transmission scheme of ATM standard cell standard through the matched link. In particular, in order to reduce the UNI link load of the high speed AIM device, it is possible to maximize the transmission efficiency of the communication link by providing the communication function between the processors that are dependent on the cell multilink control device and to flexibly process the system resource management. have.

Therefore, according to the present invention, the utilization of the ATM user network interface (UN) communication link of a high-speed, high-cost standard cell transmission standard in an asynchronous transfer mode (ATM) switching system is efficiently utilized to maximize the utilization efficiency of the communication link. It is possible to provide high quality communication service for the system by pursuing performance improvement and high added value of the exchange system, securing stability and reliability of the control transmission information in interprocessor communication in the exchange system, and providing a standard ATM cell. A communication link of a transmission standard may be provided to enable communication with a variety of standardized devices. In addition, it is possible to provide a communication link having expandability in which a processor can be added or subtracted according to the system shape structure.

On the other hand, according to the present invention, the communication path is not complicated by directly connecting the ATM switch link, which is a high-speed, high-cost communication link, by using a UNI link of an ATM standard format. It can increase the stability, performance and added value of the system by minimizing the number of devices. It can be connected to any communication link with ATM standard cell transmission standard. In addition, the internal cell switch FIFO is provided in the asynchronous transmission mode cell multilink controller for communication between a plurality of low-speed processors that are dependent on the asynchronous transmission mode cell multilink controller. Even if the communication between the processors dependent on the asynchronous transmission mode cell multilink control device can be performed normally. This has the advantage of being able to properly distribute the amount of control information for the communication link of a limited speed, thereby increasing the utilization value of the system communication link, and improve the communication service quality.

In addition, by separately providing and operating a transmission cell selection table storage unit and a reception cell selection table storage unit, cell transmission / reception table management is easy, and a table can be changed separately as necessary. This ensures the stability and reliability of control information in communication with a processor or other block processor (AIM device or ATM switch) subordinate to the cell multilink controller, thereby providing a high quality communication service for the switching system.

The conventional ATM switch transmits an ATM cell in a non-standard format of 64 bytes in which routing information on the path is added, so that there is a lot of overhead for cell-by-cell message transmission and a complicated communication path. According to the present invention, the performance of the system can be improved by using a link of an ATM standard cell transmission unit (unit of 53 bytes), and a communication path can be configured more easily than the conventional ATM switch link matching method.

Claims (9)

In the cell multi-link controller to match the plurality of processors to control the transmission and reception of cell data, A transmission path selection table storage unit for storing a relationship between address information of a transmission processor to transmit cell data and a transmission node of a processor corresponding to the address information; A reception path selection table storage unit for storing a relationship between address information of a reception processor to receive cell data and a reception node of a processor corresponding to the address information; An internal cell memory configured to store cell data for communication between the processors; When cell data is transmitted from an arbitrary processor, a transmission path address is detected from the header information of the cell data, the transmission path node corresponding to the destination is determined from the transmission path address with reference to the transmission path selection table storage unit, and the transmission is performed. A transmitting cell controller for storing the cell data in the internal cell memory when a path node is another processor; And After reading the cell data stored in the internal cell memory, a reception path address is detected from the header information of the read cell data, and a reception path node corresponding to a destination processor is determined from the reception path address by referring to a reception path selection table storage unit. And a receiving cell control unit which transmits the cell data to a processor corresponding to the receiving path node. The method of claim 1, And receiving cell memory for receiving cell data from a user network interface link of the AIM device and storing the cell data; The receiving cell controller selectively reads cell data stored in the receiving cell memory or the internal cell memory, and transmits the cell data to a processor corresponding to the receiving path node obtained from the cell data. Processing unit. The method of claim 1, wherein the transmitting cell control unit And transmitting the cell data to an AIM device if the transmission path node is an AIM device. The method of claim 1, When the transmission path node obtained from the cell data transmitted from any processor is another processor, the transmitting cell control unit transmits the cell data to the AIM device, and the receiving cell control unit receives the cell data from the AIM device. Cell data transfer processing apparatus characterized in that for transmitting to the desired processor. In the cell multi-link controller to match the plurality of processors to control the transmission and reception of the cell data, the method for processing the transmission of the cell data, Detecting a transmission path address from header information of the cell data when cell data is transmitted by an arbitrary processor, and determining a transmission path node corresponding to a destination from the transmission path address with reference to a transmission path selection table; If the transmission path node is another processor, storing the cell data in an internal cell memory; Reading cell data stored in the internal cell memory; Detecting a reception path address from the header information of the read cell data, and determining a reception path node corresponding to a destination processor from the reception path address with reference to a reception path selection table; And And transmitting the cell data to a processor corresponding to the processor reception path node. The method of claim 5, Receiving cell data from a UNI link of an AIM device and storing it in a receiving cell memory, wherein reading the cell data selectively reads cell data stored in the receiving cell memory or the internal cell memory. Characterized in that the cell data transmission processing method. 6. The method of claim 5, wherein in the determining step, if the transmission path node is an AIM device, the cell data is processed by an ATM layer signal and transmitted to the AIM device. 6. The method of claim 5, wherein the cell data is transmitted and received by the above process even when the arbitrary processor or the other processor is a local processor. A computer-readable recording medium having recorded thereon a program for executing the method of any one of claims 5 to 8.