KR100407977B1 - Apparatus for format conversion - Google Patents

Abstract

An apparatus for converting an oversampled image. In particular, the oversampled image format converter is a digital filter for limiting a band of the oversampled image in synchronization with an oversampled clock, and a resolution of an image output from the digital filter. It is configured to include a format converter for converting the output according to the input / output resolution information from the outside, and a buffer for temporarily storing the output of the format converter, eliminating the complicated analog filter to be used externally, and also the PLL function Using the included A / D converter does not require complex PLL functions, so stable A / D conversion can be performed.

Description

Apparatus for format conversion

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a format converting apparatus for a digital TV, and more particularly, to a format converting apparatus for converting horizontal resolutions of input images of various sizes.

With the introduction of digital TVs and the development of various display devices, more various types of images can be input and output than conventional analog TVs. In addition, with the introduction of digital TV, most images such as NTSC video or PC video are processed digitally.

In order to digitally process such an image, an analog / digital (A / D) converter 102 is basically required as shown in FIG. 1, and to obtain an accurate digital image, an A / D converter (Phase Locked Loop) is used. You need to make the required pixel clock. The data digitized by the A / D converter 102 is converted into an output image of a desired size by the format converter 103 and then output.

At this time, in the case of PC images, high resolution (1600x1200, 1280x1024) images have become common, and a pixel clock of 100 MHz is required for normal A / D conversion. On the other hand, in the case of conventional NTSC or PAL signals, pixel clocks of 13.5MHz and 14.32MHz bands are required for A / D conversion.

As the input image varies, the PLL should provide a pixel clock of 13 MHz to 100 MHz for each image and apply it to the A / D converter 102. A PLL providing a pixel clock of 100 MHz provides a 13 MHz pixel clock. Things are technically difficult.

To solve this problem, in the case of an image having a low pixel clock such as NTSC, PAL or VGA (640 * 480 resolution) image, the PLL is oversampled using the pixel clock which has oversampled it at an appropriate ratio. Can increase the stability.

In addition, by considering this in the format conversion unit of the next stage, the entire system can be stabilized.

That is, FIG. 2 is a block diagram illustrating an apparatus for receiving an oversampled image and converting the format. When the oversampled image is input, the filter 201 performs filtering in synchronization with the oversampled clock to prevent aliasing. The output is sent to the first format converter 202. The first format converter 202 converts the oversampled image into a normal image and stores it in the memory 203. The memory 203 is provided to output normal image data to the second format converter 204 at a later stage.

That is, by using the memory 203, the clock and the synchronization signal between the input image and the second format converter 204 can be separated, and the desired operation can be performed.

However, the above-described case of FIG. 2 also causes unnecessary waste of memory or memory bandwidth, resulting in an increase in overall system price.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a format conversion apparatus for converting an oversampled image into a normal input image after restricting the band of the oversampled image.

1 is a block diagram showing an embodiment of a conventional format conversion apparatus

2 is a block diagram showing another embodiment of a conventional format conversion apparatus;

3 is a block diagram illustrating a format conversion apparatus according to the present invention;

FIG. 4 is a detailed block diagram illustrating an embodiment of the oversampled image format converter of FIG. 3. FIG.

FIG. 5 is a detailed block diagram illustrating another embodiment of the oversampled image format converter of FIG. 3. FIG.

Explanation of symbols for main parts of the drawings

301: A / D converter 302: Oversampled video format converter

303: main format converter 401: filter

402: format converter 403: buffer

404: clock divider 405: write control unit

406: read control unit

In accordance with another aspect of the present invention, there is provided a format conversion apparatus including an A / D converter for oversampling and digitizing an input image with an oversampled pixel clock, and an oversampled image output from the A / D converter. An oversampled image format converter for band-limiting and reducing the horizontal resolution of the band-limited video to a normal video such as an input video format, and a main format converter for converting the resolution of the normal video to a resolution of the output video. Characterized in that it comprises a.

The oversampled image format converter is configured to limit the band of the oversampled image in synchronization with the oversampled clock, and to input / output resolution information externally inputting the resolution of the image output from the digital filter. And a buffer for temporarily storing the output of the format converter.

The write control unit controlling the writing of the buffer may store only valid image data among the image data generated by the format converter by using the oversampled clock.

The read control unit for controlling the reading of the buffer reads an image stored in the buffer by using a normal clock, and controls to prevent a buffer pool or empty state from occurring.

Other objects, features and advantages of the present invention will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, with reference to the accompanying drawings illustrating the configuration and operation of the embodiment of the present invention, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, By the technical spirit of the present invention described above and its core configuration and operation is not limited.

3 is a block diagram illustrating a format conversion apparatus according to the present invention, in which an A / D converter 301 and an oversample output from the A / D converter 302 for oversampling and digitizing an input image with an oversampled clock. An oversampled image format converter 302 for reducing the horizontal resolution of the normalized image to a normal image such as an input image format, and a main format converter 303 for converting the resolution of the normal image.

In this case, in FIG. 3, when the oversampled input image is not used, the oversampled image format converter 302 is removed, and the A / D converter 301 and the main screen format converter 303 are directly connected. In order to operate normally, the resolution of the input / output image is different, but the rest of the input and output formats are identical to each other.

4 is a detailed block diagram of the format converter 302 for oversampling of FIG. 3, wherein the filter 401 restricts a band of an oversampled image, and oversamples the resolution of an image output from the filter 401. A format converter 402 for converting using a clock and input / output resolution information input from the outside, a buffer 403 for temporarily storing the output of the format converter 402, and a clock divider for dividing the oversampled clock 404, a write control unit 405 for storing the normalized image converted into a format according to the oversampled clock, in the buffer 403, and the buffer 403 according to the normal clock divided by the clock divider 404. The read control unit 406 outputs a normal image in the same form as the format of the input image by reading the image stored in the "

In the present invention configured as described above, the A / D converter 301 generates an oversampled pixel clock using a PLL, oversamples the input image with the oversampled pixel clock, and outputs the oversampled image format converter 302. do. That is, the oversampled image and the oversampled pixel clock are input to the filter 401 of the oversampled image format converter 302. The oversampled clock is also input to the format converter 402, the clock divider 404, and the write controller 405.

The filter 401 of the oversampled image format converter 302 band-limits horizontal frequency components of the oversampled input image according to the output.

In general, when the input is oversampled, the image itself is band-limited, and thus a separate filter 401 may not be required, but the noise component included in the input is removed. If such an operation is unnecessary, the filter 401 can be placed in the bypass mode to immediately output the input image.

In the analog filter used in FIG. 1, it is not easy to configure a filter for each input image suitable for the frequency characteristics as the input image changes. However, unlike the analog filter, the filter 401 of the present invention has an advantage of obtaining desired frequency characteristics by loading coefficients as needed.

The format converter 402 changes the resolution of the oversampled image by using input / output resolution information and an oversampled clock.

The format converter 402 maintains or reduces the resolution of the output image to be equal to the resolution of the input image. If the format converter 402 lowers the resolution of the input image, a problem may arise in that timings of the input image and the output image do not match. That is, in the case of the input image, even if a valid image is continuously input, an invalid image is output during the format conversion process, and a separate process is required for this portion. For this purpose, a storage device is required behind the format converter 402.

It is common to use a separate external memory or a line memory for the storage device, but in the present invention, a buffer 403 having a minimum size is solved as shown in FIG. 4.

On the other hand, the clock divider 404 divides the input oversampled clock by an integer ratio and provides it to the read controller 406 and the main format converter 303 as a normal clock. In general, divide by the integer value similar to the ratio of the horizontal resolution of the input image to the horizontal resolution of the input image, such as 1/1, 1/2, 1/3, ..., 1/7, 1/8, etc. It is possible to use a divider. In addition, if the clock divider 404 can be configured to be more complicated, such as 2/3, 4/5, 3/11, the processing speed of the input image and the output image can be maintained similar to each other, and the size of the required buffer can be reduced. have.

The write control unit 405 controls the buffer 403 to store only valid images among the image data output from the format converter 402 by using the information generated by the format converter 402. In this case, the write controller 405 stores the image data in the buffer 403 using the oversampled clock.

The read control unit 406 reads the image data in the buffer 403 using a clock divided by the clock divider 404, that is, a normal clock, but the state of the buffer 403 is full. Controls continuous output without empty status. To this end, the size of the buffer 403 and the time point at which the buffer 403 is first read must be precisely controlled.

As described above, the write control unit 405 stores the data converted in the buffer 403 using the oversampled clock, and the read control unit 406 reads the data stored in the buffer 403 using the normal clock. By doing so, the main format converter 303 outputs a normal image of the same type as the input image.

On the other hand, in the case of an NTSC image having a low image processing clock, the A / D converter 301 may oversample and apply a high clock, and may reduce the processing speed by using the oversampled image format converter 302. If the image processing clock is high, such as an SVGA image, there is no need to oversample the image unnecessarily. In this case, the division ratio of the clock division unit 404 may be set to 1/1.

In this case, it is not necessary to store the buffer unnecessarily and output the same. As shown in FIG.

5 is another embodiment of the present invention, further comprising a mux 507 in FIG.

That is, the oversampled image from the A / D converter 301 is output to the mux 507 via the format converter 502 and the buffer 503, and the image not oversampled is directly output from the mux (the format converter 502). 507).

As described above, according to the format conversion apparatus according to the present invention, in the system for processing various types of inputs, it is possible to eliminate complex analog filters used externally and to use the A / D converter including the PLL function. It does not require complex PLL functions, enabling stable A / D conversion. In addition, the digital processing function is additionally required to achieve this advantage, but the overall system can be stabilized without increasing the cost.

In addition, since it uses a minimum amount of memory required for the digital processing unit, there is an advantage that it can be configured at a low cost. Also, since the input and output formats are the same, it is easy to add / delete the existing design. have.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (3)

An A / D converter for oversampling and digitizing an input image with an oversampled pixel clock; An oversampled image format converter for converting the oversampled image output from the A / D converter through filtering to reduce the horizontal resolution of the band-limited image into a normal image such as an input image format; And And a main format converter for converting the resolution of the normal video into the resolution of the output video. The method of claim 1, wherein the oversampled image format converter A digital filter for limiting a band of the oversampled image in synchronization with the oversampled clock; A format converter for converting the resolution of the image output from the digital filter according to input / output resolution information input from the outside; A buffer for temporarily storing the output of the format converter, A clock divider for dividing the oversampled clock at a predetermined ratio to convert the clock to a normal clock; A write control unit for storing only valid image data of the image data generated by the format converter by using the oversampled clock in the buffer; And a read control unit configured to read an image stored in the buffer using a normal clock divided by the clock divider, and output a normal image having the same form as that of an input image to the main format converter. Device. The method of claim 2, The MUX is further provided as an input to the output of the format converter and the output of the buffer, respectively, The mux selects the output of the buffer when the oversampled image is processed and output from the A / D converter, and outputs the format converter when the oversampled image is processed and output from the A / D converter. And a format conversion device.