KR100407563B1 - Universal serial bus device - Google Patents

Abstract

The universal serial bus device disclosed herein includes two control lines (terminals or pins) for providing test mode signals, test data lines (terminal or pins) capable of input / output data signals, and a plurality of It includes switch circuits of. The switch circuits of the universal serial bus device of the present invention allow the serial bus and the USB core to be directly connected in the test mode of operation without the involvement of the bus receiver and the bus transmitter of the data transceiver. The switch circuits can measure the characteristics of the bus receiver through the test data terminals without intervention of the USB core in a test mode of operation. In addition, the switch circuits allow the characteristics of the bus transmitter to be measured in the test mode of operation without intervention of the USB core. Therefore, according to the universal serial bus device of the present invention, the data transceiver and the USB core can be tested individually or independently.

Description

Universal Serial Bus Device {UNIVERSAL SERIAL BUS DEVICE}

The present invention relates to a universal serial bus system, and more particularly, to a universal serial bus interface device connected between a serial bus and a function device.

Recently, a new standard called Universal Serial Bus (hereinafter abbreviated as "USB") suitable for personal computers has been released. According to the new standard, connecting devices of various peripheral devices such as keyboards, mice, and game pads are made in the same form. The peripheral devices are used by connecting the connecting devices to the USB ports of the personal computer. Peripherals that conform to the USB standard have also been distributed on the market.

1 is a block diagram showing a USB interface device. The USB interface device 100 is connected between the serial bus 200 and the function device 400. The USB interface device 100 includes a data transceiver 120 and a USB core 140. The USB core 140 will be provided with a voltage regulator, a serial interface engine and a device controller, although not shown in the figure. The voltage regulator supplies a second power supply voltage of 0V-3.3V, for example, using a first power supply voltage of 0V-5V. The data transceiver 120, as shown in FIG. 2, has a bus receiver 122 and a bus transmitter 124. The bus receiver 122 of the data transceiver 120 converts data signals modulated in a bus-specific format to data signals in an interface-oriented format using the first and second power supply voltages. The bus transmitter 124 of the data transceiver 120 converts in reverse. The interface engine implements an interface between the interface oriented signals and data signals in a device oriented format. The device controller controls the function device 400 in response to data signals in the device oriented format.

Testing USB devices is largely divided into data transceiver characteristic tests and USB function tests. 1 and 2, the data transceiver 120 and the USB core 140 are closely connected. For this reason, it is difficult to determine whether the problem that occurs during the test is a characteristic problem related to the data transceiver 120 or a function error. In conclusion, testing USB devices is considerably cumbersome because the USB core 140 should be considered when testing the characteristics of the data transceiver 120 and the data transceiver 120 should be considered when testing the characteristics of the USB core.

An object of the present invention is to provide a universal serial bus device that can improve test reliability.

1 is a block diagram showing a universal serial bus interface device according to the prior art;

FIG. 2 is a block diagram showing a schematic configuration of the data transceiver shown in FIG. 1;

3 is a block diagram showing a universal serial bus interface device according to a preferred embodiment of the present invention; And

4 is a preferred embodiment of the universal serial bus interface device shown in FIG.

Explanation of symbols on the main parts of the drawings

100: USB interface device 122: bus receiver

124: bus transmitter 140: USB core

200: serial bus 300, 320, 340, 360: switch circuit

380: control logic 400: function device

(Configuration)

According to a feature of the present invention for achieving the above object, a serial interface circuit connected between a serial bus and a function device comprises: first and second test data lines; A bus receiver and a bus transmitter connected to first and second data lines DP and DM of the serial bus, respectively; First and second control terminals to which first and second test mode signals (TestMode1 and TestMode2) indicating the test operation mode of the universal serial bus device are applied; A universal serial bus that accepts data signals from the first and second data lines through the bus receiver or outputs data signals to the first and second data lines through the bus transistor; A core; Control logic to selectively activate the bus receiver or the bus transmitter in response to the first and second test mode signals and a select signal (OEN) from the universal serial bus core; In response to the first test mode signal, data signals applied to the first and second data lines are directly transmitted to the universal serial bus core or data signals output from the bus receiver are transferred to the universal serial bus core. A first switch circuit SW1; A second signal transmitting data signals output from the universal serial bus core to the bus transmitter in response to the second test mode signal or data signals applied to the first and second test data lines to the bus transmitter; A switch circuit SW2; A third switch circuit (SW3) for transferring data signals output from the bus receiver to the first and second test data lines when the first test mode signal is activated; And a fourth switch for directly transferring data signals output from the universal serial bus core to the first and second data lines in response to the first test mode signal and the selection signal OEN from the universal serial bus core. And a circuit SW4.

(Action)

With such a device, not only is it easy to perform the test by electrically separating the USB core and the data transceiver in the test operation mode, but also the test reliability can be improved.

(Example)

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the drawings.

The novel universal serial bus device of the present invention comprises two control lines (terminals or pins) for providing test mode signals, test data lines (terminals or pins) capable of inputting / outputting data signals, and It includes a plurality of switch circuits. The switch circuits of the universal serial bus device of the present invention allow the serial bus and the USB core to be directly connected in the test mode of operation without the involvement of the bus receiver and the bus transmitter of the data transceiver. The switch circuits can measure the characteristics of the bus receiver through the test data terminals without intervention of the USB core in a test mode of operation. In addition, the switch circuits allow the characteristics of the bus transmitter to be measured in the test mode of operation without intervention of the USB core. Therefore, according to the universal serial bus device of the present invention, the data transceiver and the USB core can be tested individually or independently. This will be explained in detail later.

3 is a block diagram showing a universal serial bus device according to the present invention. In FIG. 3, components having the same functions as those shown in FIG. 2 are denoted by the same reference numerals.

In the universal serial bus (USB) interface device 100 according to the present invention, referring to FIG. 3, two control terminals 403 and 404 and two data lines (terminals or pins) 405 and 406. This is provided. First and second test mode signals TestMode1 and TestMode2 indicating the test operation mode of the USB device are respectively applied to the control terminals 403 and 404. The data lines 405 and 406 enable data signals to be transmitted from the USB interface device 100 to an external device (eg, test equipment or other device) or from the external device to the USB interface device 100. The data lines 405 and 406 are shareable with other terminals or pins. In the test mode of operation, the first and second test mode signals TestMode1 and TestMode2 are exclusively activated. For example, when the first test mode signal TestMode1 is activated, the second test mode signal TestMode2 is inactivated. When the first test mode signal TestMode1 is deactivated, the second test mode signal TestMode2 is activated.

Referring to FIG. 3, the USB interface device 100 of the present invention includes a bus receiver 122, a bus transmitter 124, a USB core 140, and first to fourth switch circuits 300, 320, 340, and 360. And control logic 380. The USB core 140 will be provided with a voltage regulator, a serial interface engine and a device controller, although not shown in the figure. The voltage regulator supplies a second power supply voltage of 0V-3.3V, for example, using a first power supply voltage of 0V-5V. The bus receiver 122 converts data signals modulated in a bus oriented format using the first and second power supply voltages into data signals in an interface oriented format, and the bus transmitter 124 converts vice versa. The interface engine implements an interface between the interface oriented signals and data signals in a device oriented format. The device controller controls the function device 400 in response to data signals in the device oriented format.

3, the first switch circuit 300 is connected to the data lines DP and DM, the bus receiver 122 and the USB core 140. The first switch circuit 300 directly transmits data signals on the data lines DP and DM to the USB core 140 in response to the activation of the first test mode signal TestMode1 in the test operation mode. The first switch circuit 300 transmits data signals output from the bus receiver 122 to the USB core 140 in the normal operation mode or when the first test mode signal TestMode1 is inactivated.

The second switch circuit 320 is connected to the bus transmitter 124, the USB core 140, and the test data lines DP_T and DM_T. The second switch circuit 320 transmits the data signals VP_OUT and VM_OUT output from the USB core 140 to the bus transmitter 124 in response to the activation of the second test mode signal TestMode2 in the test operation mode. Block it. In addition, when data signals are applied to the test data terminals 405 and 406 from the outside in the test operation mode, the second switch circuit 320 receives the input external in response to the activation of the second test mode signal TestMode2. Deliver data signals to bus transmitter 124. The second switch circuit 320 transmits the data signals VP_OUT and VM_OUT output from the USB core 140 to the bus transceiver 124 in the normal operation mode.

The third switch circuit 340 is connected to the bus receiver 122 and the test data terminals 405 and 406. The third switch circuit 340 transfers the data signals output from the bus receiver 122 to the test data terminals 405 and 406 in response to the activation of the first test mode signal TestMode1 in the test operation mode. The fourth switch circuit 360 is connected to the USB core 140 and the data lines DP and DM. The fourth switch circuit 360 receives the data signals VP_OUT and VM_OUT output from the USB core 140 in response to the activation of the first test mode signal TestMode1 and the selection signal OEN in the test operation mode. Directly to the media (DP, DM). The select signal OEN is output from the USB core 140. In the normal operation mode in which the first and second test mode signals TestMode1 and TestMode2 are both inactivated, the third and fourth switch circuits 340 and 360 are inactivated.

The control logic 380 selectively activates the bus receiver 122 or the bus transmitter 124 in response to the first and second test mode signals TestMode1 and TestMode2 and the selection signal OEN. When the first test mode signal TestMode1 is activated in the test operation mode, the control logic 380 activates the receiver selection signal SEL regardless of the logic state of the selection signal OEN. At this time, the transmitter selection signal SEL # is deactivated. When the second test mode signal TestMode1 is activated in the test operation mode, the control logic 380 deactivates the receiver selection signal SEL regardless of the logic state of the selection signal OEN. At this time, the transmitter selection signal SEL # is activated. In the normal operation mode in which the first and second test mode signals TestMode1 and TestMode2 are deactivated, the control logic 380 activates the transmitter selection signal SEL # and selects the receiver in response to the activation of the selection signal OEN. Deactivate signal SEL. In the normal operation mode, the control logic 380 deactivates the transmitter selection signal SEL # and activates the receiver selection signal SEL in response to the deactivation of the selection signal OEN.

4 is a circuit diagram showing a preferred embodiment of the switch circuits and the control logic of the universal serial bus device shown in FIG.

Referring to FIG. 4, the first switch circuit 300 includes two multiplexers MUX1 and MUX2, and each multiplexer includes two input terminals D0 and D1, a selection terminal S, and an output terminal ( Y) The output data signal VP_IN_0 of the bus receiver 122 is applied to the D0 input terminal of the multiplexer MUX1, and the data signal on the data line DP is applied to the D1 input terminal. The first test mode signal TestMode1 is applied to the selection terminal S of the multiplexer MUX1. The D0 input terminal is selected when the first test mode signal TestMode1 is low level, and the D1 input terminal is selected when the first test mode signal TestMode1 is high level. The data signal applied through the input terminal thus selected is output through the output terminal Y. The other output data signal VM_IN_0 of the bus receiver 122 is applied to the D0 input terminal of the multiplexer MUX2, and the data signal on the data line DM is applied to the D1 input terminal. The first test mode signal TestMode1 is applied to the selection terminal S of the multiplexer MUX2. The D0 input terminal is selected when the first test mode signal TestMode1 is low level, and the D1 input terminal is selected when the first test mode signal TestMode1 is high level. The data signal applied through the input terminal thus selected is output through the output terminal Y.

When the first test mode signal TestMode1 is at the low level, the first switch circuit 300 transmits the data signals VP_IN_0 and VM_IN_0 output from the bus receiver 122 to the USB core 300. When the first test mode signal TestMode2 is at a high level, the first switch circuit 300 directly transfers data signals on the data lines DP and DM to the USB core 300 without passing through the bus receiver 122. To pass. That is, in the test operation mode, the first switch circuit 300 electrically disconnects the bus receiver 122 from the USB core 140.

4, the second switch circuit 320 is composed of two multiplexers MUX3 and MUX4, each of which has two input terminals D0 and D1, a selection terminal S and an output. It has a terminal Y. The output data signal VP_OUT of the USB core 140 is applied to the D0 input terminal of the multiplexer MUX3, and the data signal on the test data line DP_T is applied to the D1 input terminal. The second test mode signal TestMode2 is applied to the selection terminal S of the multiplexer MUX3. The D0 input terminal is selected when the second test mode signal TestMode2 is low level, and the D1 input terminal is selected when the second test mode signal TestMode2 is high level. The data signal applied through the input terminal thus selected is output through the output terminal (Y). The other output data signal VM_OUT of the USB core 140 is applied to the D0 input terminal of the multiplexer MUX4, and the data signal on the test data line DM_T is applied to the D1 input terminal. The second test mode signal TestMode2 is applied to the selection terminal S of the multiplexer MUX4. The D0 input terminal is selected when the second test mode signal TestMode2 is low level, and the D1 input terminal is selected when the second test mode signal TestMode2 is high level. The data signal applied through the input terminal thus selected is output through the output terminal Y.

When the second test mode signal TestMode2 is at the low level, the second switch circuit 320 transmits the data signals VP_OUT and VM_OUT output from the USB core 140 to the bus transmitter 124. When the second test mode signal TestMode2 is at the high level, the second switch circuit 320 electrically disconnects the USB core 140 and the bus transmitter 124.

The third switch circuit 340 according to the present invention is composed of two buffers B1 and B2 that use the first test mode signal TestMode1 as an enable signal. The data signal VP_IN_0 output from the bus receiver 122 is applied to the input terminal of the buffer B1, and the output terminal of the buffer B1 is connected to the test data terminal 405. The data signal VM_IN_0 output from the bus receiver 122 is applied to the input terminal of the buffer B2, and the output terminal of the buffer B2 is connected to the test data terminal 406. When the first test mode signal TestMode1 is activated, the third switch circuit 340 transfers the data signals VP_IN_0 and VM_IN_0 output from the bus receiver 122 to the test data terminals 405 and 406. . When the first test mode signal TestMode1 is inactivated, the third switch circuit 340 is inactivated.

As shown in FIG. 4, the fourth switch circuit 360 operates in response to the selection signal OEN and the first test mode signal TestMode1, and includes an AND gate G1 and two buffers B3,. B4). The selection signal OEN and the first test mode signal TestMode1 are applied to both input terminals of the AND gate G1, respectively. The data signal VP_OUT output from the USB core 140 is applied to the input terminal of the buffer B3, and the output terminal of the buffer B3 is connected to the data line DP. The data signal VM_OUT output from the USB core 140 is applied to the input terminal of the buffer B4, and the output terminal of the buffer B4 is connected to the data line DM. The buffers B3 and B4 store data signals VP_OUT and VM_OUT output from the USB core 140 when the output of the AND gate G1 is activated (OEN = 'H', TestMode1 = 'H'). Transfer to lines DP and DM. If either of the OEN and TestMode1 signals is low level, the buffers B3 and B4 are inactivated.

The control logic 380 for selectively activating the bus receiver 122 or the bus transmitter 124 consists of two inverters INV1, INV2, an end gate G2, and an or gate G3. The inverter INV1 inverts the first test mode signal TestMode1, and the selection signal OEN and the output signal of the inverter INV1 are applied to both input terminals of the AND gate G2, respectively. The output signal of the AND gate G2 and the second test mode signal TestMode2 are applied to both input terminals of the OR gate G3, respectively. The output signal of the OR gate G3 is supplied not only to the bus transmitter 124 as the transmitter selection signal SEL # but also to the bus receiver 122 as the receiver selection signal SEL through the inverter INV2. When the first test mode signal TestMode1 is activated and the second test mode signal TestMode2 is deactivated, the logic states of the output signals SEL and SEL # of the control logic 380 are controlled by the selection signal OEN. Is determined. When the first test mode signal TestMode1 is deactivated and the second test mode signal TestMode2 is activated, the bus transmitter 124 is activated and the bus receiver 122 is deactivated regardless of the selection signal OEN. .

The USB device of the present invention described with reference to FIGS. 3 and 4 supports two test operation modes. In one test mode of operation, the USB device supports testing of the characteristics of the bus receiver 122 of the USB core 140 and the data transceiver 120. In another test mode of operation, the USB device supports testing of the characteristics of the bus transmitter 124 of the data transceiver 120. In the normal mode of operation, the USB device of the present invention operates in the same way as that of the prior art. The operation of the USB device for the normal operating mode and the test operating modes will be described in detail below based on the trueness drawings.

In the normal operation mode, the first and second test mode signals TestMode1 and TestMode2 are inactivated. Since the D0 input terminal of each of the multiplexers MUX1 and MUX2 is selected according to the deactivation of the first test mode signal TestMode1, the data signals on the data lines DP and DM are transferred to the bus receiver 122 and the first switch. It will be delivered to the USB core 140 via the circuit 300. Alternatively, since the D0 input terminal of each of the multiplexers MUX3 and MUX4 is selected according to the deactivation of the second test mode signal TestMode2, the data signals VP_OUT and VM_OUT output from the USB core 140 are second. The switch circuit 320 and the bus transmitter 124 will be transferred to the data lines DP and DM. At this time, the control logic 380 selectively activates the bus receiver 122 or the bus transmitter 124 according to the selection signal OEN. In the normal mode of operation, the third and fourth switch circuits 340 and 360 are deactivated. That is, in the normal operation mode, the normal data interface function is performed.

In the test operation mode in which the first test mode signal TestMode1 is activated and the second test mode signal TestMode2 is inactivated, the characteristic test of the bus receiver 122 of the USB core 140 and the data transceiver 120 is performed. Can be supported. More specifically, it is as follows.

When the first test mode signal TestMode1 is activated, the control logic 380 activates the bus receiver 122 and deactivates the bus transmitter 124. As the first test mode signal TestMode1 is activated, the bus receiver 122 and the USB core 140 are electrically disconnected, while the data lines DP and DM disconnect the first switch circuit 300. Directly and electrically connected to the USB core 140 through. At the same time, the data signals VP_IN_0 and VM_IN_0 output from the bus receiver 122 are transmitted to the test data terminals 405 and 406 through the third switch circuit 340.

Since the second test mode signal TestMode2 is maintained in an inactive state, the second switch circuit 320 transmits the data signals VP_OUT and VM_OUT output from the USB core 140 to the bus transmitter 124. However, since the bus transmitter 124 is inactive, data signals output from the second switch circuit 320 are not transmitted to the data lines DP and DM. If the selection signal OEN is in an inactive state, the fourth switch circuit 360 is inactive. If the selection signal OEN is in an activated state, the fourth switch circuit 360 is activated. In the latter case, the USB core 140 will be directly electrically connected to the data lines DP and DM through the fourth switch circuit 360.

Under these conditions, the characteristics of the bus receiver 122 can be measured through the test data terminals 405 and 406 without having to consider the operation of the USB core 140. In addition, the characteristics of the USB core 140 can be measured through the data terminals 401 and 402 without having to consider the operation of the bus receiver 122 and the bus transmitter 124.

In a test operation mode in which the first test mode signal TestMode1 is deactivated and the second test mode signal TestMode2 is activated, the characteristic test of the bus transmitter 124 may be supported. More specifically, it is as follows.

When the second test mode signal TestMode1 is activated, the control logic 380 deactivates the bus receiver 122 and activates the bus transmitter 124. As the second test mode signal TestMode2 is activated, the second switch circuit 320 is connected to the test data terminals 405 and 406 instead of the data signals VP_OUT and VM_OUT output from the USB core 140. Applies external test data signals to the bus transmitter 124. Since the bus transmitter 124 is activated, the data signals output from the second switch circuit 320 are transferred to the data lines DP and DM.

As the first test mode signal TestMode1 is deactivated, the third and fourth switch circuits 340 and 360 are deactivated. At this time, even if the bus receiver 122 and the USB core 140 are electrically connected through the first switch circuit 300, since the bus receiver 122 is inactive, the USB core 140 is not affected. .

Under these conditions, the characteristics of the bus transmitter 124 can be measured through the data terminals 401, 402 without having to consider the operation of the USB core 140.

In the above, the configuration and operation of the circuit according to the present invention has been shown in accordance with the above description and drawings, but this is only an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, the test is not only easy to perform the test by electrically separating the USB core and the data transceiver in the test operation mode, but also the test reliability can be improved.

Claims (43)

First and second data lines DP and DM, a bus receiver and a bus transmitter connected to the first and second data lines DP and DM, respectively, and the first and second through the bus receiver. A universal serial bus apparatus having a universal serial bus core for receiving data signals from data lines or outputting data signals through the bus transmitter to the first and second data lines: A first control terminal to which a first test mode signal (TestMode1) indicating a test operation mode of the universal serial bus device is applied; In response to the first test mode signal and the selection signal OEN from the universal serial bus core, data signals applied to the first and second data lines are directly transmitted to the universal serial bus core or the universal serial bus. First switch circuits (SW1, SW4) for directly transferring data signals output from a core to the first and second data lines; First and second test data lines; A second control terminal to which a second test mode signal (TestMode2) indicating a test mode of the universal serial bus device is applied; Control logic to selectively activate the bus receiver or the bus transmitter in response to the first and second test mode signals and a select signal (OEN) from the universal serial bus core; And And a second switch circuit (SW3) for transferring data signals output from the bus receiver to the first and second test data lines under control of the control logic when the first test mode signal is activated. A universal serial bus device. delete The method of claim 1, And wherein said first and second test mode signals are exclusively activated during said test mode of operation. The method of claim 3, wherein And when the first test mode signal is activated, the control logic causes the bus receiver to be activated and the phase bus transmitter to be deactivated. The method of claim 3, wherein And when the second test mode signal is activated, the control logic causes the bus receiver to be deactivated and the bus transmitter to be activated. The method of claim 5, And when both the first and second test mode signals are deactivated, the control logic selectively activates the bus receiver or the bus transmitter in accordance with the selection signal (OEN). The method of claim 6, The control logic is A first inverter for inverting the first test mode signal; An AND gate receiving the first test mode signal and an output of the inverter; An OR gate receiving the second test mode signal and an output of the AND gate; And A second inverter for inverting the output of the or gate, wherein the bus receiver is activated / deactivated in accordance with the output of the second inverter, and the bus transmitter is activated / deactivated in accordance with the output of the or gate. Universal serial bus device. The method of claim 6, The first switch circuits SW1 and SW4 A first input terminal D0 for receiving one of the data signals output from the bus receiver, a second input terminal D1 for receiving one of the first and second data lines, and the first test A first multiplexer having a selection terminal S for accepting a mode signal as a selection signal, and an output terminal Y for outputting a data signal input through an input terminal selected by the first test mode signal; A first input terminal D0 for receiving the other of the data signals output from the bus receiver; a second input terminal D1 for receiving the other of the first and second data lines; A second multiplexer having a selection terminal S for accepting one test mode signal as a selection signal, and an output terminal Y for outputting a data signal input through an input terminal selected by the first test mode signal; ; An AND gate outputting an enable signal by combining a selection signal output from the universal serial bus core and the first test mode signal; And First and second buffers respectively receiving data signals output from the universal serial bus core and outputting the input data signals to the first and second data lines in response to an enable signal from the AND gate. Universal serial bus device, characterized in that. The method of claim 8, And the first and second multiplexers directly transfer data signals provided from the first and second data lines to the universal serial bus core when the first test mode signal is activated. . The method of claim 9, When the selection signal output from the universal serial bus core is activated and the first test mode signal is activated, data signals output from the universal serial bus core are first and second buffers through the first and second buffers. A universal serial bus device, characterized in that it is carried directly on two data lines. The method of claim 6, The second switch circuit SW3 includes first and second buffers for transmitting data signals output from the bus receiver to the first and second test data lines in response to the first test mode signal. A universal serial bus device. The method of claim 6, And a third switch circuit (SW2) for transmitting data signals applied to the first and second test data lines to the bus transmitter in response to the second test mode signal. . The method of claim 12, The third switch circuit SW2 is A first input terminal D0 for receiving one of the data signals output from the universal serial bus core, a second input terminal D1 for receiving one of the first and second test data lines, and A first multiplexer having a selection terminal S for accepting a second test mode signal as a selection signal and an output terminal Y for outputting a data signal input via an input terminal selected by the second test mode signal; Wow; And A first input terminal D0 for receiving the other of the data signals output from the universal serial bus core; a second input terminal D1 for receiving the other of the first and second test data lines; And a selection terminal S for accepting the second test mode signal as a selection signal, and an output terminal Y for outputting a data signal input through an input terminal selected by the second test mode signal. A multiplexer, wherein the output terminals of the first and second multiplexers are connected to input terminals of the bus transmitter. In the serial interface circuit connected between the serial bus and the function device: First and second test data lines; A bus receiver and a bus transmitter connected to first and second data lines DP and DM of the serial bus, respectively; First and second control terminals to which first and second test mode signals (TestMode1 and TestMode2) indicating the test operation mode of the universal serial bus device are applied; A universal serial bus that accepts data signals from the first and second data lines through the bus receiver or outputs data signals to the first and second data lines through the bus transistor; A core; Control logic to selectively activate the bus receiver or the bus transmitter in response to the first and second test mode signals and a select signal (OEN) from the universal serial bus core; In response to the first test mode signal, data signals applied to the first and second data lines are directly transmitted to the universal serial bus core or data signals output from the bus receiver are transferred to the universal serial bus core. A first switch circuit SW1; A second signal transmitting data signals output from the universal serial bus core to the bus transmitter in response to the second test mode signal or data signals applied to the first and second test data lines to the bus transmitter; A switch circuit SW2; A third switch circuit (SW3) for transferring data signals output from the bus receiver to the first and second test data lines when the first test mode signal is activated; And A fourth switch circuit which directly transfers data signals output from the universal serial bus core to the first and second data lines in response to the first test mode signal and a selection signal OEN from the universal serial bus core. Serial interface device comprising (SW4). The method of claim 14, And the first and second test mode signals are exclusively activated during the test mode of operation. The method of claim 15, And when the first test mode signal is activated, the control logic causes the bus receiver to be activated and the phase bus transmitter to be deactivated. The method of claim 16, And when the second test mode signal is activated, the control logic causes the bus receiver to be deactivated and the bus transmitter to be activated. The method of claim 17, And when both the first and second test mode signals are deactivated, the control logic selectively activates the bus receiver or the bus transmitter in accordance with the selection signal (OEN). The method of claim 18, The control logic is A first inverter for inverting the first test mode signal; An AND gate receiving the first test mode signal and an output of the inverter; An OR gate receiving the second test mode signal and an output of the AND gate; And A second inverter for inverting the output of the or gate, wherein the bus receiver is activated / deactivated in accordance with the output of the second inverter, and the bus transmitter is activated / deactivated in accordance with the output of the or gate. Serial interface device. The method of claim 18, The first switch circuit SW1 is A first input terminal D0 for receiving one of the data signals output from the bus receiver, a second input terminal D1 for receiving one of the first and second data lines, and the first test A first multiplexer having a selection terminal S for accepting a mode signal as a selection signal, and an output terminal Y for outputting a data signal input through an input terminal selected by the first test mode signal; And A first input terminal D0 for receiving the other of the data signals output from the bus receiver; a second input terminal D1 for receiving the other of the first and second data lines; A second multiplexer having a selection terminal S for accepting one test mode signal as a selection signal and an output terminal Y for outputting a data signal input through an input terminal selected by the first test mode signal; Serial interface device comprising a. The method of claim 20, And the first and second multiplexers directly transfer data signals provided from the first and second data lines to the universal serial bus core when the first test mode signal is activated. The method of claim 18, The second switch circuit SW2 is A first input terminal D0 for receiving one of the data signals output from the universal serial bus core, a second input terminal D1 for receiving one of the first and second test data lines, and A first multiplexer having a selection terminal S for accepting a second test mode signal as a selection signal and an output terminal Y for outputting a data signal input via an input terminal selected by the second test mode signal; Wow; And A first input terminal D0 for receiving the other of the data signals output from the universal serial bus core; a second input terminal D1 for receiving the other of the first and second test data lines; And a selection terminal S for accepting the second test mode signal as a selection signal, and an output terminal Y for outputting a data signal input through an input terminal selected by the second test mode signal. And a multiplexer, wherein output terminals of the first and second multiplexers are connected to input terminals of the bus transmitter. The method of claim 18, The third switch circuit SW3 includes first and second buffers for transmitting data signals output from the bus receiver to the first and second test data lines in response to the first test mode signal. Characterized by a serial interface device. The method of claim 18, The fourth switch circuit SW4 is An AND gate outputting an enable signal by combining a selection signal output from the universal serial bus core and the first test mode signal; And First and second buffers respectively receiving data signals output from the universal serial bus core and outputting the input data signals to the first and second data lines in response to an enable signal from the AND gate. Serial interface device, characterized in that. The method of claim 24, When the selection signal output from the universal serial bus core is activated and the first test mode signal is activated, data signals output from the universal serial bus core are first and second buffers through the first and second buffers. A universal serial bus device, characterized in that it is carried directly on two data lines. delete delete delete delete delete delete delete delete First and second data lines DP and DM, a bus receiver and a bus transmitter connected to the first and second data lines DP and DM, respectively, and the first and second through the bus receiver. A universal serial bus apparatus having a universal serial bus core for receiving data signals from data lines or outputting data signals through the bus transmitter to the first and second data lines: First and second test data lines; A control terminal to which a test mode signal (TestMode2) indicating a test operation mode of the universal serial bus device is applied; Control logic to selectively activate the bus receiver or the bus transmitter in response to the first and second test mode signals and a select signal (OEN) from the universal serial bus core; In response to the first test mode signal, data signals applied to the first and second data lines are directly transmitted to the universal serial bus core or data signals output from the bus receiver are transferred to the universal serial bus core. A first switch circuit SW1; A second switch circuit (SW3) for transferring data signals output from the bus receiver to the first and second test data lines when the first test mode signal is activated; And A third switch circuit which directly transfers data signals output from the universal serial bus core to the first and second data lines in response to the first test mode signal and a selection signal OEN from the universal serial bus core. A universal serial bus device, comprising: (SW4). The method of claim 34, wherein And wherein said first and second test mode signals are exclusively activated during said test mode of operation. 36. The method of claim 35 wherein And when the first test mode signal is activated, the control logic causes the bus receiver to be activated and the phase bus transmitter to be deactivated. The method of claim 36, And when the second test mode signal is activated, the control logic causes the bus receiver to be deactivated and the bus transmitter to be activated. The method of claim 37, And when both the first and second test mode signals are deactivated, the control logic selectively activates the bus receiver or the bus transmitter in accordance with the selection signal (OEN). The method of claim 38, The first switch circuit SW1 is A first input terminal D0 for receiving one of the data signals output from the bus receiver, a second input terminal D1 for receiving one of the first and second data lines, and the first test A first multiplexer having a selection terminal S for accepting a mode signal as a selection signal, and an output terminal Y for outputting a data signal input through an input terminal selected by the first test mode signal; and A first input terminal D0 for receiving the other of the data signals output from the bus receiver; a second input terminal D1 for receiving the other of the first and second data lines; A second multiplexer having a selection terminal S for accepting one test mode signal as a selection signal and an output terminal Y for outputting a data signal input through an input terminal selected by the first test mode signal; Serial interface device comprising a. The method of claim 39, And the first and second multiplexers directly transfer data signals provided from the first and second data lines to the universal serial bus core when the first test mode signal is activated. The method of claim 38, The second switch circuit SW3 includes first and second buffers for transmitting data signals output from the bus receiver to the first and second test data lines in response to the first test mode signal. Characterized by a serial interface device. The method of claim 38, The third switch circuit SW4 is An AND gate outputting an enable signal by combining a selection signal output from the universal serial bus core and the first test mode signal; And First and second buffers respectively receiving data signals output from the universal serial bus core and outputting the input data signals to the first and second data lines in response to an enable signal from the AND gate. Serial interface device, characterized in that. The method of claim 42, When the selection signal output from the universal serial bus core is activated and the first test mode signal is activated, data signals output from the universal serial bus core are first and second buffers through the first and second buffers. A universal serial bus device, characterized in that it is carried directly on two data lines.