KR100404943B1 - Method of manufacturing semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a lower portion of a capacitor is disposed below a metal contact formed in a peripheral circuit region to prevent a sudden change in contact resistance between a plug and an upper electrode according to a plug recess. The electrode, the dielectric film, and the upper electrode are formed, and a plug is formed thereon, so that the plug and the upper electrode overlap each other in the metal contact hole, so that the contact resistance can be kept constant regardless of the degree of recess of the plug. A method of manufacturing the device is provided.

Description

Method of manufacturing semiconductor device

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a first metal contact (M1C) formed on the upper electrode of a metal-insulator-metal (MIM) capacitor.

The structure of MIM (Metal-Insylator-Metal) in DRAM is widely used because of its advantages that it is easier to secure effective oxide thickness (Tox) than MIS (Metal-Insulator-Semiconductor) and there is no change of Cs according to applied voltage. Ta ₂ O ₅ is used as the dielectric material of the MIM structure, and W, TiN, Pt, Ru, Ir, etc. are used as the metal electrode. Among them, TiN is widely used in the deposition process.

The current capacitor is a fuse layer that enables laser cutting to replace failed bits or lines with redundancy lines during the semiconductor device manufacturing process. Since the upper electrode of is used, the contact resistance values of the first metal contact M1C and the upper electrode are also important in the overall device operation speed.

A method of forming a first metal contact M1C according to the prior art will be briefly described with reference to FIGS. 1A through 1C as follows.

Referring to FIG. 1A, a semiconductor substrate (not shown) in which cell regions and peripheral circuit regions are defined is provided, and an underlayer 11 is formed on the semiconductor substrate through a predetermined deposition process. The base layer 11 may include an isolation layer (not shown) for defining an active region in the semiconductor substrate, a gate electrode formed on the active region, a source and a drain formed in the active region. And a first landing plug 1 (not shown) formed between a region (not shown) and the gate electrode.

Subsequently, after the first interlayer dielectric layer ILD1 12 is formed over the entire structure, an etching process using a photoresist pattern is performed to remain only in a predetermined portion of the cell region, thereby forming the first interlayer dielectric layer ILD1 12. Etch with. Subsequently, the bit line barrier metal layer 13, the tungsten layer (W; 14) and the hard mask layer (TEOS) 15 are sequentially formed on the entire structure, and then the etching process using the bit line mask is performed. The bit line 10 is formed in the cell region by etching the mask layer TEOS 15, the tungsten layer W 14, and the barrier metal layer 13 in one direction.

Then, the bit line spacer insulating film TEOS and the second interlayer insulating film ILD 2 16 are sequentially formed on the entire structure, and then a predetermined etching process is performed to perform the second interlayer insulating film ILD 2 16. And etching the bit line spacer insulating film TEOS to form bit line spacers 17 on both sidewalls of the bit line 10, and leaving only the second interlayer insulating film ILD 2; do.

Subsequently, a second landing plug 18 is formed between the bit lines 10 to be electrically connected to the first landing plug, and then an etch stopper nitride layer 19 acting as an etch stopper on the entire structure. And the capacitor oxide film 20 are sequentially formed.

Referring to FIG. 1B, an etching process using a photoresist pattern having a predetermined shape in a cell region is performed to sequentially etch the capacitor oxide film 20 and the etch stopper nitride film 19 in a concave type. The capacitor structure pattern of is formed. At this time, the etch stopper nitride film 19 and the capacitor oxide film 20 remain in the peripheral circuit area.

Subsequently, after forming the lower electrode 21 and the dielectric film 22 of the capacitor on the entire structure, the etching process is performed to the peripheral circuit so that the lower electrode 21 and the dielectric film 22 remain only in the cell region. The lower electrode 21 and the dielectric film 22 in the area are removed. Then, the upper electrode 23 of the capacitor is formed on the entire structure, the capacitor 24 is formed in the cell region, and the upper electrode 23 remains on the capacitor oxide film 20 in the peripheral circuit region. do.

Subsequently, after the third interlayer dielectric layer ILD 3 is formed on the entire structure, a contact hole (not shown) is formed by performing an etching process using a metal contact mask to form a metal contact in the peripheral circuit region. . Subsequently, after the metal contact barrier metal layer 26 is formed on the entire structure, a tungsten layer for plug W 27 is formed to fill the contact hole.

Referring to FIG. 1C, the tungsten layer (W) 27 is etched by performing an etch back on the entire structure to form a plug 27a inside the contact hole so as to be separated from other adjacent plugs. do.

As described above, the tungsten (W) is not completely etched at the interface between the cell region and the peripheral circuit region during the etchback process for separating the plug from other adjacent plugs. In order to solve the problem of short-circuit and electrical short and electrical short-circuit between the first metal M1 formed in a subsequent process, overetch is performed so that no residue of tungsten (W) remains on the interface. Therefore, tungsten of the plug is recessed below the third interlayer insulating film, and tungsten is recessed to the upper electrode according to the overetch target. The overetch process causes an attack to be applied to the plug barrier metal layer in contact with the upper electrode, and a predetermined portion of the barrier metal layer is lost to affect the contact resistance between the plug and the upper electrode.

The change in contact resistance according to the height difference (step difference) between the plug and the upper electrode will be described with reference to FIG. 2.

In general, the lower the contact resistance between the plug and the upper electrode, the better. As shown, the step between the plug and the upper electrode should be "1000 k?" To obtain the lowest contact resistance. However, in the prior art, when the recess of tungsten increases due to overetching and the plug is recessed under the upper electrode, for example, when the step between the plug and the upper electrode is "-500 kV", the gap between the plug and the upper electrode is increased. If the contact resistance becomes 110 kV, and the recess of tungsten decreases and the step difference between the plug and the upper electrode is high, for example, "2250 kV", the contact resistance between the plug and the upper electrode becomes 60 kV.

Accordingly, the present invention has been made to solve the above problem, and the lower portion of the capacitor in the lower portion of the metal contact formed in the peripheral circuit region in order to prevent the resistance of the plug and the upper electrode changes rapidly depending on the degree of tungsten recess By forming an electrode, a dielectric film, and an upper electrode and forming a plug thereon, the purpose is to keep the contact resistance constant regardless of the degree of recess of the plug.

1A to 1C are cross-sectional views of a semiconductor device according to the prior art.

2 is a characteristic graph showing a contact resistance ratio according to a step between a plug and an upper electrode.

3A to 3E are cross-sectional views of semiconductor devices in accordance with one embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11, 31: base film 12, 32: first interlayer insulating film

13, 33: barrier metal layer 14, 34, 27, 47: tungsten layer

15, 35: hard mask layer 16, 36: second interlayer insulating film

10, 30: bit line 17, 37: bit line spacer

18, 38: second landing plug 19, 39: etching stopper nitride film

20, 40: capacitor oxide film 21, 41: lower electrode

22, 42 dielectric film 23, 43 upper electrode

24 and 44 capacitors 25 and 45 third interlayer insulating film

26, 46 barrier metal layers 27a, 47a plug

In order to achieve the above object, the present invention provides a semiconductor substrate having a cell region and a peripheral circuit region defined, forming a base film on the semiconductor substrate; Forming a capacitor oxide layer on the entire structure, and then performing an etching process to form a capacitor pattern in the cell region and a plug pattern in the peripheral circuit region; Forming a capacitor on the capacitor pattern and forming a capacitor forming material on the plug pattern; Forming a contact hole in the peripheral circuit region by performing an etching process after forming an interlayer insulating layer on the entire structure; Forming a barrier metal on the entire structure; And forming a plug to fill the contact hole.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3A to 3E are cross-sectional views illustrating manufacturing steps of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 3A, a semiconductor substrate (not shown) in which cell regions and peripheral circuit regions are defined is provided, and an underlayer 31 is formed on the semiconductor substrate through a predetermined deposition process. The base layer 31 may include an isolation layer (not shown) for defining an active region in the semiconductor substrate, a gate electrode formed over the active region, and a source and a drain formed in the active region. And a first landing plug 1 (not shown) formed between a region (not shown) and the gate electrode.

Subsequently, after the first interlayer dielectric layer ILD1 32 is formed over the entire structure, an etching process using a photoresist pattern is performed to remain only in a predetermined portion of the cell region, thereby forming the first interlayer dielectric layer ILD1 32. Etch with. Subsequently, the bit line barrier metal layer 33, the tungsten layer (W; 34) and the hard mask layer (TEOS) 35 are sequentially formed on the entire structure, and then the etching process using the bit line mask is performed. The bit line 30 is formed in the cell region by etching the mask layer TEOS 35, the tungsten layer W 34, and the barrier metal layer 33 in one direction.

Then, the bit line spacer insulating film TEOS and the second interlayer insulating film ILD 2 36 are sequentially formed on the entire structure, and then a predetermined etching process is performed to perform the second interlayer insulating film ILD 2 36. And etching the bit line spacer insulating layer TEOS to form bit line spacers 37 on both sidewalls of the bit line 30, and leaving only the second interlayer insulating layer ILD 2 36 in the peripheral circuit region. do.

Subsequently, a second landing plug 38 is formed between the bit lines 30 to be electrically connected to the first landing plug, and then an etch stopper nitride layer 39 acting as an etch stopper on the entire structure. And the capacitor oxide film 40 is sequentially formed.

Referring to FIG. 3B, an etching process using a photoresist pattern having a predetermined shape is performed on the entire structure to sequentially etch the capacitor oxide film 40 and the etch stopper nitride film 39 to concave the cell region. A capacitor pattern of a concave type is formed and a plug pattern is formed in the peripheral circuit area.

Referring to FIG. 3C, after the lower electrode 41 of the capacitor is formed on the capacitor pattern of the cell region and the plug pattern of the peripheral circuit region, a CMP process using a photoresist pattern is performed on each of the capacitor electrodes. The lower electrode 41 is separated. Subsequently, a dielectric film 42 and an upper electrode 43 are sequentially formed in the cell region and the peripheral circuit region, so that a capacitor 44 is formed in the cell region, and the dielectric film 42 and the upper portion are formed in the peripheral circuit region. A stacked structure of the electrodes 43 is formed. The lower electrode 40 and the upper electrode 42 are formed of TiN, and the dielectric film 41 is formed of TaON. In addition, the upper electrode 42 is formed to a thickness of 1000 to 2000Å.

Referring to FIG. 3D, after the third interlayer dielectric layer ILD 3 45 is formed on the entire structure, a contact hole (not shown) is formed by performing an etching process using a metal contact mask to form a metal contact in the peripheral circuit region. ) Is formed. The third interlayer insulating film (ILD 3) 45 has a silicon oxide film having a thickness of 2000 to 4000 kPa. Subsequently, after the metal contact barrier metal layer 46 is formed on the entire structure, a tungsten layer W 47 is formed to fill the contact hole.

Referring to FIG. 3E, the tungsten layer (W) 46 is etched by performing an etch back on the entire structure to form a plug 47a inside the contact hole so as to be separated from other adjacent plugs. do. The plug 47a overlaps the lower electrode 40, the dielectric film 41, and the upper electrode 42 of the capacitor in the contact hole.

That is, as described above, the biggest feature of the present invention is to form the upper electrode, the dielectric film and the lower electrode of the capacitor under the plug serving as the metal contact, and the lower surface of the plug and the upper surface of the upper electrode of the capacitor By overlapping each other, the contact resistance can be kept constant regardless of the degree of recess of the plug.

The present invention forms a lower electrode, a dielectric film, and an upper electrode of a capacitor under a metal contact formed in a peripheral circuit area to prevent the resistance of the plug and the upper electrode from changing rapidly according to the degree of plug recess. By forming a plug thereon, the plug and the upper electrode overlap each other in a metal contact hole, thereby maintaining a constant contact resistance regardless of the degree of recess of the plug.

It is also possible to increase the margin of the etch back process of the plug without additional mask processing.

Claims (8)

(a) providing a semiconductor substrate in which a cell region and a peripheral circuit region are defined, and forming an underlayer on the semiconductor substrate; (b) forming a capacitor oxide layer on the entire structure, and then performing an etching process to form a capacitor pattern in the cell region and a plug pattern in the peripheral circuit region; (c) forming a lower electrode which is formed along a step of an upper part of the entire structure, and the adjacent ones are independently separated from each other so that the upper portion of the capacitor pattern and the plug pattern are exposed; (d) forming a dielectric film on the lower electrode along a step of the entire structure; (e) forming an upper electrode on the entire structure such that the capacitor pattern and the plug pattern are buried; (f) an interlayer insulating film is formed over the entire structure, and then a portion of the interlayer insulating film and the upper electrode of the peripheral circuit region is etched through an etching process to be formed between the plug patterns, and between the plug patterns. Forming a contact hole so that a portion of the upper electrode remains; (g) forming a barrier metal layer over the entire structure along the inner surface of the contact hole; And (h) depositing a plug material layer on the entire structure to fill the contact hole, and then etching the plug material layer to form an inside of the contact hole through an etching process, wherein the area overlapping the upper electrode is formed. And forming a plug in the contact hole so as to surround the upper electrode at the boundary of the barrier metal layer. delete The method of claim 2, The lower electrode is a method of manufacturing a semiconductor device, characterized in that formed of TiN. The method of claim 2, The dielectric film is a semiconductor device manufacturing method, characterized in that formed by TaON. The method of claim 2, The upper electrode is a manufacturing method of a semiconductor device, characterized in that the TiN is formed to a thickness of 1000 to 2000Å. The method of claim 1, The interlayer insulating film is a semiconductor device manufacturing method, characterized in that the silicon oxide film is formed to a thickness of 2000 to 4000 내지. The method of claim 1, In (h), the etching process is a method of manufacturing a semiconductor device, characterized in that carried out by an etch back or CMP process. delete