KR100404376B1 - Partitioned Crossbar Switch with Multiple Input/Output Buffers - Google Patents

Abstract

The present invention relates to a split crossbar switch that reduces the collision of cells inside the switch by using several small switch elements instead of one switch.

The present invention proposes three types of split crossbar switches. The first split pieces L a conventional single cross bar in the horizontal and the structure positioning the L buffers for each output port, the second split pieces E a conventional single crossbar vertically each of the input ports on the output port dumyeo the E buffers Is a buffer that only holds internal speed-ups. The third is a structure in which a single crossbar is divided into L horizontally, each of which is divided into E vertically, and divided into a total of EL crossbars, each having an L buffer for each output port and an E buffer for each input port. One arbiter is assigned to each crossbar switch element, and if there is a buffer at the output, a scheduler is allocated to schedule a cell to ensure quality of service.

Conventional NxM input buffered switches require one crossbar switch to connect N inputs to M outputs, whereas in split crossbar switches, multiple crossbar switch elements are completely independent of each other. By connecting to smaller or equal number of outputs, the number of competing inputs and outputs in one switch element is reduced, so the collision rate is reduced and better performance can be achieved than the input buffer type switch.

Therefore, the present invention does not require a memory faster than the input link speed, and since the number of internal connection lines is almost the same as that of a conventional crossbar switch, it is easy to implement high speed.

Description

Partitioned Crossbar Switch with Multiple Input / Output Buffers}

The present invention relates to a split crossbar switch having multiple input / output buffers. More particularly, the present invention relates to a split crossbar switch structure that reduces collision of cells in a switch by using several small switch elements instead of one switch. will be.

In the last decade, many researches have been conducted to provide various services in the integrated service network. Many scheduling schemes have been proposed to ensure bandwidth and delay without affecting the flow of service contracts to users who keep service contracts. Work-conserving methods that do not waste processing time when cells remain include virtual clock, delay-EDD (delay-Earlist-Due-Date), WFQ (weighted fair queueing), and WF ² Q (Worst-case Fair Weighted Fair) Queuing, self-clocked fair queuing (SCFQ), and other nonworking-conserving methods such as jitter-EDD, stop-and-go, Hierarchical round robin (HRR) and rate-controlled static priority (RCSP). So far, most of these studies have been done on output buffered switches.

Output buffered switches have many advantages in providing QoS, but have the limitation that the memory speed must be as fast as the sum of the total input speed. Because memory speed growth is less than processor speed growth, current memory speed limits are bottlenecks in high-speed switch implementations. In input buffered switches, the memory speed need not be much faster than the speed of one channel. Thus, at the current state of the art, input buffered switches are more suitable for high speed implementations than output buffered or shared buffered switches.

However, input buffered switches have a limit of only 58.6% throughput for uniform input traffic due to HOL (head-of-line) blocking, but the input buffer is first in first out (FIFO) method. It is known that performance is improved when operating in the same way, and that the output can be increased by 100% by separating and managing the queue for each output buffer by VOQ (virtual output queueing) method in the input buffer. It is becoming.

These switches often take the form of crossbar switches with input buffers. Examples include PMC's TT1 / Enhanced TT1 switch, Cisco's 12000GSR, and 50-Gb / s IP Router. Because Cisco's IP Router performs cell switching internally, when a packet of variable length arrives, the packet is divided into fixed length cells, passed through each cell switch, and then reassembled and exported.

The crossbar switch has an implementation complexity that increases proportionally to N ² in the case of N-port crossbars, and because the collision is resolved at both the input and output ends, the control is more complicated to guarantee QoS, but the structure is simpler. The VLSI chip allows for easy implementation and high speed operation.

In the input buffer type switch that manages the queue by VOQ method in the input buffer, the number of cells that can enter a single input port at a single cell time is conflicted at the input of the switch because you may want to send cells from multiple VOQs. In this case, even though the input is connected to a switch fabric such as a crossbar, cells coming from different inputs may try to go to the same output port. In this case, a collision occurs. To resolve these two conflicts, the input buffered switch uses an arbitration algorithm to determine the order in which each cell in the input buffer will be sent. Such arbitration algorithms include parallel iterative matching (PIM), round-robin matching (RRM), iSLIP, iterative longest queue first (i-LQF), iterative oldest cell first (i-OCF), fair arbitrated round robin (FARR), FIRM (Fcfs In Round-robin Matching).

In the case of input buffered crossbar switches, throughput can be achieved up to 100% depending on the arbitration algorithm. However, input buffered switches are basically based on collisions that occur when cells enter the switch from the input buffer and at the output port of the switch. Because all conflicts must be resolved, there is a limitation that the performance cannot be better than the output buffered switch, which does not occur at the input stage.

The output buffered switch, on the other hand, can deliver all of the arriving cells to the output buffer immediately due to the internal speed-up of the switch, resulting in good performance due to no collision at the input stage, but much faster than the input link speed. There is a disadvantage in that it is difficult to be used for high-speed switching because it requires.

Accordingly, the present invention is to solve the above problems, in the present invention, the switching is performed by using several switch elements instead of one switching element in a structure having a buffer for storing cells at the input terminal in the VOQ method. By reducing the collision rate at the input and output stages, we propose a switch structure that has better performance than the conventional input buffer type switch. In this case, the proposed switch structure does not require an internal speed-up and a high speed implementation is possible because the speed of the memory does not need to be much faster than that of the input link.

As a technical idea for achieving the above object of the present invention, the present invention proposes three types of split crossbar switches.

The first divides the existing single crossbar into L horizontally and puts L buffers for each output port. The second divides the existing single crossbar into E vertically and the internal speed-up on the output port side. In this case, the buffer is placed only in case of an error and E buffers are placed in each input port. The third is a structure in which a single crossbar is divided into L horizontally, each of which is divided into E vertically, and divided into a total of EL crossbars, each having an L buffer for each output port and an E buffer for each input port.

1 is L This is a block diagram of an N × M horizontally divided crossbar switch composed of crossbar switch elements.

2 is a diagram illustrating a transmission request matrix in an N × M input buffer type switch.

3 is L A diagram showing a transmission request matrix for an N × M horizontally divided crossbar switch composed of crossbar switch elements.

4 is a diagram illustrating a synchronized folded wavefront arbitration method (SWWFA).

FIG. 5 is a diagram for describing an unsynchronized folded wavefront arbitration method (DWWFA).

6 is E This is a block diagram of an N x M vertically divided crossbar switch composed of crossbar switch elements.

7 shows LE This is a block diagram of an N × M split crossbar switch composed of crossbar switch elements.

Hereinafter will be described in detail with reference to the accompanying drawings, the configuration and operation of the embodiment of the present invention.

1 is a configuration diagram of an N × M horizontally divided crossbar switch composed of L crossbars.

1, the number L of crossbar elements is a divisor of N. Each input port has an input buffer 101 for storing the cell according to the output port number that the cell wants to go to, and the crossbar switch element 107 connecting N / L inputs and M outputs is L. Each crossbar switch element has one arbiter, and each output port can be scheduled in per-VC or per-class units with L buffers 104 that can store the cells separately according to the input ports through which they have passed. Will have a scheduler 106. i First crossbar switch element Since Connect the input ports up to to the i th buffer of all output ports.

Let's look at the more specific behavior. Once the cell enters the input buffer 101 through the input port, the input buffer stores the cell according to the output port number the cell wishes to pass through. This queuing method is called VOQ (virtual output queueing). In FIG. 1, Q _{i, j} is present in the i th input buffer as a queue 102 of cells to enter through input port i and exit through output port j. Thus, when cells enter the input buffer, they line up in the corresponding queues, depending on the desired output port number. Each queue is served in FIFO mode, that is, the earliest cell is delivered to the output buffer first. However, any i-th input buffer has M virtual output queues 102, which are the number of output ports. Even the cell at the front of the virtual output queue cannot be directly transferred to the output port direction. If the number of queues with one or more cells among the M virtual output queues in the i-th input port is m, the number of cells to be delivered to the output buffer at that time is m . In fact, there is only one cell that can be exported from one input buffer, so if m is two or more, a collision will occur between m cells. This collision is called input contention and the arbiter 103 solves this problem.

Resolving such conflicts in the arbiter allows one of the m HOL (head-of-line) cells to be selected on the i-th input port, but it must be delivered successfully when sent to the desired output buffer. You can't. This is because it can send cells from the i and other jth input ports to the same output buffer. If you increase the speed of memory and do not increase the internal speed-up to more than 1, the number of cells that can be accepted at one cell time in one output buffer is one. Attempting to send them will cause a crash. Such a collision is called an output contention. In FIG. 1, the arbiter 103 serves to solve not only an input collision but also an output collision. As a result of resolving both input and output conflicts in the arbiter, only cells that are granted can be transferred from the input buffer to the output buffer without conflict.

There are a total of L arbiters, one per crossbar switch element 107, and each arbiter operates independently of each other. In order to operate different crossbar switches independently of each other, each output port has L buffers 104 and allocates one buffer to each crossbar. Each output port stores all the cells from the first to N / L input ports in the first output buffer, depending on which input port the incoming cell comes from. N (s-1) / L All cells from the + 1th to Ns / Lth input ports are stored in the sth output buffer. Each output buffer 104 is also queued logically divided according to which input port it came from. When the cell comes from the i th input port to the j th output port The cell is stored in the logical queue OQ _{j, i} 105 of the first output buffer. In addition to queuing by input ports considering QoS, queuing by QoS class or connection can be performed.

The N and L input ports from the first input port use only the first crossbar XB-1 and always use the first buffer for all output ports, so cells from the first to N / L input ports and N There will never be a collision between cells sent from the Nth input ports at / L + 1. Therefore, the first arbiter 103 only needs to resolve a collision that occurs between the first to N / Lth input ports. For the same reason, the next N / L input ports can be arbitrated independently, and the next arbiters are responsible for the function. The k- th arbiter 103 receives the transmission request information through the control signal line 108 at the Nk / L-th input ports at N (k-1) / L + 1, performs arbitration processing, and permits cell transmission according to the result. It informs the N / L input ports and sets the k- th crossbar XB- k 107 that connects the N / L input buffers and the k- th buffer of all output ports. When the output buffer receives the cell through the crossbar, the output buffer is queued by input port, QoS class, or per-VC based on the information about which input port the cell came in through, and the QoS class and flow information. 106 schedules the cells in consideration of QoS. As the scheduling algorithm, various fair scheduling algorithms, including the existing WFQ, can be used.

Next, let's look at the benefits of using multiple independent crossbar switch elements and an arbiter.

The kth arbiter receives the transmission request vector from the N / L input buffers from the N (k-1) / L + 1th input buffer to the Nk / Lth input buffer among the N input buffers. The request vector V _l that the l th input buffer sends to the arbiter Where R _{l, n} is 1 only if the virtual output queue Q _{l, n} has at least one cell in the l-th input buffer, and 0 if no cell is present.

Fig. 2 shows a matrix R of transmission request information sent by each input buffer in the case of an N × M input buffer type switch. The request vectors from each input buffer

The shape of the request matrix created according to FIG. 2 is shown in FIG. 2. For input buffered switches that do not have internal speed-up, only one cell can come out of one input port and one output port goes out at one cell time regardless of which arbitration algorithm is used. Because only cells can be entered, there can only be at most one request for each row, and only one for each column, as the arbitrator performs the arbitration procedure.

3 is a cross-sectional crossbar switch of size NxM Shows the form of the request matrix when L crossbar elements are used.

Comparing this request matrix with the form of the request matrix required for arbitration in the input buffer type switch of FIG. 2, it can be seen that there is a difference that a dividing line enters every N / L rows. As mentioned above, the first N / L input ports transmit a cell regardless of the remaining N - N / L input ports. Likewise, the next N / L input ports Because the cells are transmitted regardless of the remaining N - N / L input ports, the input ports can be grouped by N / L in order, so that each group can be arbitrated completely independently regardless of other groups.

Thus, as N (k-1) / L + 1 -th set of transmission requirements belonging to from row Nk / L row k group (G _k) in FIG arbitration for the k-th group (G _k) is It can be made irrespective of transmission requests belonging to other groups. In the conventional input buffer type switch as shown in FIG. 2, only one permission may exist in one column, so that there may be a case where there is a competition for N requests belonging to the same column. However, a switch structure having multiple output buffers as shown in FIG. 3. It is easy to see that up to L grants can be given in one column, and the number of transmission requests competing in the same column is also reduced to a maximum of N / L , making it more likely to be granted than a conventional input buffered switch. have. Since the collision rate occurring at the inlet of one output buffer is lower than the collision rate occurring at the output of the conventional input buffer type switch, the output collision rate actually experienced by the cell is reduced.

Therefore, the cells at the input stage are more easily transferred to the output buffer, and if the cells at the input stage are well transferred to the output buffer, the number of cells remaining in the input buffer is reduced than the input buffer type switch, thereby reducing input contention. do. As a whole, since input collision and output collision are reduced, I / O buffered switch with multiple output buffers shows better performance than conventional input buffered switch.

The following arbitration algorithms can be used for the L independent arbitrators. First, FIG. 4 is a diagram illustrating a synchronized wrapped wave-front arbitration (SWWFA). In Fig. 3, the arbitration process for one group has an element of '1' or '0'. In the matrix, '1' is selected so that at most one row and each column does not exceed one. This is a process of selecting the number of '1's as many as possible. In order to select one '1' for each row or each column, transmission request signals should be examined. In FIG. 4, it is not possible to determine whether to permit transmission at the same time for R _1,1 and R _1,2 . The total number of permits must not exceed one for the first row, so if one of R _1,1 and R _1,2 is granted, the other cannot be granted. The reason why it is not possible to determine whether to permit R ₁ , ₁ and R _1,2 at the same time is because these two transmission requests are in the same row. For the same reason, it is not possible to determine whether permission is granted at the same time for transmission requests in the same row.

By the way, in the case of part of the same row in the fourth column of FIG does not belong FIG R _1,1 and R _2,2 is that R _1,1 to permit determination of the R is _2,2 do not get the license is no batneunya Does not affect Likewise, granting or _disallowing R _2,2 has no effect on whether R _1,1 is accepted or not. Only when deciding whether R _1,1 or R _2,2 is permitted will we consider only the request for which the row or column it belongs to has been granted first. As described above, since it can be independently determined whether or not requests belonging to the same row and not belonging to the same column can be performed independently, it does not matter if they are performed at the same time.

In Fig. 4, the numbers in parentheses indicate an order of determining whether to permit each request.

Initially, the transmission requests in the diagonal direction in the first group (G ₁ ) Determine whether to allow in parallel. If the request value is '1', the grant is granted to the request because the grant does not exist before the first start, and at the current arbitration stage for each row and each column to grant no more permission to the rows and columns to which the request belongs. A register is stored to remember whether or not an error occurred, and as soon as the permission is generated, a '1' is stored in the register (RR [ i ]) of the corresponding row (i) and the register (CR [ j ]) of the corresponding column (j). Remember the occurrence.

In the next step, it is determined whether or not permission is granted for the requests in (2) in FIG. 4, and only when the request value is '1' and the register values of the registers and columns of the row to which the row belongs are '0'. If a permit is granted and all three conditions are not met, the request will not be granted. If a grant is granted to a request under (2), the register of the row and the register of the row to which the request belongs is set to '1'. In this way, if the mediation process is carried out in the order of the number in parentheses, the mediation process is completed in M times when N / L ≤ M. In the case of N / L> M, arbitration will be completed in N / L times. After the arbitration, all row registers (RR [·]) and column registers (CR [·]) are set to '0' and the next arbitration is prepared. The hatch request to start the arbitration always has a high priority, thus changing the starting position each time. The starting position may continue to cycle in the direction of increasing number in parentheses in FIG. 4, or may cycle in a decreasing direction.

So far, only the mediation process for the first group (G ₁ ) has been described. As described above, since the mediation process for each group can be completely independent, the mediation process for other groups will be conducted in the same way as described in the first group. Can be. Figure 4 shows how all the groups up to the last group to mediate in the same way as the first group. By the way, although the starting point of each group may be unified to all groups to start in the same position of the diagonal line, each group may be different from the starting point of the arbitration process. The case of unified arbitration start lines of all groups is the same as in FIG. 4, and the case of different arbitration start lines of all groups is shown in FIG. 5.

As shown in FIG. 5, a method of arbitrating the mediation start line of all groups differently is referred to as a desynchronized wrapped wave-front arbitration (DWWFA). In FIG. 5, when M≥N, the mediation start position for the first group is an oblique line over the first N / L columns, and the mediation start position for the second group is an oblique line over the next N / L columns, and the kth group The starting position for the mediation is for the diagonal lines spanning the N (k-1) / L + 1 th through the Nk / L th columns so that no diagonal lines share the same row. In the case of MNs, it is not possible to make sure that all the starting lines do not share a single column. The unsynchronized folded wavefront arbitration method differs from the synchronized folded wavefront arbitration method in that each group has a different starting position of the arbitration. The other mediation process is the same as the synchronized folded wavefront arbitration method.

By unifying the start of the arbitration process for all groups in the same rows, the cells are driven to the same output port under high load. However, shifting the start position of each group's arbitration process allows cells to be evenly distributed among the output ports under high load. Rather than driving the cells in the same output port direction at the same time, it is possible to increase the utilization of the output ports as a whole by allowing the cells to be distributed among the possible output ports.

So far, we have looked at crossbar switches that are split horizontally, and then we will look at crossbar switches that are split vertically.

6 is E The structure of an NxM vertically divided crossbar switch consisting of crossbar switch elements is shown. Each input port 601 has E buffers 602 and one arbiter 605 is assigned per crossbar switch element 606. Basically, since the operation is similar to the input buffer type switch, there is no output buffer at each output port if there is no internal speed-up, but at least one cell for one cell time if the internal speed is up. Since it can be forwarded to one output port, there is a buffer 607 at each output port. Within the output buffer, cells may be stored separately according to the input port number passed by the cells, may be stored by class, or may be stored separately by connection (608). The scheduler 609 plays a role in ordering and exporting cells stored in the connected buffer in consideration of QoS.

Cells input to each input port are stored in the corresponding virtual output queue 603 according to the output port number to the input port. Unlike the existing input buffer type switch, the virtual output queue is divided into E buffers rather than existing in one buffer. It will exist. The first M / E of the M virtual output queues 603 are in the first buffer 602 of each input port, the next M / E are in the second buffer, and thereafter the M / E are It is allocated in the next buffer. When the i-th input port 601 cell arrives, the splitter 604 determines the cell's destination output port number and locates the cell destined for the j-th output port. Buffer 602 Cell is sent to the virtual output queue Q _{i, j} in its buffer. K-th buffer 602 for each input port 601 is the k-th crossbar switch element 606 is connected to the XB- k, a k-th buffer of each input port M (k-1) / E + 1 Since only cells destined for Mk / E output ports are stored, the kth crossbar switch element is the cell destined for M (k-1) / E + 1 to Mk / E output ports regardless of other crossbar switch elements. Only need to switch. When the crossbar switch is vertically divided as described above, the number of output ports that the arbiters 605 connected to each crossbar switch element 606 need to be reduced is reduced. In other words, when switching N inputs to M outputs using one crossbar switch, M virtual output queues compete at each input of the crossbar switch to send a cell. Splitting into two reduces the number of virtual output queues competing at the input of each crossbar switch from M to M / E, thus reducing cell collisions, resulting in better performance than conventional input buffered switches.

So far, we have looked at horizontally divided crossbar switches and vertically divided crossbar switches. Finally, we will look at the more common split crossbar switches that split in both horizontal and vertical directions.

7 shows LE The structure of a typical N × M split crossbar switch consisting of crossbar switch elements is shown.

Referring to FIG. 7, each input port 701 has E buffers 702, one arbiter 705 is assigned per crossbar switch element 706, and each output port is L separate buffers 707. Has If you divide one crossbar switch of size N × M into L horizontally and E equally vertically, LE The crossbar switch element 706 comes out. In this case, if the crossbar switch element in the j-th column of the i-th row is XB- ij , XB- ij is the input port from N (i-1) / L + 1 to N i / L and M (j-1 ) / E + 1 to M j / E for connecting output port.

More specifically, the jth buffer 702 of the N (i-1) / L + 1 to N i / L input ports and the M (j-1) / E + 1 to M j / E output ports The i th buffer 707 is connected. In a special case, when E = 1, that is, when not divided in the vertical direction, the structure is the same as that of the horizontally divided crossbar switch in FIG. 1, and when L = 1, that is, when not divided in the horizontal direction, It becomes the same structure as the vertically divided crossbar switch of 6.

The distribution of cells from the input stage to each buffer is done as in the vertically divided crossbar switch of FIG. When a cell arrives at the kth input port 701, the divider 704 determines the cell's destination output port number and locates the cell destined for the lth output port. First buffer (702) Cell is sent to the virtual output queue Q _{k, l} in its buffer. This cell is Of the first row When a pass grant signal is received through the arbiter 705 in the first column, the crossbar switch element 706 managed by the arbiter passes through the l th output port. The cell is transferred to the first buffer 707 and stored in the logical queue OQ _{l, k} 708 according to the input port number k passed by the cell in the buffer. Within the logical queue according to the input port number, the queue can be further classified according to class and connection information, and the scheduler 709 at the end of the switch is stored by input port, service class, or connection. Cells are scheduled in consideration of QoS.

LE instead of one crossbar switch as shown in FIG. If crossbar switch elements are used, E buffers are placed at each input end, and L buffers are placed at each output end, and each crossbar switch element completely separates the buffers used at each input end or each output end. Cells delivered through the device are completely separated from each other until they enter each input port 701 and are divided into different buffers 702 through the divider 704 and exit the switch through the scheduler 709 at the output. It moves through a separate path.

Therefore, each of the LE crossbar switch elements can operate regardless of the other switch elements. When using one crossbar switch for N × M switching, one arbiter must solve the N-to-M matching problem, but using LE crossbar switch elements as shown in FIG. 7 instead of one N-> M matching problem. This is done by solving LE (N / L)-> (M / E) matching problems. This means that the number of virtual output queues competing at the input of one crossbar switch element is reduced from M to M / E, and the number of inputs competing at the output is reduced from N to N / L. This increases the probability that cells in the input buffer will be delivered to the output buffer.

According to the split type crossbar switch according to the present invention as described above has the following advantages.

The output buffer type switch has a disadvantage of requiring a high speed memory, and the input buffer type switch has been widely used in recent years by overcoming the disadvantage of low yield. However, unlike the output buffered switch, the input buffered switch has a fundamental limitation such as cell collision at the input stage.

First, the present invention can overcome the limitation of the input buffer type switch by using several small crossbar switches instead of one crossbar switch.

If you divide one crossbar switch into L horizontally and leave L buffers for each output port, the subset of input ports competes for each buffer in the structure where all input ports compete for one output. Due to the lack of competition, the probability of passing a cell from an input port to an output buffer is higher than that of a conventional input buffered switch from each input port to an output port.

Dividing a crossbar switch into longitudinal pieces E, for each input port, leaving the E discrete buffer stretched the number of input gates on the structure to M virtual output queues are competing for one of the input gates on each input port pieces E Since M / E virtual output queues compete for one input gateway, the competition rate between virtual output queues is lowered, so that the probability of cell transfer from the input port to the output buffer is higher than that of the conventional input buffer type switch. Will increase.

LE instead of one crossbar switch The use of a crossbar switch elements, the number of each crossbar input to compete the number of virtual output queues competing in the switch device input terminal decreasing from M to M / E at the same time with a single output stage also are reduced from N to N / L As a result, the collision rate is further reduced compared to the case of splitting only in the horizontal or vertical direction. As such, when one crossbar switch is divided into the horizontal, vertical, or horizontal direction at the same time, the competition rate of the cell at the input terminal or the output terminal is lowered, thereby increasing the probability that the cell is transferred from the input terminal to the output terminal. Will be displayed.

Second , in the present invention, when the size of the switch is N × M, the number of buffers required is about N or M constant multiples ( L or E ), and does not require a memory that is much faster than the input link speed. Field-to-output buffers are also suitable for high speeds, as the number of internal wires that connect them to the output buffers is similar to the number of connections required for conventional crossbar switches.

Claims (7)

Cells arriving through input ports are classified by output ports and stored in the form of virtual output queues (VOQs). For each virtual output queue, the existence of cells is determined. An input buffer for sending a request vector containing information of non-transmission request ('0') if none; Of L that is the number of input and output ports N, connecting the input port to the i-th element is N (i-1) / L + Ni / L times from the number 1 when M in the i-th buffer of all output ports A crossbar switch element; An arbiter assigned to each crossbar switch element to solve a matching problem from N / L inputs to L outputs and to set a crossbar switch element according to the result; An output buffer for storing and managing a cell that has passed through the crossbar switch element according to input port information passed by the cell, according to a class of traffic to which the cell belongs, or according to a flow to which the cell belongs; Wherein each output port is allocated one by one scheduler for managing the L output buffers, and the scheduling in consideration of the cells that belong to the L output buffers QoS; including A split type crossbar switch, characterized in that the device receives a fixed length cell and sends the cell to a desired output port direction. The method according to claim 1, A register (RR []) for storing whether there is an authorized request for each row; A register (CR []) for storing whether there is an authorized request for each column; As the above elements, the number of input ports is N, the number of output ports is M, the number of buffers per output port is L, and N (k-1) / L + 1st input buffers to Nk / Lth input buffers. When the set of k is called the kth group, the input buffers belonging to the kth group For a request matrix, we first select a set of requests belonging to min (N / L, M) all different rows and columns, and start with that set to find the requests to grant the transfer, and if it finds a request to grant, Remember that a grant has occurred in the register for a row, remember that a grant has occurred in the register for the column to which the request belongs, and then continue to select an independent set of min (N / L, M) requests among the remaining requests. Repeat the above arbitration process NM / L / min (N / L, M) times to finally determine the request to authorize transmission at the current cell time, and then transfer the set of requests to start arbitration at the next cell time. A split crossbar switch, characterized in that it further comprises a k- th arbiter different from the time. The method according to claim 1, kth arbiter that resolves cell conflicts for the kth group ( )Wow; And the L arbitrators taking in the same column of the request matrix a set of requests for commencing arbitration in all arbitrators at every cell time as said element. The method according to claim 1, kth arbiter that resolves cell conflicts for the kth group ( )Wow; And an L arbiter such that the set of requests for starting arbitration in each arbiter at every cell time are always staggered without sharing columns in the request matrix. Type crossbar switch. When a cell arrives, look at the output port number (j) it wants to go to A distributor to send to the first buffer; E buffers for each input port, each cell arriving through the input port for each output port is stored in the form of a virtual output queue, and sends a request vector to the arbiter every cell time; When the number of input ports and output ports is N, M , the i device connects the i-th buffer of all input ports to the output ports from M (i-1) / E + 1 to M i / E. doggy A crossbar switch element; An arbitrator assigned to each crossbar switch element to solve the matching problem from N inputs to M / E outputs and to set the crossbar switch elements according to the result; A split type crossbar switch, characterized in that the device receives a fixed length cell and sends the cell to a desired output port direction. When a cell arrives, look at the output port number (j) it wants to go to A distributor to send to the first buffer; E buffers for each input port, each cell arriving through the input port for each output port is stored in the form of a virtual output queue, and sends a request vector to the arbiter every cell time; When the number of input ports and output ports is N, M , the i device connects the i-th buffer of all input ports to the output ports from M (i-1) / E + 1 to M i / E. doggy A crossbar switch element; An arbiter assigned to each crossbar switch element to solve a matching problem from N inputs to M / E outputs and to set a crossbar switch element according to the result; Depending on the input port information that the cell has passed through the cell that passed the crossbar switch for internal speed-up or for scheduling that takes into account quality, or depending on the class of traffic to which the cell belongs, Or an output buffer for storing and managing the cell according to the flow to which the cell belongs; A scheduler for allocating one of each output port and scheduling the cells stored in an output buffer in consideration of QoS. A split type crossbar switch, characterized in that the device receives a fixed length cell and sends the cell to a desired output port direction. When a cell arrives, look at the output port number ( j ) it wants to go to A distributor to send to the first buffer; E buffers for each input port, each cell arriving through the input port for each output port is stored in the form of a virtual output queue, and sends a request vector to the arbiter every cell time; When the number of input and output ports is N, M , k ( L of line 1 The device in column 1 sets the lth buffers of the input ports from N (k-1) / L + 1 to N k / L from M (l-1) / E + 1 to M l / E. LE to connect to the kth buffer of the output port of A crossbar switch element; An arbiter assigned to each crossbar switch element to solve a matching problem from N / L inputs to M / E outputs and to set a crossbar switch element according to the result; L cells are allocated to each output port and stored according to the input port information passed by the cell, the class of the traffic to which the cell belongs, or the flow to which the cell belongs. An output buffer for managing; Wherein each output port is allocated one by one scheduler for managing the L output buffers, and the scheduling in consideration of the cells that belong to the L output buffers QoS; including A split type crossbar switch, characterized in that the device receives a fixed length cell and sends the cell to a desired output port direction.