KR100399936B1 - Method for fabricatingin ferroelectric device - Google Patents

Abstract

The present invention provides a ferroelectric device and a method for manufacturing the ferroelectric device capable of obtaining a stable ferroelectric thin film having excellent film quality by acting as a stable diffusion barrier even at high temperature, the manufacturing method of the ferroelectric device of the present invention for this purpose on Patterning an interlayer insulating layer in to form a hole; Forming a recessed plug in the hole; Alternately depositing a metal buffer layer and a metal oxide on the plug to form a multi-layer diffusion barrier layer having an increased thickness of the metal oxide; And forming a capacitor electrode on the multilayer diffusion barrier layer.

Description

Method for manufacturing ferroelectric device {Method for fabricating in ferroelectric device}

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a ferroelectric element.

By using ferroelectric materials in capacitors in semiconductor devices, development of devices capable of using a large-capacity memory while overcoming the limitation of refresh required in conventional DRAM devices has been in progress.

A ferroelectric random access memory (FeRAM) device is a nonvolatile memory device that has the advantage of storing stored information even when the power supply is turned off, and its operation speed is comparable to that of a conventional dynamic random access memory (DRAM). Be in the spotlight.

When using a ferroelectric thin film as a nonvolatile memory device, the signal is input by adjusting the direction of polarization in the direction of an electric field applied to the ferroelectric thin film, and the digital signals 1 and 0 are determined by the direction of residual polarization remaining when the electric field is removed. Is to use the principle of storage.

Ferroelectric thin films, such as PZT and BST, have high dielectric constants of more than several hundreds and exhibit spontaneous polarization under Curie temperature and thus have polarization in the absence of an electric field. It is becoming. When using ferroelectric capacitors as DRAM cell capacitors, the dielectric constant is more than 10 times higher than that of conventional Ta2O5, which has the advantage of ensuring sufficient capacitance even in a small capacitor area. For this reason, many developments have been made on ferroelectric capacitors using BST thin films as cell capacitors in handwritten bit DRAM.

On the other hand, even in the case of the FRAM utilizing the nonvolatile characteristics of the ferroelectric thin film, research on ferroelectric thin film capacitors such as PZT, SBT, and the like has been actively conducted and commercialized. Most ferroelectric thin films including the above ferroelectric thin films are characterized by containing a large amount of oxygen.

Therefore, when the ferroelectric thin film is used as a dielectric material of the memory capacitor, it is necessary to use a metal thin film for both the upper and lower electrodes of the capacitor. When the ferroelectric thin film is directly formed on the polysilicon without the metal thin film, the SiO 2 thin film is formed at the interface by reacting with the oxygen component and the polysilicon contained in the ferroelectric thin film. In this case, the overall dielectric constant is reduced, and the advantage of using the ferroelectric thin film is lost. Therefore, in the case of a capacitor using a ferroelectric thin film, it is common to use a metal electrode.

1 is a cross-sectional view of a capacitor of a ferroelectric device according to the prior art.

Referring to FIG. 1, a first interlayer insulating layer 15 is formed on a substrate 10 on which an isolation layer 11, a gate structure 13, an active region 12, and a bit line 14 are formed.

A contact hole connected to the active region 12 of the semiconductor substrate is formed through the first interlayer insulating layer 15. The contact hole is formed of the storage node contact plugs 16, 17, and 18 formed of the polysilicon 16 and the metal buffer layer 18.

Subsequently, the lower electrode 19, the ferroelectric 20 and the upper electrode 21 are deposited and patterned to complete the capacitor.

The active region 12 of the transistor and the capacitor are connected by a polysilicon 16 plug. In the case of DRAM, the charge is stored, and in the case of the FRAM, the polarization direction is used.

As the metal electrodes 19 and 21 of the ferroelectric thin film, a noble metal array such as Pt, Ru, Ir, or the like is used. At this time, since the ferroelectric 20 is accompanied by a deposition or subsequent heat treatment at a high temperature, oxygen components included in the thin film when the ferroelectric 20 is formed are diffused through the lower electrode 19 so that the polysilicon 16 plugs. In order to solve the problem, the diffusion barrier 17 is used to prevent the diffusion of oxygen.

Since the diffusion barrier 17 is used to prevent the diffusion of oxygen, a material that does not react with oxygen or a material that does not lose conductivity even when reacted with oxygen should be selected. In general, TiN, a diffusion barrier material, is not suitable as a diffusion barrier material for ferroelectric capacitors because it easily reacts with oxygen to form an insulator.

Therefore, as the diffusion barrier 17 of the ferroelectric capacitor, conductive metal oxide materials such as IrO 2 and RuO 2 that maintain conductivity even when reacted with oxygen are mainly used.

For example, the lower electrode 19 may be used as iridium (Ir), and the diffusion barrier film 17 may be used as IrO 2. At this time, a thin layer of Ir is used as the metal buffer layer 18, which is a layer that is used in a thin thickness so as not to react with the polysilicon 16 when the diffusion barrier 17 is deposited with IrO2.

The metal oxide (eg IrOx) used as the diffusion barrier 17 shows stable properties up to a temperature of 500 to 600 ° C., but at higher temperatures, oxygen contained in the metal oxide is diffused downward again to form a polysilicon plug. In response, a problem arises in that the contact resistance of the portion is increased to cause a malfunction of the device.

FIG. 2 shows the result of measuring the component distribution for each depth before and after heat treatment by heat treatment of the component distribution of A-A 'of FIG. 1 using 600 ° C. structure using Augur eletron spectroscope.

Referring to FIG. 2, it can be seen that even in the heat treatment at 600 ° C., the oxygen component in the diffusion barrier film 17 is diffused to the polysilicon interface. This degree of diffusion is expected to have a very significant effect on the electrical properties such as contact resistance. For this reason, in the prior art, the process temperature for the ferroelectric thin film and subsequent processes is made to be 500 ° C or less.

However, this method is difficult to obtain a thin film having excellent characteristics because it does not give enough temperature when the ferroelectric thin film is deposited, and as a result, the development of a method that can play a stable role in the diffusion barrier even at a temperature above 600 ℃ is urgently required. .

An object of the present invention is to provide a ferroelectric device in which a capacitor diffusion barrier layer of a ferroelectric element is formed in multiple layers, and thus the diffusion barrier layer is stable even at high temperatures to obtain a ferroelectric thin film having excellent film quality.

1 is a cross-sectional view of a capacitor of a ferroelectric element according to the prior art.

2 is an experimental graph of the component distribution of the plug of the ferroelectric element according to the prior art.

3A-3C illustrate a preferred embodiment of the present invention.

Figure 4 shows the experimental results of the preferred embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings.

30: interlayer insulating layer 31: contact plug

32: metal buffer layer 33: diffusion barrier

34: lower electrode 35: ferroelectric

36: upper electrode

In order to solve the above problems, the present invention comprises the steps of forming a hole by patterning the interlayer insulating layer on the substrate is completed a predetermined process; Forming a recessed plug in the hole; Alternately depositing a metal buffer layer and a metal oxide on the plug to form a multi-layer diffusion barrier layer having an increased thickness of the metal oxide; And forming a capacitor electrode on the multilayer diffusion barrier layer.

In the present invention, the diffusion barrier formed of the metal oxide sufficiently serves to prevent diffusion of oxygen down from the ferroelectric, while in the subsequent heat treatment process of 600 ° C. or higher, the oxygen component contained in the metal oxide itself is In order to eliminate the cause of separation and diffusion to oxidize the interface with polysilicon to increase the contact resistance, the metal oxide diffusion barrier is formed in multiple layers, and the portion close to the ferroelectric contains a large amount of oxygen components contained in the diffusion barrier. Blocks the oxygen component diffused down from the thin film, and the lower portion of the diffusion barrier layer contains a small amount of oxygen component to suppress the amount of oxygen diffused to the lower portion of the polysilicon even in the subsequent high temperature heat treatment process I am doing it.

That is, the upper end of the metal oxide diffusion barrier serves to block the amount of oxygen diffused down from the ferroelectric, and the lower end is designed to contain less oxygen component that oxidizes polysilicon even at high temperature.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

3a to 3b show a preferred embodiment of the present invention.

First, referring to FIG. 3A, an interlayer insulating layer 30 is deposited on a substrate on which a predetermined process is completed, and a contact hole connected to an active region (not shown) of a semiconductor substrate is formed. The contact plug 31 is formed of the contact hole using polysilicon, and the metal buffer layer 32 and the diffusion barrier layer 33 are formed in an Ir / IrO 2 structure. The thickness of the metal buffer layer 32 is formed in the range of 100 to 300 kPa, and Ru may be used instead of Ir. In the case of forming IrOx with the diffusion barrier 33, an Ir thin film is generally deposited and an oxygen gas is introduced into the chamber to react Ir and oxygen to deposit an IrO2 thin film.

Subsequently, the lower electrode 34, the ferroelectric 35, and the upper electrode 36 are deposited and patterned to complete the capacitor.

FIG. 3B shows only an enlarged portion of the diffusion barrier 33 of FIG. 3A.

Looking at the formation process of the diffusion barrier 33 in detail, to form a metal oxide on the Ir deposited by the metal buffer layer 32, the amount of oxygen is initially reduced, the amount of oxygen contained in the metal oxide in the second half Try to increase by this height. The metal oxide diffusion barrier 33 (GDB) IrO 2 produced in this manner gradually blocks the amount of oxygen diffused from the ferroelectric thin film, and is supplied from the metal oxide itself and diffused into polysilicon. The amount of can also be reduced.

As shown in FIG. 3B, the diffusion barrier layer containing a large amount of oxygen is formed. Due to the metal oxide diffusion barrier layer formed as described above, the process may be performed by increasing the deposition temperature of the ferroelectric thin film to 700 ° C., and the thickness of the metal oxide diffusion barrier layer may be formed to be 500 Å or more to increase the oxygen blocking effect.

However, it will be very difficult to form and control precisely the amount of oxygen in the metal oxide according to the depth. This is because the oxygen mixing ratio at which each substance forms a stable phase is determined.

Accordingly, a structure for more easily applying the concept of FIG. 3B is shown in FIG. 3C.

In order to achieve the effect of FIG. 3B, instead of gradually reducing the amount of oxygen in the diffusion barrier made of metal oxide, as shown in FIG. 3B, the amount of oxygen is fixed and the thickness of the metal oxide thin film layer and The method of obtaining the effect of Fig. 3B by varying the thickness is used.

Referring to Figure 3c, the thickness of each layer of the diffusion barrier film is the largest thickness of the metal oxide layer (t1) of the uppermost and the thickness (t3) of the metal oxide layer of the lowermost and at the same time inserted in the middle The thicknesses t4 and t5 of the metal buffer layers to be fixed are formed. Here, t1, t2, and t3 are metal oxides, which are gradually thickened with IrO2, and t4, t5 are formed with a metal buffer layer having a constant thickness (within 100 to 300 kPa). For example, the first thickness of the metal oxide may be in the range of 10 to 15 kPa, the second thickness in the range of 20 to 30 kPa, and the third thickness may be 100 kPa or more.

Instead of Ir, Ru may be used as the metal buffer layer, and the metal oxide may be formed of IrO 2 or RuO 2.

Due to the metal oxide diffusion barrier formed as described above, the process may be performed by increasing the deposition temperature of the ferroelectric thin film to 700 ° C.

4 is an experimental diagram showing contact plug resistance (vertical axis) with respect to temperature (horizontal axis) during heat treatment for 10 minutes in an oxygen atmosphere at 760 torr, in order to evaluate the effect of the multilayer metal oxide diffusion barrier as a diffusion barrier of the capacitor of the ferroelectric element. to be. This is achieved by contacting with polysilicon after subsequent heat treatment at each temperature when the diffusion barrier structure (B) is formed in a multilayer (A) and the multilayer shown in FIG. The resistance is measured.

In the experiment, in the conventional diffusion barrier structure (A), Ir used as the lower electrode was 80 nm, IrO 2 used as the diffusion barrier was formed at 50 nm, Ir used as the metal buffer layer was formed at 30 nm. In the diffusion barrier structure, Ir used as the lower electrode was formed at 80 nm, and Ir used as the metal buffer layer was formed at 30 nm, and the multilayer diffusion barrier formed similar to the thickness of the existing IrO 2 layer. This is to exclude the effect on thickness.

In the case of using the conventional diffusion barrier film, it can be seen that the contact resistance rapidly increases at 500 ° C. or higher, indicating that the surface of the polysilicon plug is rapidly oxidized at 500 ° C. or higher. On the other hand, looking at the results of the multilayer diffusion barrier proposed by the present invention, it can be seen that there is no significant change in resistance up to 700 ° C.

The multilayer metal oxide diffusion barrier can improve its role as a diffusion barrier by changing the composition of not only the metal oxide but also other compound thin films used as the diffusion barrier.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and the present invention belongs to various permutations, modifications, and changes that can be made without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

According to the present invention, by forming only a diffusion barrier by controlling only the amount of oxygen introduced during manufacture without changing materials and adding process steps, it is possible to increase the deposition temperature of the ferroelectric while maintaining a low contact resistance, thereby making an excellent film quality ferroelectric thin film. You can get it.

Claims (9)

delete delete delete delete Forming a hole by patterning an interlayer insulating layer on the substrate having a predetermined process; Forming a recessed plug in the hole; Alternately depositing a metal buffer layer and a metal oxide on the plug to form a multi-layer diffusion barrier layer having an increased thickness of the metal oxide; And Forming a capacitor electrode on the multilayer diffusion barrier layer Method of manufacturing a ferroelectric element comprising a. The method of claim 5, A method of manufacturing a ferroelectric element, wherein Ir or Ru is used as the metal buffer layer. The method of claim 5, The metal buffer layer is a method of manufacturing a ferroelectric element, characterized in that the thickness of 100 ~ 300 Å range. The method of claim 5, The metal oxide is a method of manufacturing a ferroelectric device, characterized in that using IrO2 or RuO2. The method of claim 5, The metal oxide is a ferroelectric device manufacturing method, characterized in that the thickness increases in the range of 10 ~ 100Å.