KR100398867B1 - Data interpolation apparatus for use in a digital television - Google Patents

Abstract

The present invention relates to an apparatus for 1: 2 interpolation of digital image data in digital television. The 1: 2 data interpolation apparatus of the present invention aims to write interpolated data in the interpolation filter back to the data memory by utilizing half of a read period for reading data to be interpolated from the data memory. Accordingly, the present invention generates an address signal such that interpolated image data output from the interpolation filter is sequentially stored in the n data memories at every clock period of the system clock CLK by the control means, and n / every two clock periods. An address signal is generated so that two data are provided from the n memories to the interpolation filter, and the data distribution means is interpolated from the interpolation filter every clock period in synchronization with the address signal of the control means. To be sequentially input to the n memories.

Therefore, it is not necessary to use a separate filter memory for storing interpolation data, and it is possible to utilize system bus resources that are wasted every per cycle.

Description

Image data interpolation device of digital TV {DATA INTERPOLATION APPARATUS FOR USE IN A DIGITAL TELEVISION}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus for digital television, and more particularly, to an apparatus for interpolating digital video data.

Television, one of the representative media of modern society, is developed by introducing digital technology with the advent of the digital era, and recently, it is being developed into digital television such as high definition television (HDTV). Digital TVs such as HDTVs are attracting attention as new media that can maximize the realism by increasing the clarity, compact disc quality, and aspect ratio of the screen, compared to conventional analog TVs.

Since the quality of a television's screen is proportional to the signal received by the receiver, no matter how large the screen can be, if the amount of information received is the same, the screen will be blurred and the image quality will be lower. The technique of increasing the number of scan lines forming a frame is used. As is well known, the US NTSC standard has 525 scan players, while the European PAL and SECOM systems have 625 lines, whereas digital TVs, such as HDTV, now double the number of scan lines of traditional analog television. It can provide five times more information and dramatically improve image quality.

In order to display a video signal on a digital television, an image signal consisting of a series of image "frames" must be converted into a digital form and transmitted to the digital television. However, since the usable frequency range of a conventional transmission channel is limited, in order to transmit a large amount of digital data, the amount of data transmitted is compressed to reduce the amount. Among these compression techniques, the hybrid coding scheme combining probabilistic coding and temporal and spatial compression is known to be the most efficient. A video signal compressed using such an encoding method is transmitted to a receiver and decoded to be reproduced as a desired video signal.

On the other hand, although digital television has a resolution of 1920 x 1080, since decoded digital image data is applied at 640 x 480 or 704 x 480 resolution, an interpolation filter is used to match the resolution of 1920 x 1080 of digital television. The necessary image data should be generated by interpolation by up filtering. Interpolation of image data generates at least one or more new pixel data using one image data, that is, pixel data. In general, interpolation principle creates an interpolated pixel value by selecting an intermediate value between a series of pixel data. Giving is used.

A typical interpolation filter device interpolates a data memory for receiving and storing digital image data and a plurality of digital image data read from the data memory, that is, intermediate pixel data using pixel data to generate new pixel data. It consists of. At this time, the pixel data interpolated by the interpolation filter is stored in the filter memory for interpolation of new pixel data.

However, when the interpolator performs the 1: 2 interpolation filtering process, since the number of data read from the data memory is only 1/2, the time using the system bus of the actual memory is only 1/2. For this reason, the control of the entire system is complicated and wastes of system bus resources, and since the interpolation filter memory other than the data memory for storing the image data is used separately, the memory is doubled.

Therefore, an object of the present invention is to provide a digital image data interpolation apparatus for utilizing the resources of a memory bus in a digital image data interpolation apparatus.

A 1: 2 interpolation apparatus of digital image data according to the present invention for achieving the above object is performed by using one piece of image data interpolated therefrom using n pieces of image data input at every clock period of a system clock CLK. An interpolation filter to output; N memories each storing n video data in parallel; An address signal is generated so that interpolated image data output from the interpolation filter is sequentially stored in the n memories every clock period of a system clock CLK, and n / 2 data are stored in the n memories every two clock cycles. Control means for generating an address signal to be provided to the interpolation filter from the second to the interpolation filter; And distributing means for distributing interpolated data output from the interpolation filter sequentially into the n memories at every clock period in synchronization with the address signal of the control means.

In addition, the 1: 2 image data interpolation apparatus of the present invention includes data collision prevention means for delaying the interpolation data by one clock in order to prevent collision between data read from the data memory and data interpolated from the interpolation filter every predetermined clock period. It includes more.

1 is a block diagram of a data interpolation apparatus of a digital television constructed in accordance with the present invention;

2 is an operation timing diagram of the data interpolation apparatus of FIG. 1.

<Description of the symbols for the main parts of the drawings>

10: memory block 12, 14, 16, 18: data memory

30: data latch portion 32, 34, 36, 38: latch

40: interpolation filter 50: data distribution unit

70: data collision prevention unit 100: control unit

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 shows a block diagram of a video data interpolation apparatus for digital television according to the present invention. The data interpolation apparatus of the present invention is a device for performing a 1: 2 interpolation process, and includes a memory block 10 composed of n data memories 12, 14, 16, and 18 and a latch 32, 34, 36, and 38. The data latch unit 30, the interpolation filter 40, the data distribution unit 50, the data collision prevention unit 70, and the control unit 100 are included.

N, e.g., four data memories 12, 14, 16, 18 in the memory block 10 respectively store n digital image data provided in parallel from an unillustrated data rearrangement means. In addition, the memory block 10 interpolates image data sequentially from each of the data memories 12, 14, 16, and 18 at every interlocking clock period of the system clock CLK of FIG. 2A under the control of the controller 100 to be described below. Output to the filter 40 side.

The latches 32, 34, 36, and 38 of the data latch unit 30 are image data transferred from the corresponding data memories 12, 14, 16, and 18 through the memory buses 22, 24, 26, and 28, respectively. Temporarily save the function.

The interpolation filter 40 outputs one image data interpolated from the n image data provided from the latches 32, 34, 36, and 38. The interpolation filter 40 outputs the previously generated interpolation data to the data distribution unit 50 via the data collision prevention unit 70 while generating new interpolation data.

The data distributor 50 controls the interpolation data output from the interpolation filter 40 during the period in which the memory buses 22, 24, 26, and 28 are not occupied at every cycle of the system clock under the control of the controller 100. By selectively loading on the memory buses 22, 24, 26 and 28, the interpolated image data is stored in the data memories 12, 14, 16 and 18 again. The data distributor 50 includes n three-state buffers 62, 64, 66, 68.

The n three-state buffers 62, 64, 66, 68 are connected to n memories 12, 14, 16, 18 via buses 22, 24, 26, 28, and control means 100. Enabled by a buffer enable signal provided by &lt; RTI ID = 0.0 &gt;, &lt; / RTI &gt;

The control unit 100 sequentially reads data from each of the memories 12, 14, 16, and 18 in the memory block 10 at every clock cycle, and the read data is stored in the memory bus 22, 24, 26, 28. The chip select signal CS, the address signal AD, and the read enable signal R are generated so as to be provided to the interpolation filter 40 through the interpolation filter, and the interpolation data output from the interpolation filter 40 is stored in every memory. The chip select signal CS, the address signal AD, and the write enable signal W / are sequentially generated to be stored in each of the memories 12, 14, 16, and 18 in the block 10.

On the other hand, when the interpolation data, which is the output of the interpolation filter for each empty clock that does not read data from the memory block 10, is to be stored in the memory block 10 again, data read from the memory block 10 every 2n clock periods. By using the same bus for the interpolation data of the interpolation filter 40 and the interpolation filter 40, data collisions between them occur. Therefore, the video data interpolation apparatus of the present invention reads from the n-th memory 18 and is provided to the interpolation filter 40 at the 2n-th clock period of the system clock CLK as described in detail below. And an output between the output of the interpolation filter 40 and the data distribution unit 50 to prevent a collision between the 2nth interpolation data from the interpolation filter 40 to be stored in the same storage area as the 2n data of the nth memory. The data collision prevention unit 70 further includes. The data collision prevention unit 70 includes a three-state buffer 72 and 76 connected in parallel to the output of the interpolation filter 40, and a delay unit connected between the interpolation filter 40 and the three-state buffer 76. 74), with an eight-counter counter 80.

The tri-state buffer 72 provides the output of the interpolation filter 40 directly to the data distributor 50, and the tri-state buffer 76 sends the output of the interpolation filter 40 by the retarder 74. The clock is delayed by one clock of the system clock CLK and provided to the data distributor 50. The octal counter 80 counts the system clock CLK shown in FIG. 2A and buffers the high level (or logic " 1 ") signal when counting the 2nth, e.g., 8th clock. Output as. At this time, the buffer enable signal of the octal counter 80 is directly provided to the control terminal of the 3-state buffer 76, while inverted via the inverter 78 and then 3-inverted as the inverted buffer enable signal. Is provided to the status buffer 72. Accordingly, the tri-state buffer 72 is enabled by the buffer enable signal provided through the inverter 74 every clock to output the output of the interpolation filter 40 to the data distributor 50. The state buffer 76 is enabled by the octal counter 80 every eighth clock to output the output generated by the interpolation filter 40 to the data distributor 50 at this moment.

The operation of the data interpolation apparatus of the present invention having the above-described configuration will be described in detail as follows with reference to the timing diagram of FIG. FIG. 2A shows a system clock CLK, FIG. 2B shows an address signal AD generated by the control unit 100 and provided to each of the memories 12, 14, 16, and 18, and FIG. 2C shows a memory. The data read from (12 to 18) and displayed on the buses 22, 24, 26, and 28 are respectively shown, and FIG. 2D shows the control unit 100 for each of the memories 12, 14, 16, and 18. FIG. The memory select signal CS is shown. Prior to the description of the present invention, n memories shown in FIG. 1 will be described assuming four.

First, the image data interpolation apparatus of the present invention uses data D0, D1 from each memory 12, 14, 16, 18 by an address signal A0 provided from the controller 100 at the beginning of the system clock CLK. , D2, D3 are loaded on buses 22, 24, 26, 28 and are temporarily stored in respective latches 32, 34, 36, 38. In addition, the interpolation filter 40 outputs interpolation data F0 processed using the previous four data to the data distribution unit 50 of the next stage, and newly applies data D0 from the latch 32. The new interpolation data F1 is generated using the remaining three previous data.

Then, the address signal A0 provided to the first memory 12 is maintained for the first clock period of the system clock CLK in which the memory bus 22 is not occupied. At this time, the tri-state buffer 62 of the data distribution unit 50 is enabled by the control unit 100 so that the previous interpolation data F0 is loaded on the data bus 22 and the interpolation on the bus 22. The data F0 may be stored in the storage area in which the data D0 in the first memory 12 is stored by the address signal A0. On the other hand, the interpolation filter 40 provides the previous interpolation data F1 to the data collision prevention unit 70, the two data D0 and D1 provided from the latches 32 and 34, and the other two previous ones. The operation of generating new interpolation data F2 using the data is performed.

Then, during the second clock period of the system clock CLK, the controller 100 provides address signals A2 and A0 to the first and second memories 12 and 14, respectively. Therefore, the data D4 output from the first memory 12 is stored in the latch 32, and the interpolation filter 40 includes three data D0, D1, and D2 provided from the latches 32, 34, and 36. ) And new interpolation data F2 are generated using the other previous data. At the same time, the previous interpolation data F1 output from the interpolation filter 40 in the previous clock period is transferred to the data distribution unit 50 through the 3-state buffer 72 in the enabled state in the data collision prevention unit 72. ) Is then loaded onto the memory bus 24 via a three-state buffer 64 in the data distribution section 50 enabled by the control unit 100 and the second memory 14 by the address signal A0. )

Then, during the third clock period of the system clock CLK, the controller 100 provides the address signal A0 to the third memory 16. At this time, the interpolation data F2 from the interpolation filter 40 is provided to the data distribution unit 50 through the three-state buffer 72 of the data collision prevention unit 70, and is enabled by the control unit 100. It is loaded onto the memory bus 26 via a three-state buffer 66 in the data distribution section 50 and then stored in the third memory 16. In addition, the interpolation filter 40 receives data D0, D1, D2, and D3 from four latches 32, 34, 36, and 38 to generate new interpolation data F3.

The above-described process is repeated for the fourth to eighth clock periods of the system clock CLK, and data D5, D6, and D7 are interpolated from each memory 12, 14, 16, and 18 every two clock periods. The interpolation data F3, F4, F5, and F6 outputted from the interpolation filter 40 while being provided to 40 are sequentially stored in the respective memories 12, 14, 16, and 18 every clock.

However, when the data D7 is output from the fourth memory 18 by the address signal A2 generated in the control unit 100 in the eighth clock period of the system clock CLK, the interpolation filter 40 outputs the data D7. When the interpolated data F7 is stored in the same storage area in which the data D7 of the fourth memory 18 is stored, a collision phenomenon between these two data D7 and F7 occurs. At this time, the octal counter 80 of the data collision prevention unit 70 counts the eighth clock of the system clock CLK and outputs a high level buffer enable signal. The buffer enable signal is the inverter 78. Inverting through makes the three-state buffer 72 disabled, while the three-state buffer 76 is enabled.

Therefore, the interpolation data F7 output from the interpolation filter 40 in the eighth clock period of the system clock is delayed by one clock through the delay unit 74 (see FIG. 2C), and then in the ninth clock period, the control unit ( The address signal A2 generated by the control unit 100 after being loaded onto the memory bus 28 through the three-state buffer 68 in the data distribution unit 50 enabled by the buffer enable signal provided by 100. ) May be stored in the fourth memory 18. In addition, during the ninth clock period, the control unit 100 generates the address signal A1 to the first memory 12 by repeating the above-described whole process, so that the output F8 of the interpolation filter 40 becomes the first memory ( 12). Accordingly, by the above-described operation, the data D7 to be interpolated at the 2nd th (i.e., the eighth) in the fourth memory 18 and the interpolation data output at the 2n th (ie, the eighth) from the interpolation filter 40 ( The collision between F7) can be prevented.

The above-described process is repeated every 8 clock cycles, thereby providing the interpolation filter 40 with data to be interpolated from each memory 12, 14, 16, and 18 every two clock cycles, and at the same time, the interpolation filter 40 every clock. It is possible to sequentially store interpolation data output from the respective memories 12, 14, 16 and 18. In this manner, the image data and interpolation data stored in the data memories 12 and 16 in the memory block 10 are displayed on the monitor of the digital television through a video signal processing unit (not shown).

Therefore, in a 1: 2 image data interpolation apparatus that reads data to be interpolated during not every clock period, but generates double interpolation data using the read data, the interpolation filter is used with an empty time during the assault cycle. As a result, interpolation data processed by the interpolation filter can be stored in a memory while data interpolation is performed, thereby eliminating the need for a separate filter memory for storing interpolation data. In addition, since it is possible to utilize the system bus resources that are wasted every battling cycle, there is an advantage that the efficient use of system resources.

Claims (3)

In a 1: 2 interpolation apparatus of digital video data in digital television, An interpolation filter for outputting one image data interpolated therefrom using n pieces of image data input every clock period of the system clock CLK; N memories each storing n video data in parallel; An address signal is generated so that interpolated image data output from the interpolation filter is sequentially stored in the n memories every clock period of a system clock CLK, and n / 2 data are stored in the n memories every two clock cycles. Control means for generating an address signal to be provided to the interpolation filter from the second to the interpolation filter; And distribution means for distributing interpolated data output from the interpolation filter sequentially into the n memories at every clock period in synchronization with the address signal of the control means. The method of claim 1, wherein the data distribution means is: a clock counter for generating a count signal every n clock periods; A shift register for shifting the count signal of the clock counter every clock period and outputting the shifted value as an enable signal; And n tri-state buffers connected to the n memories and enabled by the enable signal to sequentially output the output of the interpolation filter to the n memories. Device. The apparatus of claim 2, wherein the interpolation device is: A data collision prevention means connected between the interpolation filter and the data divider to prevent a collision between 2nth data output from the memory to the interpolation filter and 2nth interpolation data output from the interpolation filter; , The data collision prevention means is: A first three-state buffer providing the output of the interpolation filter directly to the data divider; A delayer for delaying the 2nth interpolation data by one clock; A second three-state buffer providing the output of the delay to the data distributor; An inverter coupled to a control terminal of the first three-state buffer; By counting a system clock (CLK) and outputting a buffer enable signal to the first three-state buffer and the inverter when the second n-th clock is counted, the first three-state buffer is enabled. And a counter for disabling said second three-state buffer.