KR100390466B1 - multi chip module semiconductor package - Google Patents
multi chip module semiconductor package Download PDFInfo
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- KR100390466B1 KR100390466B1 KR10-1999-0067454A KR19990067454A KR100390466B1 KR 100390466 B1 KR100390466 B1 KR 100390466B1 KR 19990067454 A KR19990067454 A KR 19990067454A KR 100390466 B1 KR100390466 B1 KR 100390466B1
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- bonding pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/074—Stacked arrangements of non-apertured devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Wire Bonding (AREA)
Abstract
본 발명은 멀티칩 모듈 반도체패키지의 구조 개선을 통해, 상부에 적층되는 반도체칩과 회로기판과의 전기적 연결이 용이하게 이루어질 수 있도록 하는 한편, 멀티칩 모듈 패키지 제조시의 와이어 본딩 신뢰성을 높일 수 있도록 한 것이다.The present invention allows for easy electrical connection between a semiconductor chip and a circuit board stacked on top of the structure of a multi-chip module semiconductor package, and to increase wire bonding reliability in manufacturing a multi-chip module package. It is.
이를 위해, 본 발명은 베이스를 이루는 회로기판(1)과, 상기 회로기판 상부에 직접 부착되는 제1칩(2)과, 상기 제1칩(2)의 본딩패드면을 벗어난 일측에 부착되는 제2칩(3)과, 상기 제1칩(2) 또는 제2칩(3)의 상면에 부착되며 내부에 회로패턴이 형성되어 상기 제2칩(3)의 본딩패드와 회로기판의 접속단자를 전기적으로 연결시킴에 있어 가교역할을 하는 브릿지 부재(7)(bridge member)와, 상기 제2칩과 브릿지 부재 사이 및 상기 브릿지 부재와 회로기판을 전기적으로 연결하는 한편 제1칩과 회로기판을 전기적으로 연결하는 전도성 연결부재와, 상기 전도성 연결부재와 브릿지 부재, 그리고 제1칩 및 제2칩이 보호되도록 봉지하는 몰드바디(5)가 구비됨을 특징으로 하는 멀티칩 모듈 반도체패키지가 제공된다.To this end, the present invention provides a circuit board 1 forming a base, a first chip 2 directly attached to the upper portion of the circuit board, and a first side attached to one side of the first pad 2 outside the bonding pad surface. It is attached to the second chip 3 and the upper surface of the first chip 2 or the second chip 3 and a circuit pattern is formed therein so that the connection pads of the bonding pads of the second chip 3 and the circuit board are connected. A bridge member 7 which serves as a bridge in electrical connection, between the second chip and the bridge member, and electrically connects the bridge member and the circuit board, while electrically connecting the first chip and the circuit board. There is provided a multi-chip module semiconductor package, characterized in that the conductive connection member for connecting to, the mold body (5) for sealing the conductive connection member and the bridge member, and the first chip and the second chip is provided.
Description
본 발명은 멀티칩 모듈 반도체패키지에 관한 것으로서, 더욱 상세하게는 멀티칩 모듈 반도체패키지의 구조 개선을 통해 전기적 연결이 쉽게 수행될 수 있도록 하는 한편, 멀티칩 모듈 패키지의 신뢰성을 향상시킬 수 있도록 한 것이다.The present invention relates to a multi-chip module semiconductor package, and more particularly, to improve the reliability of the multi-chip module package while enabling electrical connection to be easily performed by improving the structure of the multi-chip module semiconductor package. .
일반적으로, 멀티칩 모듈( Multi-chip Moudle: 이하, "엠시엠"이라한다) 반도체패키지는 하나의 패키지내에 2개 이상의 반도체칩을 적층하여 내장하도록 한 것이다.In general, a multi-chip module (hereinafter, referred to as "MSC") semiconductor package is to stack two or more semiconductor chips in one package.
도 1 및 도 2는 종래의 멀티칩 모듈 패키지를 나타낸 것으로서, 베이스를 이루는 회로기판(1)과, 상기 회로기판(1) 상부에 직접 부착되는 제1칩(2)과, 상기 제1칩(2)의 본딩패드면을 벗어난 일측에 부착되며 상기 제1칩(2)보다 작은 사이즈의 제2칩(3)과, 상기 제1칩(2)의 본딩패드와 회로기판(1)의 해당 접속단자를 각각 전기적으로 연결함과 더불어 상기 제2칩(3)의 본딩패드와 회로기판(1)의 해당 접속단자를 각각 전기적으로 연결하는 골드와이어(4a)(4b)와, 상기 제1칩(2)과 제2칩(3) 및 골드와이어(4a)(4b)를 외부로부터 보호되도록 봉지하는 몰드바디(5)로 이루어지게 된다.1 and 2 illustrate a conventional multichip module package, wherein a base circuit board 1, a first chip 2 directly attached to an upper portion of the circuit board 1, and the first chip ( 2) a second chip 3 having a smaller size than the first chip 2, a bonding pad of the first chip 2, and a corresponding connection of the circuit board 1 Gold wires 4a and 4b that electrically connect the terminals, and electrically connect the bonding pads of the second chip 3 and the corresponding connection terminals of the circuit board 1, respectively, and the first chip. 2) and the mold body 5 for encapsulating the second chip 3 and the gold wires 4a and 4b to be protected from the outside.
그러나, 이와 같은 종래의 멀티칩 모듈 패키지는 도 1 및 도 2에 나타낸 바와 같이, 제1칩(2)의 본딩패드와 회로기판(1)의 접속단자와는 거리가 그다지 멀지않아 와이어(4b)로 본딩하는데 별문제가 없지만, 제2칩(3)의 본딩패드와 회로기판(1)의 접속단자를 와이어(4a)로 본딩하는데 많은 문제점이 있었다.However, such a conventional multi-chip module package, as shown in Figs. 1 and 2, the distance between the bonding pad of the first chip 2 and the connection terminal of the circuit board 1 is not far from the wire 4b. Although there is no problem in bonding with each other, there are many problems in bonding the connection terminal of the bonding pad of the second chip 3 and the circuit board 1 with the wire 4a.
즉, 제2칩(3)의 경우, 도 1 및 도 2에 있어서 도면상 우측의 본딩패드와 회로기판(1)의 접속단자 사이의 거리(D1)가 짧아, 와이어 본딩시 와이어(4a)와 제1칩(2)의 에지부분과의 간섭을 피하기 위해 와이어 루프가 급하게 휘어져야 하므로 인해, 와이어 본딩이 어려워지고 와이어(4a) 및 본딩 부위에 많은 응력이 걸리게 되므로 본딩 신뢰성이 저하되는 문제점이 있었다.That is, in the case of the second chip 3, the distance D 1 between the bonding pad on the right side of the drawing and the connection terminal of the circuit board 1 is short in FIGS. 1 and 2, so that the wire 4a at the time of wire bonding. Since the wire loop must be bent rapidly to avoid interference with the edge portion of the first chip 2, the wire bonding becomes difficult and a lot of stress is applied to the wire 4a and the bonding portion, which reduces the bonding reliability. there was.
또한, 상기한 바와는 달리, 도 1 및 도 2를 통해 알 수 있듯이, 제2칩(3) 좌측의 본딩패드와 회로기판(1)의 접속단자 사이의 거리(D2)는 상당히 먼 거리여서, 와이어 본딩 수행후에 와이어 처짐(sagging)이 발생하기 쉬우며 몰딩 수행시, 몰딩콤파운드에 의한 와이어 휩쓸림(sweeping) 현상이 발생할 우려가 커지게 된다.1 and 2, the distance D 2 between the bonding pad on the left side of the second chip 3 and the connection terminal of the circuit board 1 is considerably distant. After wire bonding, wire sagging is likely to occur, and a wire sweeping phenomenon caused by the molding compound increases when molding is performed.
뿐만 아니라, 와이어(4a)(4b)간의 간격이 좁아 전기적 단락(short-circuit)이 발생할 우려가 있는 등 많은 문제점 있었다.In addition, the gap between the wires 4a and 4b is narrow, which may cause electrical short-circuit.
본 발명은 상기한 제반 문제점을 해결하기 위한 것으로서, 멀티칩 모듈 반도체패키지의 구조 개선을 통해, 상부에 적층되는 반도체칩과 회로기판과의 전기적 연결이 용이하게 이루어질 수 있도록 한 멀티칩 모듈 반도체패키지를 제공하는데 그 목적이 있다.The present invention is to solve the above problems, the multi-chip module semiconductor package to facilitate the electrical connection between the semiconductor chip and the circuit board stacked on the top by improving the structure of the multi-chip module semiconductor package The purpose is to provide.
도 1은 종래의 멀티칩 모듈 반도체패키지를 종단면도1 is a vertical cross-sectional view of a conventional multi-chip module semiconductor package
도 2는 도 1의 몰딩전 상태를 나타낸 사시도2 is a perspective view showing a state before molding of FIG.
도 3은 본 발명의 제1실시예에 따른 멀티칩 모듈 반도체패키지를 나타낸 종단면도3 is a longitudinal sectional view showing a multichip module semiconductor package according to a first embodiment of the present invention;
도 4는 도 3의 몰딩전 상태를 나타낸 사시도4 is a perspective view showing a state before molding of FIG.
도 5는 본 발명의 제2실시예에 따른 멀티칩 모듈 반도체패키지를 나타낸 종단면도5 is a longitudinal sectional view showing a multichip module semiconductor package according to a second embodiment of the present invention;
도 6은 도 5의 몰딩전 상태를 나타낸 것으로서, 제2칩과 회로기판 간의 와이어링 경로가 변하는 과정을 보여주는 사시도FIG. 6 is a view illustrating a state before molding of FIG. 5 and illustrating a process of changing a wiring path between a second chip and a circuit board.
도 7는 본 발명의 제3실시예에 따른 멀티칩 모듈 반도체패키지를 나타낸 종단면도7 is a longitudinal sectional view showing a multichip module semiconductor package according to a third embodiment of the present invention;
도 8은 도 7의 몰딩전 상태를 나타낸 사시도8 is a perspective view showing a state before molding of FIG.
도 9는 본 발명의 제4실시예에 따른 멀티칩 모듈 반도체패키지를 나타낸 종단면도9 is a longitudinal sectional view showing a multichip module semiconductor package according to a fourth embodiment of the present invention;
도 10은 도 9의 몰딩전 상태를 나타낸 사시도10 is a perspective view showing a state before molding of FIG.
도 11은 본 발명의 제5실시예에 따른 멀티칩 모듈 반도체패키지를 나타낸 종단면도11 is a longitudinal sectional view showing a multichip module semiconductor package according to a fifth embodiment of the present invention;
도 12는 도 11의 몰딩전 상태를 나타낸 사시도12 is a perspective view showing a state before molding of FIG.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1:회로기판 2:제1칩1: Circuit board 2: First chip
3:제2칩 4a,4b,4c,4d,4f,4g:와이어3: second chip 4a, 4b, 4c, 4d, 4f, 4g: wire
5:몰드바디 6:솔더볼5: Molded body 6: Solder ball
7:브릿지 부재 700:접착제층7: bridge member 700: adhesive layer
701:리드 트레이스 702:절연피막701: lead trace 702: insulating film
골드와이어:핑거부 8:회로패턴Gold Wire: Finger 8: Circuit Pattern
9:범프9: bump
상기한 목적을 달성하기 위해, 본 발명은 베이스를 이루는 회로기판과, 상기 회로기판 상부에 직접 부착되는 제1칩과, 상기 제1칩의 본딩패드면 상의 본딩패드를 벗어난 영역 일측에 부착되는 제2칩과, 상기 제1칩 또는 제2칩의 상면에 부착되며 회로패턴이 형성된 필름으로서 상기 제2칩의 본딩패드와 회로기판의 접속단자를 전기적으로 연결시킴에 있어 가교(架橋)역할을 하는 브릿지 부재(bridge member)와, 상기 제2칩과 브릿지 부재 사이를 전기적으로 연결함과 더불어 상기 브릿지 부재와 회로기판 사이를 전기적으로 연결하는 한편 제1칩과 회로기판을 전기적으로 연결하는 전도성 연결부재와, 상기 전도성 연결부재와 브릿지 부재 그리고 제1칩 및 제2칩이 보호되도록 봉지하는 몰드바디가 구비됨을 특징으로 하는 멀티칩 모듈 반도체패키지가 제공된다.In order to achieve the above object, the present invention provides a circuit board forming a base, a first chip directly attached to the upper portion of the circuit board, and a first portion attached to one side of an area outside the bonding pad on the bonding pad surface of the first chip. A film formed on a second chip and an upper surface of the first chip or the second chip and having a circuit pattern formed thereon, which serves as a bridge in electrically connecting the bonding pad of the second chip and the connection terminal of the circuit board. Conductive connecting member for electrically connecting the bridge member and the second chip and the bridge member, and electrically connecting the bridge member and the circuit board, while electrically connecting the first chip and the circuit board. And a mold body for encapsulating the conductive connecting member, the bridge member, and the first chip and the second chip, the semiconductor package being provided. .
이하, 본 발명의 실시예들을 첨부도면 도 3 내지 도 10을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 10.
도 3은 본 발명의 제1실시예에 따른 멀티칩 모듈 반도체패키지를 나타낸 종단면도이고, 도 4는 도 3의 몰딩전의 상태를 나타낸 사시도로서, 본 발명의 제1실시예에 따른 멀티칩 모듈 패키지는 베이스를 이루는 회로기판(1)과, 상기 회로기판(1) 상부에 직접 부착되는 제1칩(2)과, 상기 제1칩(2)의 본딩패드 형성면상의 상기 본딩패드를 벗어난 영역 일측에 부착되며 상기 제1칩(2)보다 작은 사이즈의 제2칩(3)과, 상기 제1칩(2)의 본딩패드를 벗어난 타측에 부착되며 회로패턴(8)이 형성되어 상기 제2칩(3)의 본딩패드중 소정의 본딩패드와 회로기판(1)의 접속단자을 전기적으로 연결시킴에 있어 가교(架橋)역할을 하는 브릿지 부재(7)(bridge member)와, 상기 제2칩(3)과 브릿지 부재(7) 사이 및 상기 브릿지 부재(7)와 회로기판(1) 사이를 전기적으로 연결하는 한편, 제1칩(2)과 회로기판(1) 사이를 전기적으로 연결하는 전도성 연결부재와, 상기 전도성 연결부재와 브릿지 부재(7), 그리고 제1칩(2) 및 제2칩(3)이 보호되도록 봉지하는 몰드바디(5)가 구비된다.3 is a longitudinal cross-sectional view illustrating a multi-chip module semiconductor package according to a first embodiment of the present invention, and FIG. 4 is a perspective view illustrating a state before molding of FIG. 3, and according to the first embodiment of the present invention. The circuit board 1 forming a base, the first chip 2 directly attached to the upper portion of the circuit board 1, and one side of the region outside the bonding pad on the bonding pad forming surface of the first chip 2 A second chip 3 having a smaller size than the first chip 2 and attached to the other side of the first chip 2 beyond the bonding pad of the first chip 2 and having a circuit pattern 8 formed thereon. Of the bonding pads (3), the bridge member (7) (bridge member) which serves as a bridge in electrically connecting the predetermined bonding pad and the connection terminal of the circuit board (1), and the second chip (3) ) Between the bridge member 7 and between the bridge member 7 and the circuit board 1, while the first chip 2 A conductive connecting member electrically connecting between the circuit board 1, and a molded body 5 encapsulating the conductive connecting member and the bridge member 7 and the first chip 2 and the second chip 3 to be protected. ) Is provided.
이때, 상기 회로기판(1) 하부에는 마더보드(도시는 생략함)에의 실장을 위한 솔더볼(6)등의 외부접속단자가 구비된다.At this time, the lower portion of the circuit board 1 is provided with an external connection terminal such as a solder ball 6 for mounting on a motherboard (not shown).
한편, 상기 브릿지 부재(7)로서는 회로패턴(8)이 형성된 회로기판 또는 회로필름이 사용된다.On the other hand, as the bridge member 7, a circuit board or a circuit film on which a circuit pattern 8 is formed is used.
이와 같이 구성된 본 발명의 제1실시예에 따른 멀티칩 모듈 패키지의 제조 과정 및 작용은 다음과 같다.The manufacturing process and operation of the multichip module package according to the first embodiment of the present invention configured as described above are as follows.
먼저, 회로기판(1) 상에 제1칩(2)이 부착되고, 이어 상기 제1칩(2) 상부 일측 및 타측에 각각 제2칩(3) 및 브릿지 부재(7)가 부착된 상태에서 와이어 본딩을수행하게 되는데, 상기 제1칩(2)의 본딩패드는 전도성 연결부재인 골드와이어(4b)에 의해 회로기판(1)상에 형성된 소정의 접속단자에 각각 전기적으로 연결되고, 상기 제1칩(2) 상부면상에 부착된 제2칩(3)의 본딩패드는 브릿지 부재(7)를 매개로 하여 골드와이어(4a)(4c)에 의해 회로기판(1)상에 형성된 소정의 접속단자에 각각 전기적으로 연결된다.First, the first chip 2 is attached on the circuit board 1, and then the second chip 3 and the bridge member 7 are attached to one side and the other side of the first chip 2, respectively. Wire bonding is performed. The bonding pads of the first chip 2 are electrically connected to predetermined connection terminals formed on the circuit board 1 by gold wires 4b, which are conductive connecting members, respectively. The bonding pads of the second chip 3 attached on the upper surface of the first chip 2 are formed on the circuit board 1 by the gold wires 4a and 4c via the bridge member 7. Each terminal is electrically connected.
즉, 도 2 및 도 3을 통해 알 수 있듯이, 본 발명의 제1실시예에 따르면, 제2칩(3)의 본딩패드중 도면상 좌측에 형성된 본딩패드는 우선 골드와이어(4a)에 의해 제1칩(2) 상면에 부착된 브릿지 부재(7)의 일측 접속단자에 1차적으로 접속된다.2 and 3, according to the first embodiment of the present invention, the bonding pads formed on the left side of the bonding pads of the second chip 3 are first formed by the gold wires 4a. It is primarily connected to one connection terminal of the bridge member 7 attached to the upper surface of one chip 2.
한편, 상기 브릿지 부재(7)의 일측 접속단자는 내부에 형성된 회로패턴(8)에 의해 상기 일측 접속단자로부터 이격된 위치의 타측 접속단자와 전기적으로 연결된 상태이다.Meanwhile, one connection terminal of the bridge member 7 is electrically connected to the other connection terminal at a position spaced apart from the one connection terminal by a circuit pattern 8 formed therein.
따라서, 제1칩(2)의 도면상 우측에 위치한 본딩패드와 브릿지 부재(7)의 일측 접속단자 사이를 골드와이어(4a)로써 와이어 본딩하여 1차적으로 접속시킨 후에는, 상기 브릿지 부재(7)의 타측 접속단자와 회로기판(1)의 접속단자 사이를 골드와이어(4c)로 연결하여 2차적으로 접속시키게 되며, 이로 인해 제2칩(2)의 도면상 우측에 위치한 본딩패드는 회로기판(1)에 전기적으로 연결된다.Therefore, after the wire bonding between the bonding pad located on the right side of the drawing of the first chip 2 and one connection terminal of the bridge member 7 by primary connection with gold wires 4a, the bridge member 7 The second connection terminal of the circuit board 1 and the connection terminal of the circuit board 1 are connected to each other by connecting the gold wire 4c so that the bonding pad located on the right side of the drawing of the second chip 2 is connected to the circuit board. It is electrically connected to (1).
즉, 본 발명의 제1실시예에 따르면, 제2칩(3)의 본딩패드와 회로기판(1)의 접속단자 사이의 거리가 멀더라도 브릿지 부재(7)를 매개로하여 와이어의 처짐없이 전기적으로 연결가능하다.That is, according to the first embodiment of the present invention, even if the distance between the bonding pad of the second chip 3 and the connection terminal of the circuit board 1 is long, the electrical connection is performed without the sag of the wire through the bridge member 7. Can be connected.
한편, 도 5는 본 발명의 제2실시예에 따른 멀티칩 모듈 반도체패키지를 나타낸 종단면도로서, 몰딩 공정 후에 반도체패키지를 도 6의 Ⅰ-Ⅰ선을 따라 절개하여 바라본 상태도와 동일하다.5 is a longitudinal cross-sectional view illustrating a multi-chip module semiconductor package according to a second embodiment of the present invention, which is the same as the state of the semiconductor package cut along the line I-I of FIG. 6 after the molding process.
아울러, 도 6은 도 5의 몰딩전 상태를 나타낸 사시도로서, 본 발명의 제2실시예에 따른 멀티칩 모듈 반도체패키지는 상기한 제1실시예와 다른 구성은 동일하나, 브릿지 부재(7)의 형상을 도면에 나타낸 바와 같은 "ㄴ"자로 한다던지, "ㄷ"자(미도시) 또는 그 밖의 형태로 변형하므로써 제2칩(3)의 본딩패드와 브릿지 부재(7)의 접속단자와의 연결후, 상기 브릿지 부재(7)의 회로패턴(8)에 의해 제2칩(3)의 본딩패드와 회로기판(1)의 접속단자와의 와이어링(wiring) 경로를 변화시킬 수 있도록 구성된다.6 is a perspective view showing a state before molding of FIG. 5, wherein the multi-chip module semiconductor package according to the second embodiment of the present invention has the same configuration as that of the first embodiment, but is different from that of the bridge member 7. Connection of the bonding pad of the second chip 3 and the connection terminal of the bridge member 7 by changing the shape to "b" as shown in the figure, or to "c" (not shown) or other shapes. After that, the wiring pattern between the bonding pad of the second chip 3 and the connection terminal of the circuit board 1 can be changed by the circuit pattern 8 of the bridge member 7.
즉, 제2칩(3)의 본딩패드는 골드와이어(4a)에 의해 1차적으로 브릿지 부재(7)의 접속단자중 최단경로를 이루는 접속단자에 연결되고, 상기 접속단자는 회로패턴(8)에 의해 브릿지 부재(7)의 플랜지부에 위치한 접속단자에 연결되어 있으므로, 상기 플랜지부에 위치한 접속단자와 회로기판(1)의 접속단자를 골드와이어(4c)를 이용하여 연결시킴에 따라, 와이어링 경로가 변경된 상태로 제2칩(3)과 회로기판(1) 간의 전기적 접속이 이루어지게 된다.That is, the bonding pad of the second chip 3 is connected to the connection terminal which forms the shortest path among the connection terminals of the bridge member 7 by the gold wire 4a, and the connection terminal is connected to the circuit pattern 8. Since it is connected to the connecting terminal located in the flange portion of the bridge member 7 by connecting the connecting terminal of the flange portion and the connecting terminal of the circuit board 1 by using the gold wire (4c), the wire Electrical connection between the second chip 3 and the circuit board 1 is made with the ring path changed.
이와 같이 구성된 본 발명의 제2실시예에 따르면, 브릿지 부재(7)의 형태 및 그 내부에 형성되는 회로패턴(8)의 변경을 통해 제2칩(3)과 회로기판(1)과의 와이어링을 거리에 관계없이 자유롭고 다양하게 변화시킬 수 있게 되며, 와이어 상호 간격을 멀어지게 할 수 있음로 인해 단락 발생을 방지할 수 있게 된다.According to the second embodiment of the present invention configured as described above, the wire between the second chip 3 and the circuit board 1 is changed by changing the shape of the bridge member 7 and the circuit pattern 8 formed therein. The ring can be freely and varied regardless of the distance, and the distance between the wires can be increased, thereby preventing short circuits.
이하, 본 발명의 제3실시예를 설명하면 다음과 같다.Hereinafter, a third embodiment of the present invention will be described.
도 7은 본 발명의 제3실시예에 따른 멀티칩 모듈 반도체패키지를 나타낸 종단면도이고, 도 8은 도 7의 몰딩전 상태를 나타낸 사시도로서, 본 발명의 제3실시예에 따른 멀티칩 모듈 반도체패키지는 베이스를 이루는 회로기판(1)과, 상기 회로기판(1) 상부에 직접 부착되는 제1칩(2)과, 상기 제1칩(2) 상면의 본딩패드면을 벗어난 영역에 부착되며 상기 제1칩(2)보다 작은 사이즈의 제2칩(3)과, 상기 제2칩(3) 상면의 본딩패드를 벗어난 영역에 부착되며 회로패턴(8)이 형성되어 상기 제2칩(3)의 본딩패드중 소정의 패드와 회로기판(1)을 전기적으로 연결시킴에 있어 가교역할을 하는 브릿지 부재(7)(bridge member)와, 상기 제2칩(3)과 브릿지 부재(7)사이 및 상기 브릿지 부재(7)와 회로기판(1)을 전기적으로 연결하는 한편 제1칩(2)과 회로기판(1)을 전기적으로 연결하는 전도성 연결부재와, 상기 전도성 연결부재와 브릿지 부재(7) 그리고 제1칩(2) 및 제2칩(3)이 보호되도록 봉지하는 몰드바디(5)가 구비된다.7 is a longitudinal cross-sectional view illustrating a multi-chip module semiconductor package according to a third embodiment of the present invention, and FIG. 8 is a perspective view illustrating a state before molding of FIG. 7, and according to a third embodiment of the present invention. The package is attached to a circuit board 1 forming a base, a first chip 2 directly attached to an upper portion of the circuit board 1, and an area outside a bonding pad surface of the upper surface of the first chip 2. The second chip 3 having a smaller size than the first chip 2, and a circuit pattern 8 are formed on a region outside the bonding pad on the upper surface of the second chip 3, and a circuit pattern 8 is formed to form the second chip 3. A bridge member 7 (bridge member) which serves as a bridge in electrically connecting a predetermined pad and a circuit board 1 of the bonding pads, between the second chip 3 and the bridge member 7, and Conduction that electrically connects the bridge member 7 and the circuit board 1 while electrically connecting the first chip 2 and the circuit board 1. The connecting member and the conductive connecting member and the bridge member (7) and the first chip 2 and second chip molded body (5) such that the bag 3 is protected is provided.
이때, 상기 회로기판(1) 하부에는 마더보드(도시는 생략함)에의 실장을 위한 솔더볼(6)등의 외부접속단자가 구비되고, 상기 브릿지 부재(7)로서는 회로기판 또는 회로패턴(8)이 형성된 회로필름이 사용가능함은 전술한 실시예에서와 마찬가지이다.In this case, an external connection terminal such as a solder ball 6 for mounting on a motherboard (not shown) is provided below the circuit board 1, and the bridge member 7 includes a circuit board or a circuit pattern 8. This formed circuit film can be used as in the above-described embodiment.
이와 같이 구성된 본 발명의 제3실시예에 따르면, 제2칩(3)에 형성된 본딩패드와 상기 제2칩(3) 상면에 부착된 브릿지 부재(7)의 일측 접속단자를 1차적으로 와이어(4a)로 본딩하고 난후, 상기 일측 접속단자와 회로패턴(8)에 의해 연결된 브릿지 부재(7)의 타측 접속단자와 회로기판(1)의 접속단자를 2차적으로 와이어(4c)로 본딩하게 된다.According to the third embodiment of the present invention configured as described above, one side connection terminal of the bonding pad formed on the second chip 3 and the bridge member 7 attached to the upper surface of the second chip 3 is primarily wired ( After bonding to 4a), the second connection terminal of the bridge member 7 connected by the one connection terminal and the circuit pattern 8 and the connection terminal of the circuit board 1 are secondarily bonded by the wire 4c. .
상기의 제3실시예에서도 브릿지 부재(7) 형태 및 그 내부에 형성되는 회로패턴(8)의 변경을 통해 자유로운 와이어링 경로 변경 및 와이어 간의 간격을 넓혀 단락을 방지하는 것이 가능하게 됨은 물론이다.In the third embodiment described above, it is possible to prevent the short circuit by changing the free wiring path and widening the distance between the wires by changing the shape of the bridge member 7 and the circuit pattern 8 formed therein.
한편, 도 9는 본 발명의 제4실시예에 따른 멀티칩 모듈 반도체패키지를 나타낸 종단면도이고, 도 10은 도 9의 몰딩전 상태를 나타낸 사시도로서, 본 발명의 제4실시예에 따른 멀티칩 모듈 패키지는 베이스를 이루는 회로기판(1)과, 상기 회로기판(1) 상에 부착되는 제1칩(2)과, 상기 제1칩(2)의 본딩패드를 벗어난 영역에 부착되는 제2칩(3)과, 상기 제2칩(3)의 본딩패드에 리드 본딩되도록 제2칩(3) 상면에 부착되며 내부에 리드 트레이스(701)(lead trace)가 패터닝(paterning)되고 상부면 상에 상기 리드 트레이스(701)를 커버하는 절연피막(702)이 형성된 브릿지 부재(7)와, 상기 브릿지 부재(7)의 절연피막(702)에 형성된 윈도우(W)를 통해 노출된 리드 트레이스(701)와 회로기판(1)의 접속단자 사이를 각각 전기적으로 연결하는 한편 상기 제1칩(2)의 본딩패드와 회로기판(1)의 접속단자 사이를 각각 전기적으로 연결하는 전도성 연결부재인 골드와이어(4b)(4f)와, 상기 제1칩(2)과 제2칩(3)과 브릿지 부재(7) 그리고 전도성 연결부재가 보호되도록 봉지하는 몰드바디(5)가 구비되어 구성된다.9 is a longitudinal cross-sectional view illustrating a multi-chip module semiconductor package according to a fourth embodiment of the present invention, and FIG. 10 is a perspective view illustrating a state before molding of FIG. 9 and according to the fourth embodiment of the present invention. The module package includes a circuit board 1 forming a base, a first chip 2 attached to the circuit board 1, and a second chip attached to an area deviating from a bonding pad of the first chip 2. (3) and attached to an upper surface of the second chip 3 so as to lead-bond to the bonding pads of the second chip 3, and a lead trace 701 is patterned therein and formed on the upper surface. A bridge member 7 having an insulating film 702 covering the lead trace 701 and a lead trace 701 exposed through a window W formed in the insulating film 702 of the bridge member 7. And the connection terminals of the circuit board 1 and the connection terminals of the circuit board 1, respectively. Gold wires (4b) and (4f), which are conductive connecting members that electrically connect between the quick terminals, and the first chip (2), the second chip (3), the bridge member (7), and the conductive connecting member to be protected. A mold body 5 to be sealed is provided.
이 때, 상기 브릿지 부재(7)의 윈도우(W) 영역 내에는 와이어 본딩시 골드와이어(4f)와의 접합성을 향상시키기 위해 전도성이 우수한 Au 또는 Ag가 플레이팅 된다.In this case, Au or Ag having excellent conductivity is plated in the window W region of the bridge member 7 to improve bonding with the gold wire 4f during wire bonding.
그리고, 상기 리드 트레이스(701)는 전도성이 좋은 Cu 재질로 이루어지고, 상기 브릿지 부재(7)의 절연피막(702)은 폴리이미드 수지 계열의 재질로 이루어짐이 바람직하다.In addition, the lead trace 701 is made of a good conductive Cu material, the insulating film 702 of the bridge member 7 is preferably made of a polyimide resin-based material.
한편, 상기 브릿지 부재(7)의 저면에는 접착제층(700)이 구비되며, 상기 접착제층(700)은 제2칩(3)의 본딩패드와 접합되는 핑거부(703)를 제외한 영역에 구비된다.On the other hand, the bottom surface of the bridge member 7 is provided with an adhesive layer 700, the adhesive layer 700 is provided in the region excluding the finger portion 703 bonded to the bonding pad of the second chip (3). .
상기에서 핑거부(703)는 리드 트레이스(701)중 제2칩(3)의 본딩패드와 접합되는 부분을 의미한다.The finger portion 703 refers to a portion of the lead trace 701 that is bonded to the bonding pad of the second chip 3.
또한, 상기 회로기판(1) 하부에는 마더보드(도시는 생략함)에의 실장을 위한 솔더볼(6)등의 외부접속단자가 구비됨은 전술한 실시예에서와 마찬가지이다.In addition, the lower portion of the circuit board 1 is provided with an external connection terminal such as a solder ball 6 for mounting on a motherboard (not shown) is the same as in the above-described embodiment.
이와 같이 구성된 본 발명의 제4실시예에 따르면, 제2칩(3)과 회로기판(1)과의 전기적 연결을 위한 와이어 본딩이 제2칩(3)의 본딩패드와 회로기판(1)의 접속단자가 아닌 브릿지 부재(7)의 오프닝된 윈도우(W) 영역과 회로기판(1)의 접속단자 사이에서 이루어지게 된다.According to the fourth embodiment of the present invention configured as described above, the wire bonding for the electrical connection between the second chip 3 and the circuit board 1 is performed by the bonding pads of the second chip 3 and the circuit board 1. It is made between the opened window W area of the bridge member 7 and the connection terminal of the circuit board 1, not the connection terminal.
이는, 제2칩(3)의 본딩패드가 브릿지 부재(7)의 리드 트레이스(701)와 리드 본딩되어 전기적으로 연결되고, 브릿지 부재(7) 상에는 와이어 본딩을 위해 리드 트레이스(701)가 노출되도록 오프닝된 윈도우 영역이 형성되어 있기 때문에 가능하다.This allows the bonding pads of the second chip 3 to be lead-bonded and electrically connected to the lead traces 701 of the bridge member 7, and the lead traces 701 are exposed on the bridge member 7 for wire bonding. This is possible because the opened window area is formed.
이에 따라, 본 발명의 제4실시예에 따른 멀티칩 모듈 패키지에서는 와이어 루프가 급격하게 휘지 않고 완만한 곡선을 그리게 되므로 인해 와이어(4f) 및 본딩부위에 작용하는 응력이 줄어들게 되어 본딩 신뢰성이 향상된다.Accordingly, in the multi-chip module package according to the fourth embodiment of the present invention, since the wire loop does not bend rapidly but draws a gentle curve, the stress applied to the wire 4f and the bonding portion is reduced, thereby improving the bonding reliability. .
또한, 상기 브릿지 부재(7)의 윈도우(W) 영역 내에는 Au 또는 Ag가 플레이팅되어 있으므로 골드와이어(4f)와의 접합력이 강화된다.In addition, since Au or Ag is plated in the window W region of the bridge member 7, the bonding force with the gold wire 4f is enhanced.
그리고, 본 발명의 제4실시예의 멀티칩 모듈 패키지는 제2칩(3)의 상면에 형성되는 본딩패드를 도 10에 나타낸 바와 같이 제2칩(3)의 4면 가장자리를 따라 모두 형성하여 QFP(Quad Flat Package)에서와 동일한 형태로 와이어 본딩할 수 있으므로 인해 신호 전달을 위한 단자수를 전술한 실시예에 따른 패키지에 비해 증가시킬 수 있게 된다.In the multi-chip module package according to the fourth embodiment of the present invention, the bonding pads formed on the upper surface of the second chip 3 are all formed along the four surface edges of the second chip 3 as shown in FIG. Since wire bonding may be performed in the same form as in a quad flat package, the number of terminals for signal transmission may be increased as compared with the package according to the above-described embodiment.
또한, 본 발명의 제4실시예의 멀티칩 모듈 패키지는, 와이어 본딩시 전도성 연결부재인 와이어 상호간의 간격을 넓힐 수 있으므로 인해, 와이어(4b)(4f)의 단락을 방지할 수 있게 된다.In addition, the multichip module package according to the fourth embodiment of the present invention can widen the space between the wires, which are conductive connecting members, during wire bonding, thereby preventing short circuits of the wires 4b and 4f.
이하, 본 발명의 제5실시예에 대해 설명하면 다음과 같다.Hereinafter, the fifth embodiment of the present invention will be described.
도 11은 본 발명의 제5실시예에 따른 멀티칩 모듈 반도체패키지를 나타낸 종단면도이고, 도 12는 도 11의 몰딩전 상태를 나타낸 사시도로서, 제5실시예에 따른 멀티칩 모듈 반도체패키지는 베이스를 이루는 회로기판(1)과, 상기 회로기판(1) 상에 부착되는 제1칩(2)과, 상기 제1칩(2)의 본딩패드를 벗어난 영역에 부착되는 제2칩(3)과, 상기 제2칩(3)의 본딩패드 상부에 구비되는 범프(9)(bump)와, 저면에는 상기 범프(9)와 접합되도록 형성되는 콘택부가 구비되며 상면에는 상기 콘택부와 연결된 회로패턴(8)이 노출되는 윈도우(W) 영역이 구비된 브릿지 부재(7)와, 상기 제2칩(3) 상면에 부착된 브릿지 부재(7)의 윈도우 영역으로 노출되는 회로패턴(8)과 상기 회로기판(1)의 접속단자를 각각 전기적으로 연결하는 한편 제1칩(2)의 본딩패드와 회로기판(1)의 접속단자를 각각 전기적으로 연결하는 전도성 연결부재(4g)(4b)와, 상기 제1칩(2)과 제2칩(3) 및 브릿지 부재(7)와 전도성 연결부재가 보호되도록 봉지하는 몰드바디(5)가 구비되어 구성된다.11 is a longitudinal cross-sectional view illustrating a multi-chip module semiconductor package according to a fifth embodiment of the present invention, and FIG. 12 is a perspective view showing a state before molding of FIG. 11, and the multi-chip module semiconductor package according to the fifth embodiment is a base. A circuit board 1, a first chip 2 attached to the circuit board 1, a second chip 3 attached to a region outside the bonding pad of the first chip 2, and And a bump 9 provided on the bonding pad of the second chip 3 and a contact portion formed on the bottom thereof to be bonded to the bump 9, and a circuit pattern connected to the contact portion on the upper surface thereof. The bridge member 7 having the window W region to which the 8 is exposed, the circuit pattern 8 exposed to the window region of the bridge member 7 attached to the upper surface of the second chip 3, and the circuit The connection terminals of the substrate 1 are electrically connected to each other, while the bonding pads of the first chip 2 and the connection terminals of the circuit board 1 are respectively connected. Conductive connecting members 4g and 4b electrically connected to each other, and a mold body 5 encapsulating the first chip 2 and the second chip 3 and the bridge member 7 and the conductive connecting member to be protected. It is provided and configured.
이 때, 상기 브릿지 부재(7)의 윈도우(W) 영역 내에는 와이어 본딩시 골드와이어(4g)와의 접합성을 향상시키기 위해 전도성이 우수한 Au 또는 Ag가 플레이팅됨은 전술한 제4실시예에서와 마찬가지이다.At this time, Au or Ag having excellent conductivity is plated in the window W region of the bridge member 7 to improve bonding with the gold wire 4g during wire bonding as in the above-described fourth embodiment. to be.
또한, 상기 리드 트레이스(701)는 전도성이 좋은 Cu 재질로 이루어지고, 상기 브릿지 부재(7)의 양면에는 절연피막(702)이 형성되며, 상기 절연피막(702)은 폴리이미드 수지 계열의 재질로 이루어짐이 바람직하다.In addition, the lead trace 701 is made of a good conductive Cu material, an insulating film 702 is formed on both sides of the bridge member 7, the insulating film 702 is made of a polyimide resin-based material Is preferred.
한편, 상기에서 콘택부는 브릿지 부재(7)에 형성된 회로패턴(8)중 제2칩(3)의 본딩패드와 접합되도록 노출된 부분을 의미한다.In the above description, the contact portion refers to a portion of the circuit pattern 8 formed on the bridge member 7 exposed to be bonded to the bonding pad of the second chip 3.
그리고, 상기 회로기판(1) 하부에는 마더보드(도시는 생략함)에의 실장을 위한 솔더볼(6)등의 외부접속단자가 구비됨은 전술한 실시예에서와 마찬가지이다.The lower portion of the circuit board 1 is provided with an external connection terminal such as a solder ball 6 for mounting on a motherboard (not shown) as in the above-described embodiment.
이와 같이 구성된 본 발명의 제5실시예에 따르면, 제2칩(3)과 회로기판(1)과의 전기적 연결이 제2칩(3)의 본딩패드와 회로기판(1)의 접속단자 사이의 와이어 본딩이 아닌, 브릿지 부재(7)의 윈도우 오프닝 영역과 회로기판(1)의 접속단자 간의 와이어 본딩에 의해 이루어지게 된다.According to the fifth embodiment of the present invention configured as described above, the electrical connection between the second chip 3 and the circuit board 1 is connected between the bonding pad of the second chip 3 and the connection terminal of the circuit board 1. Instead of wire bonding, wire bonding between the window opening area of the bridge member 7 and the connection terminal of the circuit board 1 is achieved.
이는, 제2칩(3)의 본딩패드가 범프 본딩에 의해 브릿지 부재(7)의 콘택부에 전기적으로 연결되고, 브릿지 부재(7) 상에는 와이어 본딩을 위해 회로패턴(8)이노출되도록 오프닝된 윈도우(W) 영역이 형성되어 있기 때문에 가능하다.This means that the bonding pad of the second chip 3 is electrically connected to the contact portion of the bridge member 7 by bump bonding, and the circuit pattern 8 is opened to expose the circuit pattern 8 on the bridge member 7 for wire bonding. This is possible because the window W region is formed.
이에 따라, 본 발명의 제5실시예에 따른 멀티칩 모듈 패키지에서는, 제4실시예에서와 마찬가지로 와이어 루프가 급격하게 휘지 않고 완만한 곡선을 그리게 되므로 인해 와이어(4g) 및 본딩 부위에 작용하는 응력이 줄어들게 되어 본딩 신뢰성이 향상된다.Accordingly, in the multi-chip module package according to the fifth embodiment of the present invention, as in the fourth embodiment, since the wire loop does not suddenly bend and draws a gentle curve, the stress acting on the wire 4g and the bonding portion This reduces the bonding reliability.
또한, 상기 브릿지 부재(7)의 윈도우(W) 영역 내에는 Au 또는 Ag가 플레이팅되어 있으므로 와이어(4)와의 접합력이 강화된다.In addition, since Au or Ag is plated in the window W region of the bridge member 7, the bonding force with the wire 4 is enhanced.
한편, 본 발명의 제5실시예의 멀티칩 모듈 패키지 또한 제4실시예에서와 마찬가지로 제2칩(3)의 상면에 형성되는 본딩패드를 도 12에 나타낸 바와 같이 제2칩(3) 네면의 가장자리를 따라 모두 형성하여 QFP(Quad Flat Package)에서와 동일한 형태로 와이어 본딩할 수 있으므로 인해 신호 전달을 위한 단자수를 전술한 실시예에 비해 증가시킬 수 있게 되며, 와이어 본딩시 이웃하는 골드와이어간의 간격을 손쉽게 넓혀 와이어(4b)(4g)의 단락을 방지할 수 있게 된다.On the other hand, the multi-chip module package according to the fifth embodiment of the present invention also has a bonding pad formed on the upper surface of the second chip 3 as shown in FIG. Since all wires can be formed in the same form as in QF (Quad Flat Package), the number of terminals for signal transmission can be increased compared to the above-described embodiment, and the distance between adjacent gold wires during wire bonding can be increased. It can be easily widened to prevent the short circuit of the wire (4b) (4g).
이상에서와 같이, 본 발명은 멀티칩 모듈 반도체패키지의 구조 개선을 통해, 상부에 적층되는 반도체칩과 회로기판과의 전기적 연결이 용이하게 이루어질 수 있도록 한 것이다.As described above, the present invention is to facilitate the electrical connection between the semiconductor chip and the circuit board stacked on the upper side through the improvement of the structure of the multi-chip module semiconductor package.
뿐만 아니라, 와이어 본딩시 와이어간의 단락 및 처짐이 방지되고, 와이어링 경로 변경이 가능하며 와이어 및 본딩 부위의 응력이 저감되어 본딩 신뢰성이 향상되며, 결국 멀티칩 모듈 패키지의 기계적·전기적 신뢰성을 향상시킬 수 있게 된다.In addition, short-circuit and deflection between wires can be prevented, the wiring path can be changed, and the stress on the wire and the bonding part is reduced, thereby improving the bonding reliability, which in turn improves the mechanical and electrical reliability of the multichip module package. It becomes possible.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9214441B2 (en) | 2013-08-16 | 2015-12-15 | Samsung Electronics Co., Ltd. | Semiconductor package including stacked memory chips |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100426608B1 (en) * | 2001-11-20 | 2004-04-08 | 삼성전자주식회사 | Center pad type integrated circuit chip that means for jumpering is mounted on the active layer and manufacturing method thereof and multi chip package |
| KR100728977B1 (en) * | 2006-02-24 | 2007-06-15 | 주식회사 하이닉스반도체 | Stack package |
| KR100908753B1 (en) * | 2007-05-11 | 2009-07-22 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
| JP5453983B2 (en) * | 2009-07-28 | 2014-03-26 | セイコーエプソン株式会社 | Integrated circuit device and electronic apparatus |
Citations (5)
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|---|---|---|---|---|
| JPS61287133A (en) * | 1985-06-13 | 1986-12-17 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH04284663A (en) * | 1991-03-13 | 1992-10-09 | Toshiba Corp | Semiconductor device |
| JPH0513663A (en) * | 1991-07-09 | 1993-01-22 | Fujitsu Ltd | Semiconductor device and method for mounting semiconductor chip |
| JPH08340081A (en) * | 1995-06-14 | 1996-12-24 | Matsushita Electron Corp | Semiconductor device and its manufacture |
| JP2001007278A (en) * | 1999-06-18 | 2001-01-12 | Nec Corp | Semiconductor memory device |
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- 1999-12-30 KR KR10-1999-0067454A patent/KR100390466B1/en active IP Right Grant
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61287133A (en) * | 1985-06-13 | 1986-12-17 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH04284663A (en) * | 1991-03-13 | 1992-10-09 | Toshiba Corp | Semiconductor device |
| JPH0513663A (en) * | 1991-07-09 | 1993-01-22 | Fujitsu Ltd | Semiconductor device and method for mounting semiconductor chip |
| JPH08340081A (en) * | 1995-06-14 | 1996-12-24 | Matsushita Electron Corp | Semiconductor device and its manufacture |
| JP2001007278A (en) * | 1999-06-18 | 2001-01-12 | Nec Corp | Semiconductor memory device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9214441B2 (en) | 2013-08-16 | 2015-12-15 | Samsung Electronics Co., Ltd. | Semiconductor package including stacked memory chips |
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| KR20010059916A (en) | 2001-07-06 |
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