KR100390145B1 - Method for programming a nonvolatile semiconductor memory device - Google Patents

Abstract

A method of programming a nonvolatile semiconductor memory device disclosed herein is to block current flow of parasitic MOS transistors formed between a program inhibited memory cell and an adjacent memory cell to be programmed. In such a programming method, after transferring the data bits to be programmed to the bit lines, the bit line corresponding to the data bit representing the program is biased with a field inhibit voltage between the ground voltage and the power supply voltage. The field inhibit voltage is a minimum voltage for turning off a parasitic MOS transistor formed between adjacent cells on the same word line. By applying a field inhibit voltage to a bit line corresponding to a data bit representing a program, the threshold voltage of the parasitic MOS transistor is increased to be higher than the program voltage. As a result, a program disturb caused by the parasitic MOS transistor can be prevented.

Description

Program method of nonvolatile semiconductor memory device {METHOD FOR PROGRAMMING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to nonvolatile semiconductor memory devices, and more particularly to a flash capable of adjusting the threshold voltage of parasitic MOS transistors parasiticly present between adjacent memory cells of the same row electrically insulated by field regions. A memory device and a program method thereof are provided.

There is an increasing demand for semiconductor memory devices that are electrically erasable and programmable without refreshing data stored in the semiconductor memory device. In addition, increasing the storage capacity and the degree of integration of the memory device is the main flow. An example of a nonvolatile semiconductor memory device that provides a large capacity and a high degree of integration without refreshing stored data is a NAND type flash memory device. Such flash memory devices are widely used in electronic devices (eg, handheld terminals, portable computers, etc.), which may suddenly lose power, because they retain data even during power-off.

Nonvolatile semiconductor memory devices, such as NAND-type flash memory devices, include electrically erasable and programmable read-only memory cells, referred to as "flash EEPROM cells." Typically, a flash EEPROM cell comprises a cell transistor, which transistor is a semiconductor substrate (or bulk) of a first conductivity type (e.g., P-type), a second conductivity type (e.g., N spaced apart from each other) Type) source and drain regions, a floating gate located on the channel region between the source and drain regions and storing charges, and a control gate located on the floating gate. ).

An array of flash EEPROM cells having the structure described above is shown in FIG.

Referring to FIG. 1, a memory cell array includes a plurality of cell strings 10 respectively corresponding to bit lines. For convenience of illustration, two bit lines BL0 and BL1 and two cell strings 10 corresponding thereto are shown in FIG. 1. Each cell string 10 includes a plurality of flash EEPROM cells connected in series between a string select transistor SST as a first select transistor, a ground select transistor GST as a second select transistor, and the select transistors SST and GST. (MCm) (m = 0-15). The string select transistor SST has a drain connected to a corresponding bit line and a gate connected to a string select line SSL, and the ground select transistor GST is connected to a source and ground select line connected to a common source line CSL. GSL). The flash EEPROM cells MC15-MC0 are connected in series between a source of the string select transistor SSL and a drain of the ground select transistor GSL, and the cells MC15-MC0 correspond to corresponding word lines. Respectively connected to (WL15-WL0).

Initially, flash EEPROM cells of a memory cell array are erased to have a threshold voltage of, for example, -3V. Then, in order to program the flash EEPROM cells, the selected memory cell is changed to a higher threshold voltage by applying a high voltage (eg, 20 V) to the word line of the selected flash EEPROM cell for a predetermined time, while The threshold voltages of the (not selected) EEPROM cells do not change.

One problem arises when trying to program selected memory cell (s) connected on the same word line without programming unselected flash EEPROM cells connected on the selected word line. When a program voltage is applied to the word line, the program voltage is applied not only to the selected flash EEPROM cell but also to unselected flash EEPROM cells arranged along the same word line. Unselected flash EEPROM cells connected on the word line, in particular flash EEPROM cells adjacent to the selected memory cells, are programmed. Unintended programs of unselected cells connected to selected word lines are called "program disturbs."

One of the techniques for preventing the program disturb is a program banning method using a self-boosting scheme. A program banning method using a self-boosting scheme is described in US Pat. 5,677,873 entitled " METHOD OF PROGRAMMING FLASH EEPROM INTEGRATED CIRCUIT MEMORY DEVICES TO PREVENT IN ADVERTENT PROGRAMMING OF NONDESIGNATED NAND MEMORY CELLS THEREIN " and US Patent No. 5,991,202, entitled " METHOD FOR REDUCING PROGRAM DISTURB DURING SELF-BOOSTING IN A NAND FLASH MMEORY ", incorporated by reference.

In the program prohibition method using the self-boosting scheme, the ground path is interrupted by applying a voltage of 0V to the gate of the ground select transistor GST. A voltage of 0 V is applied to the select bit line (eg, BL0), and a power supply voltage (Vcc) of 3.3 V or 5 V is applied as the program inhibition voltage to the unselected bit line (eg, BL1). . At the same time, the source of the string select transistor SST is charged to Vcc-Vth (Vth is the threshold voltage of the string select transistor) by applying a power supply voltage to the gate of the string select transistor SST connected to the bit line BL1. . At this time, the string select transistor SST is effectively blocked (or shut off). The channel voltage of the program inhibited cell transistor is then boosted by applying a high voltage or a program voltage Vpgm to the selected word line and a pass voltage Vpass to the unselected word lines. This avoids F-N tunneling between the floating gate and the channel, as a result of which the program inhibited cell transistor remains in an initial erase state.

One problem can arise when the program prohibition scheme described above is used. That is, the flash EEPROM cell to be prohibited adjacent to the flash EEPROM cell to be programmed due to the leakage current flowing through the parasitic MOS transistor receives a "program disturb", which is described in detail below.

Referring to FIG. 2 showing a memory cell array cut along the dashed line A-A 'of FIG. 1, flash EEPROM cells connected to the same word line WL14 may be formed with field regions formed in a semiconductor substrate (or pocket P-well), or It is electrically insulated by the field oxide regions 12. In this structure, adjacent flash EEPROM cells, word line WL14, and a semiconductor substrate form parasitic MOS transistors. The channel region of the cell to be programmed inhibited among the adjacent flash EEPROM cells serves as a drain region of the parasitic MOS transistor, the channel region of the cell to be programmed serves as a source region of the parasitic MOS transistor, and the word line WL14 is a parasitic MOS transistor. Acts as a gate. The semiconductor substrate in contact with the field region 12 between the source and drain regions of the parasitic MOS transistor serves as a channel region of the parasitic MOS transistor.

When the high voltage Vpgm applied to the word line WL14 is higher than the threshold voltage of the parasitic MOS transistor, the parasitic MOS transistor is turned on. This causes a leakage current to flow through the parasitic MOS transistor turned on from the channel region of the cell to be programmed inhibited to the channel region of the cell to be programmed. Therefore, the self-boosted channel voltage of the cell to be program inhibited is lowered, so that the flash EEPROM cell to be program inhibited is subjected to program disturb.

This problem can be prevented by increasing the threshold voltage of the parasitic MOS transistor. A method of increasing the threshold voltage of the parasitic MOS transistor by injecting impurities into the field region has been proposed. However, this impurity implantation method has a disadvantage in that the breakdown voltage of the drain region is lowered. In addition, increasing the impurity concentration is limited by the trend of decreasing the size of the memory cell array. A method of raising the threshold voltage of parasitic MOS transistors by biasing a semiconductor substrate (or pocket P-well) with a negative voltage has been proposed. However, this method has the disadvantage of increasing the overall program time since it takes a lot of time to charge the pocket P-well.

In conclusion, there is a need for a new programming method capable of effectively blocking the leakage current flowing through parasitic MOS transistors existing between adjacent flash EEPROM cells.

The present invention provides a nonvolatile semiconductor memory device capable of increasing the threshold voltage of parasitic MOS transistors formed between adjacent cells without increasing the word line voltage during a program operation, and a program method thereof.

1 is a circuit diagram showing a memory cell array of a typical NAND flash memory device;

FIG. 2 is a cross-sectional view illustrating the memory cell array cut along the dotted line AA ′ in FIG. 1; FIG.

3 is a circuit diagram showing a NAND flash memory device according to the present invention; And

4 is an operation timing diagram illustrating a program operation of the NAND flash memory device according to the present invention.

* Description of symbols on the main parts of the drawings *

100: memory cell array 110: bit line level control circuit

120: row decoder circuit 130: page buffer circuit

140: thermal pass gate circuit

(Configuration)

According to one aspect of the present invention for achieving the above object, there is provided a program method of a nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device may include first and second bit lines, first and second cell strings connected to the first and second bit lines, and each cell string includes first and second select transistors. A memory cell transistor connected in series between the memory cell transistors, the memory cell transistors being respectively connected to corresponding word lines, respectively corresponding to the first and second bit lines and respectively latching data bits to be programmed. Include them. In the method of programming the nonvolatile semiconductor memory device, first, one of a first voltage and a second voltage is applied to the first and second bit lines according to data bits to be programmed, respectively, latched in the corresponding registers. Each is provided. After electrically separating the first and second bit lines from the corresponding registers, the first and second for a predetermined time such that the potential of the bit line to which the first voltage is applied is biased higher than the first voltage; The bit lines are supplied with a predetermined charging current. After interrupting current supply to the first and second bit lines, a program voltage is applied to a selected word line of the word lines.

In this embodiment, the first voltage is a ground voltage and the second voltage is a power supply voltage.

In this embodiment, when the program voltage is supplied to the selected word line, the channel voltage of the memory cell transistor in the second cell string connected to the selected word line is boosted higher than the second voltage.

In this embodiment, when the program voltage is supplied to the selected word line, a pass voltage lower than the program voltage is applied to unselected word lines such that the channel voltage of the memory cell transistors in the second cell string is boosted. do.

In this embodiment, adjacent cells arranged along the same row are electrically separated by a field region, and a parasitic MOS transistor is formed between the adjacent memory cells, wherein the same word line serves as a gate of the parasitic MOS transistor. One of the adjacent memory cells serves as a drain of the parasitic MOS transistor, and the other of the adjacent memory cells serves as a source of the parasitic MOS transistor.

In this embodiment, the potential of the bit line biased higher than the first voltage is the minimum voltage that causes the threshold voltage of the parasitic MOS transistor to increase above the program voltage applied to the selected word line.

In this embodiment, the predetermined time for which current is supplied to the bit lines is determined by bit line capacitance and a third voltage, where the third voltage is the minimum voltage of the bit line corresponding to the data bit representing the program. .

According to another feature of the invention, there is provided a nonvolatile semiconductor memory device, the memory device comprising a memory cell array having first and second cell strings and first and second bit lines corresponding to the cell strings. Include. Each of said cell strings has a string select transistor coupled to a corresponding bit line, a ground select transistor coupled to a common source line, and a plurality of memory cells connected in series between said string and ground select transistors; The cells are each connected to corresponding word lines; And adjacent memory cells connected to the same word line are electrically separated by a field region, and a parasitic MOS transistor is formed between the adjacent memory cells, wherein the same word line serves as a gate of the parasitic MOS transistor. One of the memory cells serves as a drain of the parasitic MOS transistor, and the other of the adjacent memory cells serves as a source of the parasitic MOS transistor. The nonvolatile semiconductor memory device further includes first and second page buffers, first and second bit line voltage control transistors, and a bit line voltage control circuit. First and second page buffers correspond to the first and second bit lines, respectively, and latch data bits to be programmed into the memory cell array during a program operation. First and second bit line voltage control transistors are connected between the first and second bit lines and the first and second page buffers, respectively, and the first and second bit line voltage control transistors are in response to a bit line level control signal. Electrically isolate / connect bit lines and the first and second page buffers. The bit line voltage control circuit generates a bit line level control signal commonly applied to the first and second bit line voltage control transistors. The bit line level control signal has a pass voltage such that data bits each latched in the page buffers are sufficiently transferred to corresponding bit lines during a first bit line setup period of a program cycle; Each of the page buffers loads the load current for a predetermined time to the corresponding bit line during the second bit line setup period of the program cycle such that the bit line corresponding to the data bit representing the program is biased to the field inhibit voltage higher than the ground voltage. Supply.

And further comprising a row decoder circuit for selecting one of said word lines, said second cell string being coupled to said selected word line when a high voltage is supplied during programming to said selected word line. The channel voltage of the memory cell transistor is boosted higher than the power supply voltage.

In this embodiment, the row decoder circuit applies the pass voltage to unselected word lines such that the channel voltage of the memory cell transistors in the second cell string is boosted.

In this embodiment, when the field inhibit voltage is biased to the bit line of the data bit representing the program, the threshold voltage of the parasitic MOS transistor is increased higher than the high voltage applied to the selected word line.

In this embodiment, the bit line level control signal remains at the pass voltage until the program cycle ends.

(Action)

According to such an apparatus and method, the threshold voltage of the parasitic MOS transistor is greater than the program voltage by applying a minimum voltage (or field inhibit voltage) for turning off the parasitic MOS transistor formed between adjacent cells on the same word line to the selected bit line. Is increased highly.

(Example)

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

A block diagram showing a NAND flash memory device according to the present invention is shown in FIG. The memory device includes a cell array 100, a row decoder circuit 120, a page buffer circuit 130, and a column pass gate circuit 140. The cell array 100 consists of a plurality of cell strings (or NAND strings) 12 arranged in columns. Each cell string 12 includes a string select transistor SSTm (m = 0, 1, 2, ..., i), and the gate of the string select transistor SSTm is connected to the string select line SSL. . Each cell string 12 also includes a ground select transistor GSTm, with the gate of the ground select transistor GSTm connected to the ground select line GSL. Between the source of the string select transistor SSTm of each cell string 12 and the drain of the ground select transistor GSTm, a plurality of memory cells or flash EEPROM cells MCn (n = 0,1,2, ..., 15) are connected in series. Control gates of the EEPROM cells MCn of each cell string 12 are respectively connected to corresponding word lines WLj. A drain of each string select transistor SSTm is connected to a corresponding bit line BLm, and a source of each ground select transistor GSTm is connected to a common source line CSL. The string select line SSL, the word lines WLj and the ground select line GSL are electrically connected to the row decoder circuit 120.

The bit lines BLi are connected to the page buffer circuit 130 through corresponding NMOS transistors M1 as bit line level control transistors, and the NMOS transistors M1 are connected to the bit line level control circuit 110. Controlled by the control signal (BLCTL) generated from the common. Each NMOS transistor M1 adjusts the voltage level of the corresponding bit line in response to the control signal BLCTL output from the bit line level control circuit 110.

3, the page buffer circuit 130 includes page buffers 130_i corresponding to the bit lines BLi, respectively. During a read cycle, the page buffer senses data from the selected cell and passes the data through the column pass gate circuit 140 to a data output buffer (not shown). During the program cycle, the page buffer stores data applied from the input / output buffer through the column pass gate circuit 140. Hereinafter, the configuration and the function will be described with reference to the page buffer 130_0 corresponding to the bit line BL0. The page buffers 130_1 to 130_i corresponding to the other bit lines BL1 to BLi have the same function and configuration as the page buffer 130_0.

The page buffer 130_0 includes a latch 50 consisting of a PMOS transistor M2, four NMOS transistors M3-M6, and two inverters. The gate and the source of the PMOS transistor M2 whose drain is connected to the node N1 are respectively connected to the bit line precharge signal LOADEN and the power supply voltage Vcc. The PMOS transistor M2 supplies current to the bit line BL0 in response to the bit line precharge signal LOADEN that is activated when the bit line setup operation is performed. Transistor M3, whose source and gate are connected to ground voltage Vss and signal BLDIS, respectively, is connected between node N1 and ground voltage, discharging the voltage on bit line BL0 and turning off the page buffer (i.e. latch) ) To the ground voltage level. NMOS transistor M4, whose gate is connected to signal BLSEL, is connected between node N1 and node N2 of latch 50. Node N3 of latch 50 is connected to ground voltage through NMOS transistors M5 and M6. The gate of the transistor M5 is connected to the node N1, and the gate of the transistor M6 is connected to the signal LATCH. NMOS transistors M5 and M6 change the state of data stored in latch 50 in response to the voltage level on bit line BLO and the signal LATCH.

As is well known, the program cycle of a NAND flash memory device consists of a bit line setup operation, a program operation and a recovery operation. In the present invention, the bit line setup operation is divided into a first bit line setup period (A) and a second bit line setup period (B). During the first bit line setup period A, data bits latched in the page buffers 130_i are transferred to corresponding bit lines. During the second bit line setup period (B), a bit line corresponding to a data bit representing a program is referred to as a minimum source-bulk voltage (Vfi, hereinafter " field inhibited voltage ") required to turn off a parasitic MOS transistor. Bias). When the bit line corresponding to the data bit representing the program is biased to the field inhibit voltage, the threshold voltage of the parasitic MOS transistor formed between adjacent flash EEPROM cells is higher than the voltage Vpgm applied to the selected word line.

In general, the threshold voltage Vt of the MOS transistor is determined by the following equation.

Here, the voltage Vto represents a threshold voltage Vt obtained when V _SB is 0V, and gamma represents a process parameter. As can be seen from the equation, the threshold voltage (Vt) value is affected by the voltage (V _SB ) between the source and the bulk. The field inhibit voltage (Vfi) level is a word when the threshold voltage (or potential of the field region) of the parasitic MOS transistor is effectively blocked so that leakage current between adjacent cells can be effectively blocked without increasing the voltage applied to the word line during a program operation. Will be higher than the line voltage). An operation for biasing the bit line corresponding to the flash EEPROM cell to be programmed to the field inhibit voltage Vfi is described in detail later.

4 is an operation timing diagram illustrating a program operation of the NAND flash memory device according to the present invention. Hereinafter, a program operation of the NAND flash memory device will be described in detail with reference to FIGS. 3 and 4.

Assume that the data bits " 01 " to be programmed are loaded into the page buffers 130_0 and 130_1 respectively corresponding to the bit lines BL0 and BL1. The bit line BL0 corresponding to the page buffer 130_0 latching the "0" data bit is called a selection bit line, and the bit line BL1 corresponding to the page buffer 130_1 latching the "1" data bit is It is called an unselected bit line. In addition, the word line WL14 connected to the cell to be programmed (e.g., MC14) is supplied with the program voltage Vpgm during the program operation of the program cycle and is called a select word line. The remaining word lines WL0 to WL13 and WL15 receive a pass voltage Vpass and are referred to as unselected word lines.

Under this assumption, as shown in FIG. 4, in the first bit line setup period A, the string select signal SSL transitions to the high level of the power supply voltage and the signals BLSEL and BLCTL are the pass voltage Vpass. Let's transition to the high level. At the same time, the signals GSL, CSL, BLDIS, LATCH are maintained at the low level of the ground voltage. According to this condition, the NMOS transistors M1 are turned on by the bit line level control signal BLCTL having the pass voltage Vpass, and the string select transistors SST0 and SST1 of the cell strings 12 are turned on. It is turned on by the string select signal SSL having a high level of the power supply voltage. In addition, the NMOS transistors M4 in the page buffers 130_0 and 130_1 are turned on by the signal BLSEL having a high level of the pass voltage Vpass. As a result, in the first bit line setup period A, the select bit line BL0 is developed to ground voltage, and the unselected bit line BL1 is developed to the power supply voltage as a program inhibit voltage.

When the second bit line setup period B starts, a voltage Vcsl is applied to the common source line CSL to prevent punch through of the ground select transistors GST0 and GST1. The signal BLSEL transitions from the high level to the low level, and as a result, the bit lines BL0 and BL1 are electrically separated from the corresponding page buffers 130_0 and 130_1. At the same time, a predetermined time (t _fi) bit lines (BL0, BL1) to a load current (I _load) from the bit line supply voltage of the voltage level of the pre-charging signal (LOADEN) at a high level so as to supply a predetermined voltage during the ( V _load ). The relationship between the time t _fi and the load current I _load for biasing the bit line corresponding to the data bit representing the program to the field inhibit voltage Vfi is as follows.

Here, the symbol C _BL represents the capacitance of the bit line.

The select bit line BL0 is biased to the field inhibit voltage Vfi by the load current supplied through the PMOS transistors M2 during the second bit line setup B or during the time t _fi . On the other hand, the unselected bit line BL1 is maintained at a voltage set in the first bit line setup period A, that is, a power supply voltage. At this time, since the string select transistors SST0 and SST1 are substantially shut off, the cell strings 12 corresponding to the bit lines BL0 and BL1 are floated.

Subsequently, when a substantial program operation starts, a high voltage Vpgm is applied to the select word lines WL14 and a pass voltage Vpass is applied to the unselected word lines WL0-WL13 and WL15. As described above, since the cell string 12 corresponding to the unselected bit line BL1 is floated, the flash EEPROM cell defined by the unselected bit line BL1 and the select word line WL14 ( MC14), i.e., the channel voltage of the program inhibiting cell, is boosted to a voltage sufficient to prevent FN tunneling according to the self-boosting mechanism. The channel voltage so boosted (eg, 8V or higher) prevents a program inhibited flash EEPROM cell from being programmed. The channel voltage of the flash EEPROM cell MC14 defined by the selection bit line BL1 and the selection word line WL14, that is, the flash EEPROM cell to be programmed is a field biased in the second bit line setup period B. It is maintained at the prohibited voltage Vfi. After the program operation is completed, the potentials of the bit lines BL0 and BL1 are discharged and the page buffers 130_0 and 130_1 are initialized during the recovery operation period.

According to the bias condition described above, the threshold voltage Vt of the parasitic MOS transistor formed between adjacent flash EEPROM cells MC14 connected to the select word line WL14 is, as shown in Equation 1, the flash to be programmed. It is increased higher than the word line voltage Vpgm in proportion to the channel voltage Vfi of the EEPROM cell, that is, the source-bulk voltage V _SB . That is, because the parasitic MOS transistors formed between adjacent flash EEPROM cells of the selected word line are turned off, the leakage current flowing through the channel of the parasitic MOS transistor is blocked during the program operation. In conclusion, it is possible to prevent program disturb caused by parasitic MOS transistors.

As described above, the threshold voltage of the parasitic MOS transistor is increased above the program voltage by applying a minimum voltage (or field inhibit voltage) for turning off the parasitic MOS transistor formed between adjacent cells on the same word line to the selected bit line. do. Therefore, program disturb due to parasitic MOS transistors can be prevented.

Claims (12)

First and second bit lines, first and second cell strings coupled to the first and second bit lines, and each cell string is a memory cell connected in series between first and second select transistors A nonvolatile semiconductor memory comprising transistors, the memory cell transistors respectively connected to corresponding word lines, each register corresponding to the first and second bit lines and each having a latch for latching data bits to be programmed In the programming method of the device: Providing one of a first voltage and a second voltage to the first and second bit lines, respectively, in accordance with data bits to be programmed latched in the corresponding registers, respectively; Electrically separating the first and second bit lines from the corresponding registers; Supplying current to the first and second bit lines in response to bit line precharge for a predetermined time such that the potential of the bit line to which the first voltage is applied is biased higher than the first voltage; Applying a program voltage to a selected one of said word lines after interrupting current supply to said first and second bit lines. The method of claim 1, The first voltage is a ground voltage, and the second voltage is a power supply voltage. The method of claim 1, And when the program voltage is supplied to the selected word line, a channel voltage of a memory cell transistor in the second cell string connected to the selected word line is boosted higher than the second voltage. The method of claim 1, When the program voltage is supplied to the selected word line, a pass voltage lower than the program voltage is applied to unselected word lines such that channel voltages of memory cell transistors in the second cell string are boosted. Way. The method of claim 1, Adjacent cells arranged along the same row are electrically separated by field regions, and parasitic MOS transistors are formed between the adjacent memory cells, wherein the same word line serves as a gate of the parasitic MOS transistor, and the adjacent memory Wherein one of the cells serves as a drain of the parasitic MOS transistor, and the other of the adjacent memory cells serves as a source of the parasitic MOS transistor. The method of claim 5, And the potential of the bit line biased higher than the first voltage is a minimum voltage that causes the threshold voltage of the parasitic MOS transistor to increase higher than the program voltage applied to the selected word line. The method of claim 6, The predetermined time period during which the current is supplied to the bit lines is determined by bit line capacitance and a third voltage, wherein the third voltage is a minimum voltage of a bit line corresponding to a data bit representing a program. . A memory cell array having first and second cell strings and first and second bit lines corresponding to the cell strings; Each of said cell strings has a string select transistor coupled to a corresponding bit line, a ground select transistor coupled to a common source line, and a plurality of memory cells connected in series between said string and ground select transistors; The cells are each connected to corresponding word lines; And Adjacent memory cells connected to the same word line are electrically separated by a field region, and a parasitic MOS transistor is formed between the adjacent memory cells, wherein the same word line serves as a gate of the parasitic MOS transistor, and the adjacent memory One of the cells serves as a drain of the parasitic MOS transistor, and the other of the adjacent memory cells serves as a source of the parasitic MOS transistor; First and second page buffers corresponding to the first and second bit lines, respectively, for latching data bits to be programmed into the memory cell array during a program operation; Connected between the first and second bit lines and the first and second page buffers, respectively, the first and second bit lines and the first and second page in response to a bit line level control signal. First and second bit line voltage control transistors electrically separating / connecting buffers; A bit line voltage control circuit for generating a bit line level control signal commonly applied to the first and second bit line voltage control transistors, The bit line level control signal has a pass voltage such that data bits each latched in the page buffers are sufficiently transferred to corresponding bit lines during a first bit line setup period of a program cycle; And Each of the page buffers supplies a load current for a predetermined time to the corresponding bit line during the second bit line setup period of the program cycle such that the bit line corresponding to the data bit representing the program is biased with a field inhibit voltage higher than the ground voltage. A nonvolatile semiconductor memory device comprising a bit line precharge circuit. The method of claim 8, And a row decoder circuit for selecting one of the word lines, the channel voltage of a memory cell transistor in the second cell string connected to the selected word line when a high voltage is supplied when programming to the selected word line. A nonvolatile semiconductor memory device boosted higher than this power supply voltage. The method of claim 9, And the row decoder circuit applies the pass voltage to unselected word lines such that channel voltages of memory cell transistors in the second cell string are boosted. The method of claim 8, And the threshold voltage of the parasitic MOS transistor is increased higher than the high voltage applied to the selected word line when the field inhibit voltage is biased to the bit line of the data bit representing the program. The method of claim 8, And the bit line level control signal is maintained at the pass voltage until the program cycle ends.