KR100384890B1 - Apparatus for self test of Embedded Memory in Semiconductor Circuit - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a test apparatus used for automatically testing a memory inside a semiconductor device circuit from outside thereof.

2. The technical problem to be solved by the invention

An object of the present invention is to provide a test apparatus for testing a memory inside a semiconductor device circuit for performing a test in a circuit for testing a memory inside a semiconductor device circuit.

3. Summary of Solution to Invention

The present invention provides a test pattern generating means for generating a test pattern in testing a memory inside a semiconductor element circuit; Data selecting means for selecting normal data generated from an internal circuit and test pattern data generated from the test pattern generating means; Data input means for inputting data selected by the data selecting means into a memory cell; Data output means for outputting data from the memory cell; And data comparing means for comparing the input data of the data input means with the output data of the data output means to determine whether the memory cell is defective.

4. Important uses of the invention

The present invention is used to test a memory inside a semiconductor device circuit.

Description

Apparatus for self test of Embedded Memory in Semiconductor Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to testing of memory in semiconductor device circuits, and more particularly to a test apparatus used to test memory in semiconductor device circuits to facilitate and automatically perform the test.

In the conventional memory test, since the input and output data cannot be controlled from an external pin, the failure of various models could not be detected by performing a whole function test or a simple test. Therefore, it is impossible to detect the defects according to the data pattern generated in the memory, but even if the system works well, if it meets the sensitive pattern, the defect occurs. As a result, it was necessary to test the memory cells in the circuit effectively and automatically.

On the other hand, US patent "Maximizing improvement to fault coverage of system logic of an integrated circuit with embedded memory arrays [right holder, Levit No. 5379303, Jan. 3, 1995]] is integrated using a memory array inside the circuit. The circuit (IC: Integrated Circuit) can be tested and the scan circuit can be used to view the output of the integrated circuit (IC: Integrated Circuit), but since it does not have a pattern generator and a data comparator, it is difficult to perform memory cell tests. There was a problem that can not be tested. Thus, various circuits have been devised, but there has been a problem in that the memory in the circuit cannot be tested effectively because it remains only to test a simple stuck at fault of the memory cell.

The present invention has been proposed to solve the above problems, and is a test that can automatically perform tests such as a fixed defect, a transition defect, and an inductive defect of a memory in a circuit of a semiconductor device automatically outside the circuit. The purpose is to provide a device.

1 is a configuration diagram of an embodiment of the present invention including a memory cell to be tested.

2 is a diagram illustrating an embodiment of a pattern generator in a system according to the present invention.

3 is a block diagram of an embodiment of a scan (SCAN) circuit in accordance with the present invention;

Explanation of symbols on the main parts of the drawings

101: internal circuit 102: pattern generator

103: scan circuit 104: data input buffer

105: memory cell 106: comparison pattern generator

107: comparator 108: data output buffer

109: comparison result control circuit

The present invention for achieving the above object, the test pattern generating means for generating a test pattern in testing the memory inside the semiconductor element circuit; Data selecting means for selecting normal data generated from an internal circuit and test pattern data generated from the test pattern generating means; Data input means for inputting data selected by the data selecting means into a memory cell; Data output means for outputting data from the memory cell; And data comparing means for comparing the input data of the data input means with the output data of the data output means to determine whether the memory cell is defective.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a system configuration according to the present invention including a memory cell to be tested.

The system to which the present invention is applied is connected to the internal circuit 101, the pattern generator 102, and the data input buffer 104 to receive data generated from the internal circuit 101 and the pattern generator 102 and to test the data. A scan circuit 103, a scan circuit 103, and a memory cell 105 which selects the pattern data P transmitted from the pattern generator and selects the internal data D transmitted from the internal circuit during normal operation of the circuit; Connected to the data input buffer 104, the data input buffer 104 and the data output buffer 108 to buffer the data input from the scan circuit 103, the data input buffer 104 by a write signal A memory cell 105, a pattern generator 102, a comparison result control circuit 109, a memory cell 105, and a comparator 107 which receive data from the data and transfer the data to the data output buffer 108 by a read signal. ) From the memory cell 105 It is connected to a comparison pattern generator 106, a memory cell 105, and a comparator 107 that receives a signal synchronized with a read signal for transferring data to the output buffer 108, and inputs data to the comparator 107. Is connected to the data output buffer 108, the comparison pattern generator 106, and the data output buffer 108, which buffers the data output from the memory cell 105 and delivers the data to the comparator 107. Connected with a comparator 107, a comparison pattern generator 106, a comparator 107, and a pattern generator 102 for comparing data, the pattern generator 102 and the comparison pattern generator according to the quantity / defect of the memory cell 105. A comparison result control circuit 109 for controlling 106 is provided.

In addition, a status display device (for example, an LED display panel, etc.) 110 that displays the status of the memory cell 105 under test from the outside is connected to the comparator 107 to display the quantity / defect of the memory cell 105. can do.

Referring to the operation of the system as described above, the data generated from the pattern generator 102 is transmitted to the scan circuit 103 by the operation of the system clock, the scan circuit 103 in the pattern generator 102 at the time of the memory test The generated data is selected and transferred to the data input buffer 104, and the transferred data is written to the corresponding memory cell 105 by the write signal and read by the read signal to the data output buffer 108. Is printed through). At the same time, the read signal causes data to be output from the comparison pattern generator 106, allowing the comparator 107 to compare the output of the comparison pattern generator 106 with the output of the data output buffer 108. If the comparison result is matched, the output of the comparator is in a state 1, and the output of the comparison result control circuit 109 operates as a system clock. If the memory cell 105 is bad and the data does not match, the comparator output In this state, the system clock is stopped via the AND gate, which is the comparison control circuit 109, and the operation of the pattern generator 102 and the comparison pattern generator 106 is stopped.

On the other hand, the memory test should be tested using various data patterns. However, in the case of the memory inside the circuit, the data cannot be written and read at will, and thus the memory cells cannot be tested in various patterns. Therefore, in order to test the memory inside the circuit, the test is performed using the pattern generator 102 configured as shown in FIG. 2, and the scan circuit 103 as shown in FIG. 3 capable of selecting normal data and test pattern data of the internal circuit. Is needed.

2 is a schematic diagram of an embodiment of a pattern generator 102 in a system in accordance with the present invention.

The pattern generator 102 has four shift registers SR0-SR3 composed of flip-flops. The shift register SR0 receives an input from a data select input SDI, and the shift register ( SR1) 1 sets the input signal as the outputs Q and Q of the shift register SR0, shift register SR2 sets the input signal as the outputs Q and Q of the shift register SR1, and shift register SR3. 3 denotes an input signal as outputs Q and Q of shift register SR2, and output terminals of dual shift registers 2102-3 (SR2) and shift register 3 (102-4) (SR3) It is connected to the input terminal of Exclusive OR Gate IN 102-5, and the Exclusive OR Gate IN 102-5 output terminal is shift register 0 (SR0) (102). It is connected to the input terminal of the inverter 102-6, which is the input terminal of the negative terminal -1), and the system clock CP and the comparator 107. ) The output terminal is connected to an input of an end gate, which is a control circuit 109 as a result of the comparison.

Referring to the operation of the pattern generator according to the present invention, four SR flip-flops, which are shift registers, receive an input of a data select input (SDI) and output four data (P0-P3). Four output data P0-P3 are input to the memory cell through the scan circuit. At this time, P0-P3, the output of shift register 0 (SR0)-shift register 3 (SR3), is set to 1 state using the Select Data Input (SDI) and Scan Select Input (SSI). After initialization, the outputs of shift register 2 (SR2) and shift register 3 (SR3) among the four output data become inputs to the exclusive OR gate 102-5 and the inverter 102-6. By feeding back to the shift register 0 (SR0) 102-1, the automatic test pattern shown in Table 1 is generated. Test the entire memory cell with one data pattern using the generated automatic test pattern, and then set the scan select input (SSI) to 0 and test again with the opposite data pattern. Accordingly, when the scan select input (SSI: Scan Select Input) is 1, the pattern generator of FIG. 2-1 is outputted as P0-P3 as it is, but when the scan select input (SSI: Scan Select Input) is 0 The output of Q is output to P0-P3, and the output pattern is as shown in Table 1. The same data pattern is repeated from 0 to 15 times for the address.

Address SSI P0 P1 P2 P3 Reset (0) 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) One 1 (0) 0 (1) 1 (0) 1 (0) 1 (0) 2 1 (0) 0 (1) 0 (1) 1 (0) 1 (0) 3 1 (0) 0 (1) 0 (1) 0 (1) 1 (0) 4 1 (0) 1 (0) 0 (1) 0 (1) 0 (1) 5 1 (0) 0 (1) 1 (0) 0 (1) 0 (1) 6 1 (0) 0 (1) 0 (1) 1 (0) 1 (0) 7 1 (0) 1 (0) 0 (1) 0 (1) 1 (0) 8 1 (0) 1 (0) 1 (0) 0 (1) 0 (1) 9 1 (0) 0 (1) 1 (0) 1 (0) 0 (1) 10 1 (0) 1 (0) 0 (1) 1 (0) 1 (0) 11 1 (0) 0 (1) 1 (0) 0 (1) 1 (0) 12 1 (0) 1 (0) 0 (1) 1 (0) 0 (1) 13 1 (0) 1 (0) 1 (0) 0 (1) 1 (0) 14 1 (0) 1 (0) 1 (0) 1 (0) 0 (1) 15 1 (0) 1 (0) 1 (0) 1 (0) 1 (0) One 1 (0) 0 (1) 1 (0) 1 (0) 1 (0)

A fixed defect can be detected by writing and reading 0 and 1 into the memory cell, and the transition defect is a defect in which the data does not change when the data is changed from 1 to 0 or from 0 to 1, so the scan selection input Transient defects can be detected by changing the Scan Select Input (SSI) from 1 to 0 or from 0 to 1 to read or write data to the memory cell. In addition, in order to detect an inductive defect, the state of the induced memory cell should be tested when the inductive memory cell transitions from 0 to 1 and from 1 to 0. In other words, inductive defects can be detected by changing the scan select input (SSI) from 1 to 0 or from 0 to 1, as in the case of detecting a transition defect. Can be.

Therefore, the fixed defect can be detected by writing and reading 1 and 0 to each memory cell as in the test pattern of Table 1, and transition defects and inductive defects can also be detected from 1 to 0 in each memory cell. Defects can be detected by changing the data from 0 to 1 or by writing the data.

The data pattern of the comparison pattern generator 106 is shown in Table 1, and synchronizes the address of the comparison pattern generator with the address of the memory cell by synchronizing with the CE signal which is a read signal of the memory cell. The comparator 107 compares the output data of the comparison pattern generator with the output data of the memory cell at each bit and shows the result.

3 is a circuit diagram of an embodiment of a scan circuit according to the present invention.

As shown, AND gates 103-1 and 103-2 for selecting test data and normal data, OR gates 103-3, and flip-flops (103-4) is provided.

In detail, the first end gate 103-1 which inputs the output of the pattern generator and the scan selection signal, the second end that receives the negative signal of the scan selection signal and the normal data signal generated from the internal circuit are input. Input output of ohwa gate 103-3 and output of ohwa gate 103-3 as inputs of gates 103-2, first and second end gates 103-1, 103-2 It consists of flip-flops 103-4.

Referring to the operation of the circuit illustrated in FIG. 1, when the scan select signal SS input becomes 0, the D data passes through an AND gate 103-1 and an OR gate 103-3. Appears on the output, the scan data (P) appears at the output of the flip-flop (103-4) when the system clock (SC) is operating. When the scan select signal (SS) input is 1, P data is displayed at the OR gate 103-3 through the AND gate 103-2, and the system clock SC is operated. The normal data D of the internal circuit is displayed at the output of the flip-flop 103-4. To test the memory, data generated in the test pattern is input to the P pin, which is the output of the AND gate 103-1, and flip-flop 103 when the skin select signal SS is 1. It is written to the memory cell 105 via the data input buffer 104 through the output of -4). In normal operation, the skin select signal (SS) becomes zero, so that the normal data D passes through the data input buffer 104 to the memory cell 105 through the output of the flip-flop 103-4. It is written. <Table 2> shows the operation state of the scan circuit 103, and writes a data pattern which is likely to cause a defect due to interference effects between memory cells using the output P of the pattern generator 102 of FIG. Can be tested effectively.

D SS P Q 0 0 X 0 One 0 X One X One 0 0 X One One One

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

According to the present invention as described above, by using a test apparatus for testing a memory in a circuit, input data is applied through a test pattern to confirm normal operation, and a fixed type in which data is fixed in a memory cell. In addition to failures, Coupling faults cause state transitions to other cells due to transition faults that do not change data when the data changes, and electrostatic coupling when the cell's state transitions. ), The defect of the memory cell can be detected automatically, and the defect of the memory can be detected automatically from the outside, thereby improving the reliability of the system.

Claims (5)

delete delete delete In testing the memory inside the semiconductor device circuit, Test pattern generating means for generating a test pattern-The test pattern generating means includes: a first flip flop that receives an input from a data selection input (SDI), and a second flip that receives outputs Q1 and Q1 of the first flip flop A flop, a third flip-flop having the outputs Q2 and Q2 of the second flip-flop as inputs, a fourth flip-flop having the outputs Q3 and Q3 of the third flip-flop as inputs, and an output Q3 and the output of the third flip-flop An Exclusive OR Gate with the output Q4 of the fourth flip-flop as an input and an output circuit using the output Q and the scan select input of the flip-flops; Data selecting means for selecting normal data generated from an internal circuit and test pattern data generated from the test pattern generating means; Data input means for inputting data selected by the data selecting means into a memory cell; Data output means for outputting data from the memory cell; Data comparison means for comparing the input data of the data input means with the output data of the data output means to determine whether a memory cell is defective; And As a result of the comparison of the data comparing means, the system control means stops the system clock when a failure occurs in the memory cell, and continuously generates the system clock when the failure does not occur. Automatic memory test device in the circuit comprising a. In testing the memory inside the semiconductor device circuit, Test pattern generating means for generating a test pattern; Data selecting means for selecting normal data generated from an internal circuit and test pattern data generated from the test pattern generating means, wherein the data selecting means comprises: a first end gate for inputting an output of the test pattern generating means and a scan selection signal; (AND Gate), a second end gate for inputting a reverse signal of the scan selection signal and a normal data signal generated from an internal circuit, and outputs of the first and second end gates. An OR gate having an input and a flip-flop having an output of the OR gate; Data input means for inputting data selected by the data selecting means into a memory cell; Data output means for outputting data from the memory cell; Data comparison means for comparing the input data of the data input means with the output data of the data output means to determine whether a memory cell is defective; And As a result of the comparison of the data comparing means, the system control means stops the system clock when a failure occurs in the memory cell, and continuously generates the system clock when the failure does not occur. Automatic memory test device in the circuit comprising a.