KR100383505B1 - Digital automatic gain control method and apparatus for code division multiple access wireless telephone - Google Patents

Abstract

A method and apparatus are disclosed for generating digital receiver AGC values and transmitter AGC values for a spread spectrum transceiver. The method includes (a) integrating 34a the power of the received and sampled signal; (b) calculating a log of received and integrated power (34b); (c) subtracting a predetermined reference value from a log of power to generate a first error signal (34c); (d) filtering the first error signal 34d; (e) comparing (34e) the filtered first error signal with a predetermined first threshold value; (f) increasing or decreasing 34e the first counter value as a function of the result of the comparing step and resetting the filter accumulator; And (g) converting the first counter value to an analog voltage for controlling the gain of the spread spectrum receiver amplifier 36a.

Description

Digital automatic gain control method and apparatus for code division multiple access wireless telephone

FIELD OF THE INVENTION The present invention relates generally to telecommunications devices, and more particularly to wireless telephones compatible with Spread Spectrum (SS) Code Division Multiple Access (CDMA) protocols.

A direct-sequence or direct sequence coding spread spectrum communication technique essentially combines two digital signals or bit streams to produce a third signal prior to transmission. The first signal is an information signal such as an output of a digitalized voice circuit. For example, the first signal may have a bit rate of 10 kb / s. The second signal is generated by a random-sequence or pseudonoise (PN) generator and is a stream of essentially random bits having a bit rate tens of orders of magnitude greater than the bit rate of the digitized speech signal. Modulation of these two signals results in a third signal having the same bit rate as the second signal. However, the third signal also includes a digitized voice signal. At the receiver, the same random-sequence generator produces a random bit stream that reflects the original random-sequence that was used for modulation at the transmitter. For proper operation, after carrier frequency demodulation, the PN generator of the receiver must be synchronized with the input PN sequence. By removing the random sequence from the received signal and integrating it over a symbol period, a despread signal is obtained. Ideally, the despread signal accurately represents the original 10 kb / s speech signal.

The mobile station-base station compatibility standard (TIA / EIA / IS-95 (July 1993)), a TIA / EIA interim standard for dual-mode wideband spread-spectrum cellular systems, describes in section 6.1.2 that the mobile station has two independent Specifies that they will provide These two techniques are open loop estimation based solely on mobile station operation and closed loop correction involving mobile station and cell site controller or base station. In the latter technique, the mobile station adjusts its output power level in response to power control bits received over the forward traffic channel. In the former technique, the received signal strength to the base station is used.

Power control in CDMA systems is also referred to as "Introduction to the Common Air Interface Specification (CAI) for the CDMA and Spread Spectrum Digital Cellular Standards-Code Division Multiple Access (CDMA) for digital cellular systems and personal cellular networks." In the publication entitled “Application Overview” (Swecome Inc., 3/28/92), it is described on pages 10 and 12 and shown in full in FIGS. 3-2. As described in this publication, the purpose of mobile station transmitter power control processing is to produce a nominal received signal power from each mobile station transmitter operating within a cell, in a cell site receiver. If all mobile stations are so controlled, the end result is that the total signal power received from all of the mobile stations at the cell site is equal to the nominal received power multiplied by the number of mobile stations.

Therefore, control of transmitter power can be evaluated as an important consideration when designing a mobile station such as a cordless telephone for operation in a CDMA telecommunications system.

Moreover, the operation of the mobile station receiver plays an important role in the correct operation of the open loop power control in that open loop power control depends on the signal received from the cell site by the mobile station. In particular, the operation of the receiver Automatic Gain Control (AGC) function must be carefully considered.

In a CDMA system the receiver is required to operate in the 80 dB range. However, due to the high sampling rate, the number of bits of the resolution of the receiver analog-to-digital (A / D) converter is limited. If the problem is further complicated by the limited resolution of the A / D converter, the receiver AGC function must also accommodate received signal fluctuations due to slow fades and fast fades.

In a CDMA system, fast AGC functionality should not undermine the functionality of the receiver algorithm, and ideally should not undermine the information gathered for convolutional decoding and synchronization acquisition.

The CDMA specification also specifies the operation of mobile station transmitters. The response time of the transmitter power to the change in the received signal level is specified as 30 ms, after which the transmit power level must be determined within a new range. The range for the transition period is also specified. However, the specified transmitter response time is too long for the fast receiver AGC function, thus excluding the solution where the transmitter AGC setting and the receiver AGC setting are the same.

In addition, the accuracy of the transmitter gain setting is specified in detail in the CDMA specification. To meet the CDMA specification, a transmitter power step size of 0.25 dB is required at the transmitter. In contrast, the receiver is rather tolerant of the inaccuracy of gain setting, thus enabling a less complex and less expensive solution. In addition, the receiver requires a step size greater than 0.25 dB to enable higher tracking rates.

The following United States patents and other publications generally relate to the teachings of the present invention.

"Automatic Gain Control Device for Spread Spectrum Communication Devices," US Patent 5,168,505, dated December 1, 1992, Akazawa et al.

"High Dynamic Range Closed Loop Automatic Gain Control Circuit" by US Pat. No. 5,107,225, dated April 21, 1992, Whitley III.

US Patent 5,093,840, published date 1992.3.3, Schilling, "Adaptive Power Control for Spread Spectrum Transmitters."

US Pat. No. 5,099,204, publication date March 24, 1992, Whitley III, " Linear Gain Control Amplifier ".

U.S. Patent 5,132,985, dated 1992.7.21, Hashimoto et al. "Spread Spectrum Receiver".

US Patent No. 5,056,109, publication date 1991.10.8, Gilhousen et al. "Method and Apparatus for Transmission Power Control in a CDMA Cellular Mobile Phone System".

US Patent No. 5,265, 119, dated May 15, 1991, Gilhousen et al. "Method and Apparatus for Transmission Power Control in a CDMA Cellular Mobile Phone System".

United States Patent 4,993,044, publication date February 2, 1991, Akazawa et al., &Quot; spread spectrum communication receiver ".

"Spread-Spectrum Multiple Access Communication System Using Satellite or Terrestrial Repeaters," US Patent No. 4,901,307, published date 1990.2.13, Gilhousen et al.

PCT International Publication No. W0 93/1060, Publication Date May 27, 1993, "Adaptive Power Control and Method for Spread Spectrum Communication Systems".

PCT International Publication No. WO 93/07702, Publication Date 1993.4.15, "Transmitter Power Control System".

PCT International Publication No. WO 93/05585, Publication Date 1993.3.18, "Method of Automatic Transmission Power Control in a Transceiver Suitable for CDMA Environments Using Direct Sequence Spreading".

Purpose of invention

It is an object of the present invention to provide a digital AGC implementation that enables improved receiver and transmitter control in a transceiver.

Another object of the present invention is to provide a receiver AGC function and an open loop transmitter power control function, each having a separate tracking accuracy.

It is still another object of the present invention to provide a method and apparatus for providing a receiver AGC function and an open loop transmitter power control function, each having separate tracking rates for use in spread spectrum radiotelephones.

Summary of the Invention

The above and other problems are overcome and the objects are realized by the method and apparatus according to the invention. The present invention teaches a method for generating a receiver AGC signal for a transceiver, such as a spread spectrum transceiver, and an apparatus that operates in accordance with the method.

The method of the present invention comprises the steps of (a) integrating the power of the received and sampled signal; (b) calculating a log of received and integrated power; (c) subtracting a predetermined reference value from a log of power to generate a first error signal; (d) filtering the first error signal; (e) comparing the filtered first error signal with a predetermined first threshold value; (e) increasing or decreasing the first counter value as a function of the result of the comparing step and simultaneously resetting the filter accumulator; And (f) converting the first counter value into an analog voltage for gain control of the receiver.

In a preferred embodiment of the invention, the log is a secondary log of power, and the calculating step (a) prioritizes the digital word representing the value of the received and integrated power to determine the position of the most significant set bit of the digital word. Inputting to encoder means; And (b) using the determined location as a secondary log.

For the case where the log is a secondary login, the calculating step comprises the steps of: (a) inputting a digital word representing the value of the received and integrated power to the priority encoder means to determine the position of the most significant set bit of the digital word; (b) extracting one or more bits adjacent to the determined most significant set bit; (c) linking the extracted bit or bits to a value representing a determined position of the most significant set bit; And (d) using the resulting concatenated bits as an approximation of the secondary logarithm.

The method of the present invention comprises the steps of (a) generating a second counter value; (b) subtracting the second counter value from the first counter value to form a second error signal; (c) filtering the second error signal; (d) comparing the filtered second error signal with a predetermined second threshold value; (e) increasing or decreasing the second counter value as a function of the result of comparing the filtered second error signal and resetting the filter accumulator; And (f) generating a transmitter AGC value by converting at least a second counter value into an analog voltage for gain control of the transmitter.

In a preferred embodiment, the third counter value is set as a function of the received power control command bits, the method comprising: (a) adding a second counter value to the third counter value; And (b) converting the sum of the second counter value and the third counter value into an analog voltage for gain control of a spread spectrum transmitter amplifier.

Each of the converting steps preferably includes a preliminary step of applying amplifier slope correction to the first and third counter values before these values are converted to analog voltages.

Thus, the teachings of the present invention provide an AGC signal that reacts quickly to changes in the received signal in either direction (increase or decrease signal strength). Moreover, the receiver gain is varied by the first increment, while the transmitter gain is varied by the second increment. In a presently preferred embodiment of the invention the receiver gain is varied in increments of 1 dB, while the transmitter gain is varied in increments of 0.125 dB.

These and other features of the present invention will become more apparent when described in conjunction with the accompanying drawings in the following detailed description of the invention.

1 is a schematic block diagram of a wireless telephone constructed and operated in accordance with the present invention.

FIG. 2 is a block diagram illustrating in more detail the digital automatic gain control circuit and transmitter power control circuit of FIG.

FIG. 3 is a schematic diagram illustrating a lookup circuit (34a in FIG. 2) in ROM for determining received signal power.

FIG. 4 shows the block 38a of FIG. 2 in more detail.

5 is a block diagram of a preferred embodiment for implementing the blocks 38a and 38b of FIG.

FIG. 6 is a graph showing the effect of the scaling block shown in FIG. 5.

Reference is made to Fig. 1 which shows a presently preferred embodiment of a spread spectrum CDMA radiotelephone 10 according to the present invention. As will be apparent, any of the blocks of the radiotelephone 10 may be implemented as discrete circuit components, or may be implemented as software routines executed by a suitable digital data processor such as a high speed signal processor. Alternatively, a combination of circuit components and software routines can be used. By doing so, the following description is not intended to limit the application of the present invention to any one particular technical embodiment.

In a preferred embodiment of the present invention, the radiotelephone 10 operates according to the mobile station-base station compatibility standard TIA / EIA / IS-95 (1993.7.) For a dual mode wideband spread spectrum cellular system, which is a TIA / EIA interim standard. However, compatibility according to this particular interim standard will not be considered a practical limitation of the present invention.

The radiotelephone 10 includes an antenna 12 for receiving RF signals from a cell site, later called a base station (not shown), and for transmitting the RF signals to the base station. When operating in digital (CDMA) mode, RF signals are phase modulated to convey voice and signaling information. The transmitter 12 is connected with a gain control receiver 14 and a gain control transmitter 16 for receiving and transmitting phase modulated RF signals, respectively. The frequency synthesizer 18 provides the required frequencies to the receiver and transmitter under the control of the controller 20. The controller 20 interfaces with the speaker 22a and the microphone 22b via a codec 22 and is also composed of a low speed MCU for interfacing with the keyboard and the display 24. In general, the MCU is responsible for the overall control and operation of the radiotelephone 10. The controller 20 is also preferably comprised of a high speed digital signal processor (DSP) suitable for real time processing of received and transmitted signals.

The received RF signals are converted to baseband at the receiver and applied to a phase demodulator 26 which derives in-phase (I) and quadrature (Q) signals from the received signal. The I and Q signals are converted into digital representations by suitable A / D converters (26a and 26b in FIG. 2) and applied to the three fingers F1-F3 demodulator 30. Each of the fingers includes a local PN generator. The output of the demodulator 28 is applied to the combiner 30, and the combiner 30 outputs a signal to the controller 20 via the deinterleaver and the decoder 32. The digital signal input to the controller 20 represents voice samples or signaling information. Subsequent processing of this signal by the controller 20 is closely related to the understanding of the present invention except that it should be noted that the signaling information will include transmitter power control bits transmitted from the base station to the radiotelephone 10. It is not explained any more because it is not.

The I and Q signals output from the IQ demodulator 26 are also applied to the receiver digital AGC block 34 according to the present invention, which processes these signals in a manner described below, and outputs the output signal. Calculate with an amplifier slope corrector block 36. One output of the slope corrector block 36 is an RX GAIN signal that is used to automatically control the gain of the receiver 14.

The output of the receiver digital AGC block 34 is also applied to the TX open loop power control block 38. TX closed loop control block 40 inputs the received transmitter power control bits from controller 20. The adder 42 adds the output of the TX open loop control block 38 to the output of the TX closed loop control block 40 and generates a sum signal, which is applied to the slope corrector 36, which From to the TX limiter block 44. The output of the TX limiter block 44 is a TX GAIN signal applied to the transmitter 16 to control the output power of the transmitter 16.

Input to transmitter 16 (vocoded speech and / or signaling information) is via convolutional encoder, interleaver, Walsh modulator, PN modulator, and IQ modulator, shown entirely at block 46. It is derived from the controller 20.

Before describing in detail the configuration and operation of the receiver digital AGC block 34, the slope compensator 36, and the open and closed loop transmitter blocks 38, 40, 42 and 44, firstly the optimal received from the base station with all channels. It is noted that the signal sampled with will have a dynamic range of approximately 64/1 or 18 dB. Additionally, fast fades can have a dynamic range of approximately +6 dB to -34 dB. If the receiver AGC cannot fully track fast fades, then the signal is likely clipped by the receiver's A / D converter, or the signal is too small (A / D underflow) for the A / D converter. However, clipping is generally symmetrical and can be allowed to some extent. By doing so, the receiver AGC step response time constant of 0.5 ms to 2 ms is considered appropriate to properly track fast fading for the receiver AGC, and to prevent clipping and A / D converter overflow and underflow.

Consequently, the present invention also provides a high tracking rate capability for the receiver AGC function when signal amplification or attenuation is required.

Reference is now made to FIG. 2 for a detailed description of the receiver AGC function and transmitter power control function that were briefly described above in the description of FIG. 1. In FIG. 2, the partial components of receiver AGC 34 are denoted as 34a-34e and the partial components of TX open loop power control 38 are denoted as 38a-38c.

Based on the digital outputs (A / Ds 26a and 26b) of the IQ phase demodulator 26, the power of the I sample and the Q sample is calculated at least once per chip by the block 34a, preferably for example in the ROM table. (34b) Calculated twice per chip by lookup. The calculated powers are integrated over a predetermined period corresponding to, for example, one symbol (64 chips). The integrated output signal is denoted as Rx_AGC or here RxAGC.

When sampled once per chip, one suitable technique for determining the received signal power based on ROM lookup is as follows. See also FIG. 3.

The outputs of the 6 bit A / Ds 26a and 26b are time division multiplexed and used as addresses in the ROM 34b. Thus, the address space of the ROM is 2 ⁶ = 64. The content of ROM 34b at each address is the square of that address, i.e., if the output of one of the A / Ds is " 25 ", then the ROM content at address 25 is 625. The largest possible amount of output of one of the A / Ds is "31" whose squared value is 961. Similarly, the largest possible negative output of one of the A / Ds is "-32" whose squared value is 1024. However, this number is truncated to 1023. As a result, the data output width requirement of the ROM 34b is limited to 10 bits, so the total ROM size is 64 x 10 bits.

The output of the ROM 34b is connected to an integrator consisting of an adder 35a and a register 35b. The register 35b is clocked by a 2X chip clock, and the 2X chip clock clocks the counter 35d, and the counter 35d counts 128 samples. The clock signal also uses multiplexer (MUX) 35e to select I A / D and Q A / D 26a and 26b, respectively. As a result, the A / D outputs are time division multiplexed to the address inputs of ROM 34b which output in response to the square of the A / D output value. The ROM 34b output is then added to the value stored in register 35b, and the addition result is then stored back in register 35b. Every 64th chip, the second register 35c is clocked to store the output of the adder 35a, while at the same time the first register 35b is cleared. As a result, the second register 35c contains a value corresponding to 64 consecutive chips or an energy of one symbol.

Referring back to FIG. 2, according to a feature of the present invention, in order to obtain the same rate of change when increasing amplification and decreasing amplification, the power of the input signal RX_AGC is not directly used, Logs (any log base) are used.

More specifically, in a preferred embodiment of the present invention, the secondary log of power is calculated using priority encoder 34c, where the secondary log is taken to be the position of the most significant set bit. For example, with 6-bit A / D converters 26a and 26b, the log is scaled such that the power of 0 <= power <2 is zero, the power of 2 <= power <4 is 1, and so on. As a result, each unit of logarithmic value corresponds to 3 dB power. Therefore, the average input amplitude 4 (during 6-bit A / D converter interval of 0-32) is 64x2x4 ² corresponding to 11 log values. Yield a linear power of 2048.

Moreover, two or more bits for the logarithm are calculated by adding two bits to the right of the most significant set bits of the linear power value. Although this is a linear approximation of the logarithmic function, the error turns out to be meaningless. Thus, the resolution of the power measurement is approximately 0.75 dB.

The desired log of power (4x11 = 44 in the above example) is also subtracted from the power calculated at block 34c, and the difference value (error signal e ₁ ) is input to the single-pole low pass filter 34d, whose time constant is Determine the speed of the overall digital AGC circuit. By way of example only, a filter feedback ratio of 1- (31/32) yields a time constant of approximately 1.6 ms.

The output of filter 34d is input to threshold detector and counter circuit 34e, where the filtered output is monitored once per symbol as its output is compared to first threshold THRESH ₁ . If the filtered output exceeds the first threshold, the counter CNTR is incremented or decremented according to the sign of the exceeded threshold. At the same time, the filter accumulator is reset. For theoretically correct operation, the filter accumulator must be set to a threshold of opposite polarity. That is, if a positive threshold is exceeded, the counter counts up and the filter register is set to a negative threshold. However, this allows the counter to immediately count in the opposite direction. Therefore, it is preferable to use some degree of hysteresis. In a preferred embodiment, +/- 0.16667 is used as the threshold and +/- 0.125 is used as the reset value. The filter accumulator can be reset to zero to provide more hysteresis. The output of the counter is eventually delivered to a D / A converter contained within the slope corrector block 36, which outputs a signal Rx GAIN to control the receiver amplifiers.

The threshold THRESH ₁ is preferably set to +/- 0.33333 (1 dB) for an AGC step size of 2 dB in that the unit change in the input and output of the filter 34d corresponds to a 3 dB change in power. Or +/- 0.166667 (0.5 dB) for an AGC step size of 1 dB. That is, the value of THRESH ₁ is a function of the desired receiver AGC step size.

The receiver AGC signal reaches a stable value when negative values of the log occur as often as positive values at the input to the low pass filter 34d. The optimal steady state of AGC occurs when there is a signal headroom of 6-12 dB in the A / D converters 26a and 26b. Since the number of bits is limited, the steady state headroom can be determined empirically best for a given application.

There are several possible techniques for changing the signal headroom in the A / D converter, but the presently preferred technique changes the expected value of the log of the input power. It should be noted here that the parameters for transmitter AGC determination should be changed at the same time, as described later.

The transmitter digital AGC function 38 has a step counter 38a similar to the receiver AGC step counter 34e. The transmitter AGC step counter value is subtracted from the step counter value of the receiver AGC to form a second error signal e ₂ . The error signal e ₂ is low pass filtered in the monopole low pass filter 38b, and its time constant is selected such that the total time constant for the transmitter AGC function is approximately 30 ms. A filter feedback factor of 1- (1023/1024) gives this time constant.

The step size of the transmitter AGC should preferably not be greater than 0.125 dB. By doing so, assuming a 1 dB step in the receiver AGC signal Rx_AGC, the Rx AGC counter value output from 34e is shifted left by three before the difference is determined.

This technique, by itself, will yield an accuracy of 1 dB in the transmitter AGC signal. In order to achieve better accuracy, the power integrated over one symbol Rx_AGC is used instead. The precomputed expected value of the power integrated over one symbol is subtracted from the actual integrated power value, and the result is filtered in the low pass filter 38b described above. As before, this means that the log function will approximate a linear function. Following the example presented above, if the desired log value is 44, the linear average power of the signal will have a deviation of 1 dB, and thus have a value between 2048 and 2578, and eventually, the desired linear power value is (2048 + 2560) / 2 = 2313 is set. This input is shifted to the right by 6 in that the input to the filter 38b of 1 dB corresponds to a value of 8 ((10 ^0.1-1 ) x2048 = 530 512, 512/8 = 64 => 6 right Shift).

If the signal headroom in the receiver A / D converters 26a and 26b is changed by changing the expected value of the log of the received power, the expected value of the aforementioned linear power is also changed. This is preferably achieved by appropriate additional shifting of the linear power value. Table 1 below lists the appropriate values for this additional shift given the desired receiver power log.

 Average received amplitude  Received linear power     Power log Additional shift of linear power for Tx AGC 11.422.845.6811.21622.432 1282565121024204840968192163843276865536131072 2832364044 (11 * 4) 485256606468 -4-3-2-10123456

More specifically, block 38a of FIG. 2 calculates the difference between the Rx counter value CNTR at block 34e and the Tx counter value CNTR at block 38c. This difference is then lowpass filtered and compared with the threshold. If the threshold is exceeded, the counter of block 38c counts up or counts down, the new value is passed back to block 38a and compared to the Rx counter value from block 34e again at block 38a. do. This process will continue until the Rx counter value and the Tx counter value are the same.

Block 38a also calculates the difference between the received linear power from block 34a and a predetermined fixed value REF. This difference is also passed to the low pass filter 38b. As a result, there are two input values in filter 38b for each processing iteration.

4 in this regard, the function of the receiver chain (blocks 26a-b and 34a-e) is to maintain an average input amplitude constant for the A / D converters 26a and 26b. As an example, assume that the desired absolute amplitude corresponds to an A / D output of 8 (in the A / D absolute range of 0-32). After integration, the measured power will be 8 ² x128 = 8192. Therefore, this value is a predetermined fixed reference value (linear power reference value).

According to a preferred embodiment of the present invention, one step at the output of the counter 34e corresponds to a gain change of 1 dB and one step at the output of the counter 38c corresponds to 0.125 dB. Therefore, the output of the counter 34e must be multiplied by 8 before the subtraction of the TxAGC counter value by the block 39d (shifted left by 3 in the block 39a). The switches 39e and 39f function as multiplexers that connect the TxAGC counter value and the shifted RxAGC counter values to the subtractor 39d, or connect the shifted Rx linear power value and the shifted linear power reference value to the subtractor 39d. do.

If we ignore the linear power REF and RxAGC linear outputs for a while, the Tx open loop will be balanced if eight times the value of the RxAGC counter 34e is equal to the value of the TxAGC counter 38c. Although the Tx counter may have any value in the transition period, in any steady state its output has a value of n × 8, ie the Tx open loop has a steady state result of 8 × 0.125 = 1 dB. However, this resolution is not sufficient to meet the requirements of the IS-95 specification.

In order to improve the resolution, the present invention uses the difference between the linear power value and its corresponding reference value. The power here is expressed linearly rather than in dB, so that a linear approximation of the logarithm function is first formed. Since the intention is to improve the resolution, the counter difference is formed to handle a large gain difference and limit the difference between the linear power value and the reference value to 3 dB.

Now 3 dB corresponds to a linear value of 2, 2 dB corresponds to 1.58 1.5, 1 dB corresponds to 1.2589 1.25, 0.5 dB corresponds to 1.122 1.125, 0.25 dB corresponds to 1.0593 1.0625, 0.125 dB If we recognize that n corresponds to 1.0292 1.03125 and so on, we can see that as long as the difference is less than 3 dB, twice the dB value corresponds to twice the fraction of the linear value.

If we define that 0 dB corresponds to 1 x 8192, 0.125 dB is 1.03125 x 8192 = 8448. Therefore, according to the linear approximation value, a gain change of 0.125 dB corresponds to a change of 256 in the linear power value, a gain change of 0.25 dB corresponds to a change of 512, and the like.

The unit step change in the TxAGC counter 38c has been described above as corresponding to a gain change of 0.125 dB. Therefore, since 0.125 dB in the linear difference corresponds to 256, the linear difference is divided by 256 before being input into the filter 38b (shifted to the right by 8 in the block 39b).

Now assume that the RxAGC and TxAGC counters have a value of 24 and a value of 192 (8x24), respectively. In this case the average input power varies from the desired value of 8192 to 8448. That is, it has a gain change of 0.125 dB. The receiver counter 34e will not respond to this gain change because the change is less than 1 dB. However, the linear difference input to filter 38b would be (8192-8448) / 256 = -1. After a predetermined time period, depending on the time constant of the filter 38b, the TxAGC counter 38c will count down by 191 step by step. Thus, the difference between the counters would be 8 x 24-191 = 1. The two inputs to filter 38b now cancel each other out, but the transmitter gain is reduced by 0.125 dB. That is, the circuit increases the resolution of TxAGC to 0.125 dB and meets the CDMA specification.

It should be noted that the linear approximation does not work equally well for negative gain changes since -1 dB corresponds to 0.794 but should be 0.741, -2 dB corresponds to 0.630 but must be 0.415, and so on. That is, the linear approximation works best for differences less than -2 dB. Also, as previously described, the true reference value should be (10 ^0.1 x 8192 + 8192) / 2 = 9252 rather than 8192. However, even if the latter is actually used for subtraction, the former is used for scaling the approximation (dividing to 256). The exact scaling value is 10313/8192 x 256 = 322, but this results in a more cumbersome hardware implementation. This results in a small error in the approximation, but is partially offset by the fact that larger errors may exist for negative gain changes than for positive gain changes.

In summary, it is desirable to provide two inputs to the filter 38b so that the relatively large step size of RxAGC can cancel out fast changes in the input signal level. TxAGC, on the other hand, is required to be slower and more accurate. If TxAGC would only follow RxAGC, the resolution of TxAGC would not be suitable. However, by introducing a linear power value and its equally shifted linear power reference value (block 39c) from block 34a, it is possible to increase the accuracy of TxAGC to the required level.

While the above description has served to illustrate the operation of the present invention, it should be noted that there are many possible implementations. For example, FIG. 5 illustrates a presently preferred implementation that enables substantial hardware savings as the blocks 38a and 38b are integrated.

The embodiment of FIG. 5 includes a 5: 1 multiplexer 50, a 1 / x scaling circuit 52 (eg, x = 1024), an adder / subtracter 54, and a filter (D-flop) 56. . Register 58 may be used to store the output of filter 56. State machine 60 controls the overall operation and timing of these components. The overall transfer function of the circuit shown in FIG. 5 is similar to a monopole IIR filter. The value of x can be made programmable. In general, the value of x affects the response time of the circuit (and thus the transmitter power level) to a step change in the input reception level, as indicated in the illustrative graph of FIG. 6.

Referring again to FIG. 2, the output of the transmitter AGC filter 38b forms an overall open loop power estimate. As described, this estimate is applied to comparator 38c, which comparator 38c detects whether the step threshold is exceeded by comparison with a second threshold THRESH ₂ , in which case an internal TX counter Is increased or decreased depending on the sign of the exceeded threshold. Since one unit input and output from the filter 38b corresponds to 0.125 dB, and this value is also the step size of TxAGC, the dipole threshold THRESH ₂ is preferably in the range of +/- 0.5.

The second counter 40 is used to count closed loop power steps output from the controller 22, and the output of the counter 40 is added to the output of the counter of the comparator 38c using the adder 42.

The transmitter AGC step size of 0.5 dB has been shown to meet the requirements of the CDMA interim specification, assuming ideal analog hardware. However, according to the same theory as for receiver AGC, using a 10-bit D / A converter 44a, a step size of 0.125 dB is desirable.

s의 수신내에서 실행되도록 요구되기 때문이다. 그러나, 다른 변환 레이트들은 본 발명의 교시의 영역내에 있다.The current preferred conversion rate for A / Ds 26a and 26b is 9.6 kHZ, which means that the position of the closed loop power control bits is variable and 500

This is because it is required to run within the reception of s. However, other conversion rates are within the scope of the teachings of the present invention.

Tx limiter block 44 operates in a similar manner to comparators and switches. The input to block 44 is the amplification value appropriately determined by the Tx AGC algorithm. This amplification value is compared with a preset value that represents the largest possible amplification value allowed (by standard and / or by design). If the amplification value exceeds the preset value, the preset value will be output through the DAC rather than the calculated amplification value. In this way the output power of the transmitter of the terminal is limited to a predetermined maximum value. Moreover, this maximum output power level is adaptive. Thus, the preset value is replaced by the value from the next counter CNCR. The input of block 44 is compared with the counter value. If the input exceeds the counter value, the counter value is output. At the same time the counter is enabled to count up or count down one step. The direction of counting is determined by the 1-bit signal from the RF section, where the detected absolute output power level is compared if it exceeds the maximum allowable output level. In this way, the Tx AGC decision depends on the actual absolute output power level, and its adaptability ensures that the maximum output power level is fixed despite the difference in temperature and component tolerances.

등의 "적응형 송신기 이득 제어를 갖는 확산 스펙트럼 무선전화기"에 기재되어 있다(대리인의 서류 번호 309-934809-NA).Details of the operation of the Tx limiter 44 can be found in the jointly assigned US patent application Ser. No. 08 / 303,619, filed September 9, 1994, Lars

And "spread spectrum radiotelephones with adaptive transmitter gain control" (Document No. 309-934809-NA of the agent).

Receiver and transmitter power amplifiers typically require slope correction to be applied to their respective gain adjustment signals. For this purpose, the unsigned output from the step counter 34e and the sum of the step counters 38c and 40 are transformed into two's complements by inverting the sign bits. Each two's complement is multiplied by a seven-bit number in block 36 to correct the amplification slope.

Assuming a 50% maximum error in the power amplifier slopes, the value of the 7-bit number should be 0.5-1.5 => -2 to 2 since the multiplier must be able to perform two's complement multiplication. After all, the LSB corresponds to 1/32 and the error after correction is at most 1/64 or 1.56%.

If S curve transmitter correction is desired, the dynamic range is divided into a plurality of sub-ranges (e.g., 4, 8, 16, etc.), each sub range having its own correction coefficient. Two (or three, four, etc.) most significant bits are used to select the correct correction coefficient subrange.

Thus, a presently preferred embodiment of the present invention has been described. However, this embodiment may make many variations and such variations will still be within the scope of the teachings of the present invention. By way of example, other values and ranges of values may be used for the various thresholds used to increment or decrement counters in blocks 34e and 38c. Moreover, by way of example, lookup table 34b may be implemented in any suitable form of memory element, such as RAM, which is loaded by controller 20 with suitable values. In addition, any reference value for a counter or counter value may also be read to include a register or register value. By way of example, storage can be increased and decreased under software control, and thus can be functionally equivalent to a counter such as a decimal or binary counter element or circuit.

Moreover, the teachings of the present invention can generally be used for RF transceivers that include time division multiple access type transceivers, and are not limited to spread spectrum and / or CDMA transceiver types. In addition, it should be realized that power can be integrated over a suitable period of time and need not be integrated over only a period corresponding to one symbol.

Thus, while the invention has been particularly shown and described with respect to its preferred embodiments, it will be apparent to those skilled in the art that changes may be made in form and detail without departing from the scope and spirit of the invention.

Claims (26)

Integrating the power of the received and sampled signal; Calculating a log of received and integrated power; Subtracting a predetermined reference value from a log of power received and integrated to generate a first error signal; Filtering the first error signal; Comparing the filtered first error signal with a first predetermined threshold value; Increasing or decreasing the first counter value as a function of the result of the comparing step and resetting the filter accumulator; And And converting the first counter value into an analog voltage for controlling the gain of the receiver. The method of claim 1, wherein the log is a secondary log of power, and the calculating comprises: Inputting a digital word representing the value of the received and integrated power to the priority encoder means to determine the position of the most significant set bit of the digital word; And And using the determined position as a secondary log. The method of claim 1 wherein the log is a secondary log of power, The calculating step, Inputting a digital word representing the value of the received and integrated power to the priority encoder means to determine the position of the most significant set bit of the digital word; Extracting one or more bits adjacent to the determined most significant set bit; Linking the extracted bit or bits to a binary value representing a determined position of the most significant set bit; And And using the resulting concatenated bits as an approximation of the secondary logarithmic. The method of claim 1, Generating a second counter value; Subtracting the second counter value from the first counter value to form a second error signal; Filtering the second error signal; Comparing the filtered second error signal with a predetermined threshold range; Increasing or decreasing the second counter value as a function of the result of comparing the filtered second error signal and resetting the filter accumulator; And And converting at least a second counter value into an analog voltage for adjusting the gain of the transmitter. The method of claim 1, Generating a second counter value; Subtracting the second counter value from the first counter value to form a second error signal; Filtering the second error signal; Comparing the filtered second error signal with a second predetermined threshold value; Increasing or decreasing the second counter value as a function of the result of comparing the filtered second error signal and resetting the filter accumulator; Setting a third counter value as a function of received power control command bits; Adding the second counter value to the third counter value to form a sum of the second counter value and the third counter value; And And converting the sum of the second counter value and the third counter value into an analog voltage for controlling the gain of the transmitter. The method of claim 5, wherein each of the converting steps, And a preliminary step of applying the amplifier slope correction to the first counter value and the third counter value. Means for integrating power of the received and sampled signal; Means for calculating a log of received and integrated power; Means for subtracting a predetermined reference value from a log of power to generate a first error signal; Means for filtering the first error signal; Means for comparing the filtered first error signal with a predetermined first threshold; Means for increasing or decreasing the first counter value and resetting the filter accumulator as a function of the result of the comparing step; And And means for converting the first counter value into an analog voltage for controlling the gain of the receiver. 8. The method of claim 7, wherein the log is a secondary log of power, Means for calculating, Priority encoder means for inputting a digital word representing a value of the received and integrated power to determine the position of the most significant set bit of the digital word, wherein the determined position is represented as a secondary log. Gain control signal generator for transceivers. 8. The method of claim 7, wherein the log is a secondary log of power, Means for calculating, Priority encoder means for inputting a digital word representing a value of the received and integrated power to determine the position of the most significant set bit of the digital word, wherein the determined position is indicated as a secondary log; Means for extracting one or more bits adjacent to the most significant set bit; And Means for concatenating the extracted bit or bits to the determined most significant set bit, wherein the resulting concatenated bits are represented as an approximation of the secondary logarithm. The method of claim 7, wherein Means for generating a second counter value; Means for subtracting the second counter value from the first counter value to form a second error signal; Means for filtering the second error signal; Means for comparing the filtered second error signal with a predetermined second threshold; Means for increasing or decreasing the second counter value and resetting the filter accumulator as a function of the result of the means for comparing the filtered second error signal; And And means for converting at least a second counter value into an analog voltage for controlling the gain of the transmitter. The method of claim 7, wherein Means for generating a second counter value; Means for subtracting the second counter value from the first counter value to form a second error signal; Means for filtering the second error signal; Means for comparing the filtered second error signal with a predetermined second threshold; Means for increasing or decreasing the second counter value and resetting the filter accumulator as a function of the result of the means for comparing the filtered second error signal; Means for setting a third counter value as a function of received power control command bits; Means for adding the second counter value to the third counter value to form a sum of the second counter value and the third counter value; And And means for converting the sum of the second counter value and the third counter value into an analog voltage for controlling the gain of the transmitter. The method of claim 11, wherein each of the means for converting comprises: And means for applying an amplifier slope correction to the first counter value and the third counter value. Receiving a spread spectrum RF signal and amplifying the received signal with at least one receiver amplifier; Demodulating the received RF signal to derive the in-phase I signal and the quadrature Q signal; Iteratively squares the magnitudes of the I and Q signals and integrates the squared magnitudes over a predetermined period to derive an indication of the power of the received signal over the predetermined period; Obtaining a log of the derived power indication; Obtaining a first error signal indicating a difference between a log of power indication and a predetermined power; Filtering the first error signal; Comparing the filtered first error signal with a first dipole threshold signal, increasing or decreasing the first counter value in accordance with the comparison and resetting the filter accumulator; And Generating a gain control signal for at least one receiver amplifier in accordance with a first counter value. The method of claim 13, wherein squaring comprises: Converting each of the I and Q signals into a digital representation; Alternately applying digital representations to address inputs of a memory element; And And for each application of one of the digital representations, outputting a value from the memory element corresponding to the square of the digital representation. The method of claim 13, Generating a second counter value; Subtracting the second counter value from the first counter value to form a second error signal; Filtering the second error signal; Comparing the filtered second error signal with a second dipole threshold signal, increasing or decreasing a second counter value and resetting the filter accumulator according to the comparison to form an open loop transmitter power control value; Combining the open loop power control value with the closed loop power control value to form a combined power control value; And Generating a gain control signal for at least one transmitter amplifier in accordance with the combined power control value. The method of claim 13, Generating a second counter value; Subtracting the second counter value from the first counter value to form a second error signal, and subtracting the derived display value of the power of the received signal over a predetermined period from the reference value; Filtering the second error signal; Comparing the filtered second error signal with a second dipole threshold signal, increasing or decreasing a second counter value and resetting the filter accumulator according to the comparison to form an open loop transmitter power control value; Combining the open loop power control value with the closed loop power control value to form a combined power control value; And Generating a gain control signal for at least one transmitter amplifier in accordance with the combined power control value. A transmitter for transmitting a spread spectrum RF signal through at least one transmitter amplifier; A receiver for receiving a spread spectrum RF signal and amplifying the received signal with at least one receiver amplifier; A demodulator for demodulating received RF signals to derive in-phase I and quadrature Q signals; Means for deriving an derived power indication of a received signal over a predetermined period from the I and Q signals; Means for obtaining a first error signal indicating a difference between the power indication and the predetermined power; A first filter for filtering the first error signal; Means for comparing the filtered first error signal with a first threshold signal, increasing or decreasing the first value and resetting the filter accumulator in accordance with the comparison; Means for generating a gain control signal for at least one receiver amplifier in accordance with the first value; Means for generating a second value; Means for subtracting the second value from the first value and subtracting the derived power indication of the received signal over a period of time from the reference value to form a second error signal; A second filter for filtering the second error signal; Means for comparing the filtered second error signal with a second threshold signal, increasing or decreasing the second value according to the comparison and resetting the filter accumulator to form an open loop transmitter power control value; Means for combining the open loop power control value with the closed loop power control value to form a combined power control value; And Means for generating a gain control signal for said at least one transmitter amplifier in accordance with a combined power control value. The method of claim 17, wherein the means for deriving, Means for iteratively squaring the magnitudes of the I and Q signals; And Means for integrating squared magnitudes over a predetermined period to derive a power indication of the received signal over the predetermined period. 18. The method of claim 17, wherein the step size of the first counter value is equal to a value expressed in a predetermined number of dB, and the derived indication of the power of the signal received over a predetermined period is a signal received over a predetermined period. A spread spectrum transceiver, characterized in that it is a linear approximation of the power of. 20. The spread spectrum of claim 19, wherein the open loop transmitter power control value is controlled in accordance with a solution of less than a predetermined number of dBs due to the difference between the derived power indication and the reference value of the signal received over a predetermined period. Transceiver. 21. The spread spectrum transceiver of claim 20, wherein the predetermined number of dBs is one. 18. The spread spectrum transceiver of claim 17, wherein the first threshold is a function of the desired step size in dB of the transmitter gain control signal. 18. The spread spectrum transceiver of claim 17, wherein the second threshold is a function of the desired step size in dB of the transmitter gain control signal. 18. The spread spectrum transceiver of claim 17, wherein the first threshold in dB is approximately half of the desired step size in dB of the receiver gain control signal. 18. The transmitter gain control signal of claim 17, wherein the first threshold value is a function of the desired step size in dB of the receiver gain control signal, and the second threshold value is a function of the desired step size in dB of the transmitter gain control signal. The desired step size in dB of the spread spectrum transceiver, characterized in that less than the desired step size in dB of the receiver gain control signal. 18. The spread spectrum transceiver of claim 17, wherein the predetermined period is a symbol period.

Images