KR100377402B1 - Address-While-Display driving method using plural frame memories for plasma display panel - Google Patents

Abstract

The present invention is a method of driving a plasma display panel having a three-electrode surface discharge structure by an in-display method. According to this method, new frame data is written to the remaining one frame-memory while two frame data recorded in the two frame-memory are read out and processed into single frame data corresponding to the in-display-address scheme. Since the operation is continuously performed in units of frames, data for address discharge may be continuously output. Accordingly, the display quality of the moving image can be improved also by the in-display driving method.

Description

Address-While-Display driving method using plural frame memories for plasma display panel}

The present invention relates to a method of driving an address-while-display of a plasma display panel, and more particularly, to a method of driving a plasma display panel having a three-electrode surface discharge structure by an in-display method. It is about.

1 shows a structure of a conventional three-electrode surface discharge plasma display panel. FIG. 2 shows an example of one display cell of the panel of FIG. 1. 1 and 2, the conventional surface discharge plasma between the front and rear glass substrate of the display panel 1 (10, 13), the address electrode lines (A _1, A _2, ..., Am _{- 1} , Am, dielectric layers 11 and 15, Y electrode lines Y ₁ , ..., Yn, X electrode lines X ₁ , ..., Xn, phosphor 16, barrier rib 17 ) And a magnesium monoxide (MgO) layer 12 as a protective layer.

The address electrode lines A ₁ , A ₂ ,..., Am ₋₁ , Am are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is applied over the entire surface in front of the address electrode lines A ₁ , ..., Am. In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A ₁ ,..., Am. These partitions 17 function to partition the discharge area of each display cell and prevent optical cross talk between each display cell. The phosphor 16 is applied between the partition walls 17.

The X electrode lines (X ₁ , ..., Xn) and the Y electrode lines (Y ₁ , ..., Yn) are front glass substrates so as to be orthogonal to the address electrode lines (A ₁ , ..., Am). 10 is formed in a constant pattern on the back. Each intersection sets a corresponding display cell. Each X electrode line (X ₁ , ..., Xn) and each Y electrode line (Y ₁ , ..., Yn) is a transparent electrode line of transparent conductive material such as indium tin oxide (ITO) or the like (Xna of FIG. 2). , Yna) and metal electrode lines (Xnb and Ynb in FIG. 2) for increasing conductivity are formed. The front dielectric layer 11 is formed by applying the entire surface to the rear of the X electrode lines X ₁ ,..., Xn and the Y electrode lines Y ₁ ,..., Yn. A protective layer 12 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

FIG. 3 illustrates a conventional address-display separation driving method for the Y electrode lines of the plasma display panel of FIG. 1. Referring to FIG. 3, a unit frame is divided into eight subfields SF1, ..., SF8 to realize time division gray scale display. Further, each subfield SF1, ..., SF8 is divided into address periods A1, ..., A8 and sustain discharge periods S1, ..., S8.

In each address period A1, ..., A8, address electrode lines (Fig. , , ..., , At the same time the display data signal is applied to each Y electrode line ( , ..., Are sequentially applied. Accordingly, when a high level display data signal is applied while the scan pulse is applied, wall charges are formed by the address discharge in the corresponding discharge cell, and wall charges are not formed in the discharge cell that is not.

In each sustain discharge period S1, ..., S8, all Y electrode lines ( , ..., ) And all X electrode lines ( , ..., The sustain discharge pulse is alternately applied to generate the display discharge in the discharge cells in which the wall charges are formed in the corresponding address periods A1, ..., A6. Therefore, the luminance of the plasma display panel is proportional to the length of the sustain discharge periods S1, ..., S8 occupied in the unit frame. The lengths of the sustain discharge cycles S1, ..., S8 occupy a unit frame are 255T (T is the unit time). Therefore, it can be displayed in 256 gray scales, even if it is not displayed once in a unit frame.

Here, the time 1T corresponding to 2 sup 0 in the sustain discharge period S1 of the first subfield SF1 corresponds to 2 sup 1 in the sustain discharge period S2 of the second subfield SF2. The time 2T corresponds to 2 sup 2 in the sustain discharge period S3 of the third subfield SF3, and 2 sup in the sustain discharge period S4 of the fourth subfield SF4. The time 8T corresponding to 3 is the sustain discharge period S5 of the fifth subfield SF5. The time 16T corresponding to 2 sup 4 is the sustain discharge period S6 of the sixth subfield SF6. ) Is the time 32T corresponding to 2 sup 5, the sustain discharge period S7 of the seventh subfield SF7 is the time 64T corresponding to 2 sup 6, and the time of the eighth subfield SF8. In the sustain discharge period S8, a time 128T corresponding to 2 sup 7 is set.

Accordingly, when the subfield to be displayed among the eight subfields is appropriately selected, it can be seen that display of 256 gray levels can be performed including all zero (zero) gray levels that are not displayed in any of the subfields.

According to the above-described address-display separation driving method, since the time domains of the subfields SF1, ..., SF8 are separated in the unit frame, the address period and the address period in each of the subfields SF1, ..., SF8 are separated. The time domains of the display periods are also separated from each other. Therefore, in the address period, after each XY electrode line pair has been addressed, it has to wait until all other XY electrode line pairs are addressed. As a result, the time period occupied by the address period for each subfield becomes longer and the display period becomes relatively short. Therefore, the luminance of light emitted from the plasma display panel is relatively low. In order to remedy this problem, a known method is an Address While Display driving method as shown in FIG.

FIG. 4 illustrates a typical Address-While-Display driving method for Y electrode lines of the plasma display panel of FIG. 1. Referring to FIG. 4, a unit frame is divided into _eight sub-fields SF ₁ , SF ₈ for time division gray scale display. Here, each unit sub-field overlaps each other based on the driven Y electrode lines Y ₁ ,..., Y n to form a unit frame. Therefore, since all sub-fields SF ₁ ,..., SF ₈ are present at every time point, an address time slot is set between each display discharge pulse for performing each address step.

Reset, address and display discharge steps are performed in each sub-field, and the time allocated to each sub-field is determined by the display discharge time corresponding to the gray scale. For example, in the case of displaying 256 gray levels in frame units as 8-bit image data, if a unit frame (typically 1/60 second) consists of 256 units of time, driving is performed according to the image data of the least significant bit (Least Significant Bit). The first sub-field SF ₁ is 1 ( ) Unit time, the second sub-field SF ₂ is 2 ( ) Unit time, the third sub-field SF ₃ is 4 ( ) Unit time, the fourth sub-field SF ₄ is 8 ( ) Unit time, the fifth sub-field SF ₅ is 16 ( ) Unit time, the sixth sub-field SF ₆ is 32 ( ) Unit time, the seventh sub-field SF ₇ is 64 ( ) The eighth sub-field SF ₈ driven according to the unit time and the image data of the most significant bit is 128 ( ) Each has a unit time. That is, since the sum of the unit times allocated to each sub-field is 257 unit time, 255 gray scales can be displayed, and if gray scales without display discharge in any sub-fields are included, 256 gray scales can be displayed.

FIG. 5 illustrates a multiple-address overlapping display driving method, which is a kind of driving method of FIG. 4. The method for driving a composite-address superimposed display as shown in FIG. 5 has been filed in the Republic of Korea and the United States by the present applicant (Korean Patent Publication No. 59,283 in 2000 and US Patent Application No. 09 / 512,874 in 2000).

Referring to Figure 5, the minimum driving period (T ₁₁ + T ₁₂ , T ₂₁ + T ₂₂ , T ₃₁ + T ₃₂ , T ₄₁ + T ₄₂ , T ₅₁ + T ₅₂ , ...) are respectively displayed discharge period, Reset period and address period (T ₁₂ , T ₂₂ , T ₃₂ , T ₄₂ , T ₅₂ ,...). Reference numerals T ₁₂ , T ₂₂ , T ₃₂ , T ₄₂ , T ₅₂ , ... denote periods including the display discharge period and the reset period, respectively. The display discharge pulses 2 and 5 are alternately applied to all the Y and X electrode lines once in the minimum display discharge period, and between the minimum display discharge periods, the minimum reset period and the address period T ₁₂ , T _22. , T ₃₂ , T ₄₂ , T ₅₂ , ...). That is, the minimum reset period and the address period appear in the pause period of sustain discharge.

In the minimum address period, the scan pulse 6 is applied to the Y electrode line corresponding to the four sub-fields and the corresponding display data signal S _A1 .. _m is applied to each address electrode line. In FIG. 5, reference numerals S _Y1 , ..., S _Y8 are driven to the Y electrodes applied to the corresponding Y electrode lines of the first to eighth sub-fields (SF ₁ , ..., SF ₈ of FIG. 4). Indicates signals More specifically, S _Y1 applies a driving signal applied to any one Y electrode line of the first sub-field SF ₁ , and S _Y2 applies any one Y electrode line of the second sub-field SF ₂ . Is a driving signal, S _Y3 is a driving signal applied to any one Y electrode line of the third sub-field SF ₃ , and S _Y4 is applied to any one Y electrode line of the fourth sub-field SF ₄ . The driving signal is applied, S _Y5 is a driving signal applied to any one Y electrode line of the fifth sub-field SF ₅ , S _Y6 is applied to any one Y electrode line of the sixth sub-field SF ₆ a drive signal, S _Y7 is a seventh sub-drive signals applied to any one of the Y-electrode line of the field (SF _7), and S _Y8 is the eighth sub-to any one of the Y-electrode line of the field (SF ₈₎ Each of the driving signals applied is indicated. Reference numerals S _X1 .. ₄ and S _X5 .. ₈ correspond to the drive signals applied to the X electrode line groups corresponding to the Y electrode lines to be scanned, and S _A1 .. _m corresponds to the Y electrode lines to be scanned. Indication data signals, and GND indicates ground voltage.

Each minimum display discharge period alternates the display discharge pulses 2, 5 to the X and Y electrode lines (X ₁ , ..., Xn, and Y ₁ , ..., Yn in FIG. 1). It is a period for causing display discharge to occur in the pixels where wall charges have been formed by applying. Each minimum reset period is a period for applying the reset pulse 3 to the Y electrode lines to be scanned in the subsequent address period to form space charges while removing the remaining wall charges from the previous sub-field. Each minimum address period T ₁₂ , T ₂₂ , T ₃₂ , T ₄₂ , T ₅₂ , ... sequentially applies a scan pulse 6 to the Y electrode lines corresponding to the four sub-fields. At the same time, it is a period for forming wall charges in the pixels to be displayed by applying a corresponding display data signal S _A1 .. _m to each address electrode line A ₁ .

After the reset pulse 3 is applied until the scan pulse 6 is applied, a predetermined rest period is allowed to smoothly distribute the space charges in the corresponding pixel region. In FIG. 5, the times T ₁₂ , T ₂₁ , T ₂₂ and T ₃₁ correspond to the rest periods corresponding to the Y electrode line groups of the first to fourth sub-fields, and T ₂₂ , T ₃₁ , T ₃₂ and T ₄₁ represent Indicates a rest period corresponding to the Y electrode line group of the fifth to eighth sub-fields. The pulses for display discharges 5 applied in each pause period do not cause actual display discharges and allow the space charges to be smoothly distributed in the corresponding pixel region. The display discharge pulses 5 applied in each idle period do not cause an actual display discharge and allow the space charges to be smoothly distributed in the corresponding pixel region. However, the display discharge pulses 2 applied outside the rest period cause the display discharge to occur in the pixels in which the wall charges are formed by the scan pulse 6 and the display data signal S _A1 .. _m .

Four addressing operations are performed in the minimum address period T ₃₂ or T ₄₁ between the last pulses and the first display discharge pulses 2 that follow during the display discharge pulses 5 applied in the idle period. For example, at time T ₃₂ , addressing is performed on corresponding upper Y electrode lines of the first to fourth sub-fields SF ₁ ,..., SF ₄ . Further, at time T ₄₁ , addressing is performed on corresponding lower Y electrode lines of the first to fourth sub-fields SF ₁ ,..., SF ₄ . As mentioned in the description of FIG. 4, since all sub-fields SF ₁ ,..., SF ₈ are present at all time points, the minimum address period for the performance of each address step depends on the number of sub-fields. The corresponding time slots for the address are set.

After the end of the display-discharge pulses 2 and 5 that are simultaneously applied to the Y electrode lines Y ₁ ,..., And Yn, they are simultaneously applied to the X electrode lines X ₁ ,..., Xn. Display discharge pulses 2 and 5 are started. Simultaneously with the Y electrode lines Y ₁ , ..., Y _n after the end of the display-discharge pulses 2, 5 that are simultaneously applied to these X electrode lines X ₁ , ..., Xn. Scan pulses 6 and corresponding display data signals S _A1 .. _m are applied in the minimum address period before the display discharge pulses 2, 5 to be applied are started.

FIG. 6 shows a typical driving device of the plasma display panel 1 of FIG. 1.

Referring to FIG. 6, a typical driving device of the plasma display panel 1 includes an image processor 66, a controller 62, an address driver 63, an X driver 64, and a Y driver 65. The image processing unit 66 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The controller 62 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 66. The address driver 63 processes the address signal S _A among the drive control signals S _A , S _Y , and S _X from the controller 62 to generate a display data signal, and generates the generated display data signal. Applied to the address electrode lines. The X driving unit 64 processes the X driving control signal S _X among the driving control signals S _A , S _Y , and S _X from the control unit 62, and applies the X driving control signal S _X to the X electrode lines. The Y driver 65 processes the Y driving control signal S _Y among the driving control signals S _A , S _Y , and S _X from the controller 62 and applies the Y driving control signal S _Y to the Y electrode lines.

Referring to FIG. 7, the conventional logic controller 62 of the driving apparatus of FIG. 6 includes a clock buffer 75, a synchronization controller 726, a gamma correction unit 71, an error diffusion unit 712, and first-in-first-out (First in First Out). In First-Out Memory 711, Subfield Generator 721, Subfield Matrix 722, Matrix Buffer 723, Memory Interface 724, Frame-Memorys RFM1, ... , BFM2), rearrangement unit 725, power control unit 973, and XY control unit 74.

The clock buffer 75 converts the 26-megahertz (MHz) clock signal CLK26 from the image processor (66 in FIG. 6) into a 40-megahertz (MHz) clock signal CLK40 and outputs the converted signal. The synchronization adjusting unit 726 includes a clock signal CLK40 of 40 mega-hertz (MHz) from the clock buffer 75, an initialization signal RS from the outside, and a horizontal synchronization signal from the image processing unit (66 in FIG. 6). (H _SYNC ) and the vertical sync signal V _SYNC are input. The synchronization adjusting unit 726 outputs the horizontal synchronization signals H _SYNC1 , H _SYNC2 , and H _SYNC3 to which the input horizontal synchronization signal H _SYNC is delayed by a predetermined number of clocks, respectively. V _SYNC ) outputs vertical synchronization signals V _SYNC2 and V _SYNC3 delayed by a predetermined number of clocks, respectively.

The image data R, G, and B input to the gamma correction unit 71 have reverse nonlinear input / output characteristics in order to correct the nonlinear input / output characteristics of the cathode ray tube. Therefore, the gamma correction unit 71 processes the image data R, G, and B of the reverse nonlinear input and output characteristics to have a linear input and output characteristic. The error diffusion unit 712 reduces the data transmission error by using the first-in first-out memory 711 to move the position of the maximum sign bit, which is a boundary bit of the image data R, G, and B. FIG.

The subfield generator 721 converts 8-bit image data R, G, and B into 8-bit image data R, G, and B, respectively, corresponding to the number of subfields. For example, in the case of driving grayscale with 14 subfields in a unit frame, after converting 8-bit image data R, G, and B into 14-bit image data R, G and B, respectively, In order to reduce a data transmission error, 16 bits of image data R, G, and B are output by adding invalid data '0' of a maximum value bit (MSB) and a minimum value bit (Least Significant Bit).

The subfield matrix unit 722 rearranges 16-bit video data R, G, and B into which data of different subfields is simultaneously input, so that data of the same subfield is simultaneously output. The matrix buffer unit 723 processes the 16-bit image data (R, G, B) from the subfield matrix unit 722 and outputs it as the 32-bit image data (R, G, B).

The memory interface 724 temporarily stores the 32-bit image data (R, G, B) from the matrix buffer unit 723 in the corresponding frame-memory (RFM1, ..., BFM2) on a frame basis. The 32-bit image data R, G, and B temporarily stored are output to the rearrangement unit 725 in units of frames. In FIG. 7, reference numeral EN denotes an enable signal generated from the XY controller 94 and input to the memory interface 724 to control the data output of the memory interface 724. Also, the reference numeral S _SYNC is generated from the XY control unit 74 to control data input / output in units of 32-bit slots in the memory interface 724 and the rearrangement unit 725, and thus the memory interface 724 and the rearrangement unit. The slot synchronization signal input to 725 is indicated. The rearrangement unit 725 rearranges and outputs 32-bit image data R, G, and B from the memory interface 724 in accordance with the input format of the address driver (6 in FIG. 6).

Meanwhile, the power controller 73 processes the image data signals R, G, and B input from the error diffusion unit 712 to display the number of all discharge-cells in the plasma display panel 1 in FIG. 6. A load rate, which is a ratio of the number of discharge-cells to be predicted, is predicted in each frame unit, and the discharge recovery control data APC corresponding thereto is input to the XY controller 74. The XY control unit 74 operates in accordance with the discharge recovery control data APC and the built-in drive sequence from the power control unit 73 to output the X drive control signal S _X and the Y drive control signal S _Y. do.

FIG. 8A illustrates frame data input to the memory interface 724 by the conventional logic controller 62 of FIG. 7. FIG. 8B illustrates frame data that is processed and output by the frame data of FIG. 8A by an address-while-display driving method by the memory interface 724 of FIG. 7.

8A and 8B, the first frame data FR1 input to the memory interface 724 may include two frames FR1 and FR2 each having a pause for an address-while-display driving method. Must occupy. Similarly, the second frame data FR2 input to the memory interface 724 must also occupy two frames FR3 and FR4 each having a pause for an address-while-display driving scheme during display.

Therefore, according to the conventional Address-While-Display driving method using a single frame-memory for each of the red (R), green (G), and blue (B) image data, the display image quality of a moving image is reduced. There is a problem of deterioration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of improving the display image quality of a moving image in a method of driving a three-electrode surface discharge structure plasma display panel by an in-display method.

1 is a perspective view showing an internal structure of a conventional three-electrode surface discharge plasma display panel.

FIG. 2 is a cross-sectional view illustrating an example of one display cell of the panel of FIG. 1.

FIG. 3 is a timing diagram illustrating a conventional address-display separation driving method for Y electrode lines of the plasma display panel of FIG. 1.

FIG. 4 is a timing diagram illustrating a typical Address-While-Display driving method for Y electrode lines of the plasma display panel of FIG. 1.

FIG. 5 is a timing diagram illustrating a multiple-address overlapping display driving method, which is a driving method of FIG. 4.

6 is a block diagram illustrating a conventional driving device of the plasma display panel of FIG. 1.

FIG. 7 is a block diagram illustrating an internal configuration of a conventional logic controller of the driving device of FIG. 6.

FIG. 8A illustrates frame data input to a memory interface in the conventional logic controller of FIG. 7. FIG.

FIG. 8B is a diagram illustrating frame data in which the frame data of FIG. 8A is processed and output by the address-while-display driving method by the memory interface of FIG. 7.

FIG. 9 is a block diagram illustrating an internal configuration of a logic controller according to an address-while-display driving method according to the present invention in the driving apparatus of FIG. 6.

FIG. 10A illustrates frame data input to a subfield matrix unit in the logic controller of FIG. 9.

FIG. 10B is a diagram illustrating frame data output from a subfield matrix unit in the logic controller of FIG. 9.

FIG. 11 is a block diagram illustrating an internal configuration of a matrix buffer unit in the logic controller of FIG. 9.

FIG. 12 is a block diagram illustrating an internal configuration of a red memory controller in the memory controller of the logic controller of FIG. 9.

FIG. 13 is a diagram illustrating an operation sequence of the red memory controller of FIG. 12.

FIG. 14A illustrates frame red data input to the red memory controller of FIG. 12.

FIG. 14B is a diagram illustrating frame red data of the frame red data of FIG. 14A processed and output by the address driving method during display by the red memory controller of FIG. 12.

<Description of the symbols for the main parts of the drawings>

1 ... plasma display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 protective layer,

13 ... back glass substrate, 14 ... discharge space,

16 phosphors, 17 bulkheads,

X ₁ , ..., Xn ... X electrode line, Y ₁ , ..., Yn ... Y electrode line,

A ₁ , ..., Am ... address electrode line, Xna, Yna ... transparent electrode line,

Xnb, Ynb ... metal electrode line, SF ₁ , ... SF ₈ ... sub-field,

S _Y1 , ..., S _Y8 ... Y electrode drive signal, GND ... ground voltage,

S _X1..4 , S _X5..8 ... X electrode drive signal, S _A1 .. _m ... display data signal, 2, 5 ... display discharge pulse, 3 ... reset pulse,

6 ... scan pulse, 62 ... logic control,

63 ... address drive, 64 ... X drive,

65 ... Y drive unit, 66 ... image processing unit,

71, 91, gamma correction unit, 711, 911, first-in, first-out memory,

712, 912, error diffusion unit, 721, 921, subfield generation unit,

722, 922, subfield matrix, 723, 923, matrix buffer,

724 memory interface, 924 memory control,

RFM, RFM1, RFM2, RFM3 ... Red frame-memory,

GFM, GFM1, GFM2, GFM3 ... Green frame-memory,

BFM, BFM1, BFM2, BFM3 ... Blue frame-memory,

725, 925, rearrangement, 726, 926, synchronous adjustment,

75, 95 ... clock buffer, FR1, ..., FR4 ... frame,

11R, 11G, 11B ... delay elements,

924R ... Red memory control unit, 101 ... Initial control unit,

102 ... recording control, 103 ... reading control,

104 ... selection control, 107 ... output selection,

A105, B105, C105 ... port control unit,

A106, B106, C106 ... port buffer.

The present invention for achieving the above object, as a method of driving the plasma display panel of the three-electrode surface discharge structure in the display-address method, comprising three steps that are repeatedly performed.

In the first step, the n-th (n is an integer of 3 or more) frame data input from the outside is written in the first frame-memory and at the same time, the n-2 and the second are written in the second and third frame-memory. By reading and processing the n-1 frame data, the (n-2) 'frame data corresponding to the display-address method is formed and output as data for address discharge of the (n-2)' frame.

In the second step, the n + 1th frame data input from the outside is written to the second frame-memory, and the n-1th and nth frame data stored in the third and first frame-memory are stored. By reading and processing, (n-1) 'frame data corresponding to the display-address method is formed and output as data for address discharge of the (n-1)' frame.

In the third step, the n + 2th frame data input from the outside is written to the third frame-memory, and the nth and n + 1th frame data stored in the first and second frame-memory are read. And n &lt; th &gt; frame data corresponding to the out-of-display method are formed and output as data for address discharge of the n'th frame.

According to the above in-display address driving method of the present invention, two frame data recorded in two frame-memory are read and stored in the other one frame-memory while being processed into single frame data corresponding to the in-display-address scheme. New frame data is recorded. Since the operation is continuously performed in units of frames, data for address discharge may be continuously output. Accordingly, the display quality of the moving image can be improved also by the in-display driving method.

Hereinafter, preferred embodiments according to the present invention will be described in detail.

FIG. 9 illustrates an internal configuration of the logic controller 62 according to the address-while-display driving method according to the present invention in the driving apparatus of FIG. 6. Referring to FIG. 9, the logic controller 62 of the driving apparatus of FIG. 6 includes a clock buffer 95, a synchronization controller 926, a gamma correction unit 91, an error diffusion unit 912, and first-in-first-out. (First-In First-Out) memory 911, subfield generator 921, subfield matrix unit 922, matrix buffer unit 923, memory controller 924, frame-memory RFM1,. ..., BFM3), rearrangement unit 925, power control unit 93 and XY control unit 94. Here, three frame memories (RFM1, ..., BFM3) are provided for each of red (R), green (G), and blue (B) image data.

The clock buffer 95 converts the 26-megahertz (MHz) clock signal CLK26 from the image processor (66 in FIG. 6) into a 40-megahertz (MHz) clock signal CLK40 and outputs the converted signal. The synchronization adjustment unit 926 includes a 40-megahertz (MHz) clock signal CLK40 from the clock buffer 95, an initialization signal RS from the outside, and a horizontal synchronization signal from the image processing unit (66 in FIG. 6). (H _SYNC ) and the vertical sync signal V _SYNC are input. The synchronization adjusting unit 926 outputs the horizontal synchronization signals H _SYNC1 , H _SYNC2 , and H _SYNC3 in which the input horizontal synchronization signal H _SYNC is delayed by a predetermined number of clocks, respectively. V _SYNC ) outputs vertical synchronization signals V _SYNC2 and V _SYNC3 delayed by a predetermined number of clocks, respectively.

The image data R, G, and B input to the gamma correction unit 91 have reverse nonlinear input / output characteristics in order to correct the nonlinear input / output characteristics of the cathode ray tube. Therefore, the gamma correction unit 91 processes the image data R, G, and B of the reverse nonlinear input and output characteristics to have a linear input and output characteristic. The error diffusion unit 912 reduces the data transmission error by using the first-in first-out memory 911 to move the position of the maximum sign bit that is the boundary bit of the image data R, G, and B.

The subfield generator 921 converts the 8-bit image data R, G, and B into image data R, G, and B of the number of bits corresponding to the number of subfields, respectively. For example, when grayscale driving is performed with 14 subfields in a unit frame, after converting 8-bit image data R, G, and B into 14-bit image data R, G and B, respectively, In order to reduce the data transmission error, 16 bits of image data R, G, and B are output by adding invalid data '0' of the maximum value bit MSB and the minimum value bit Least SignificantBit.

The subfield matrix unit 922 rearranges 16-bit video data R, G, and B into which data of different subfields is simultaneously input, so that data of the same subfield is simultaneously output. The matrix buffer unit 923 processes the 16-bit image data R, G, and B from the subfield matrix unit 922 and outputs it as 32-bit image data (R, G, B).

The memory control unit 924 includes a red memory control unit (924R in FIG. 12) and three green (G) frame-memory units for controlling three red frame R memories (RFM1, RFM2, and RFM3). Green memory control unit (not shown) for controlling the fields GFM1, GFM2, and GFM3, and blue memory control unit for controlling the three frame-memory units BFM1, BFM2, and BFM3 for blue (B). Not shown). Each memory control unit (not shown) in the memory control unit 924 temporarily records corresponding image data R or G or B from the matrix buffer unit 923 in one frame-memory at the same time. The two frame data recorded in the remaining two frame memories are read out and processed into single frame data corresponding to the in-display method. The single frame data processed as described above is continuously output in units of frames and input to the rearrangement unit 925. A control method of the memory controller 924 related to this will be described in detail with reference to FIGS. 12 and 13. In FIG. 9, reference numeral EN denotes an enable signal generated from the XY control unit 94 and input to the memory control unit 924 to control the data output of the memory control unit 924. In addition, the reference numeral S _SYNC is generated from the XY control unit 94 to control data input / output in units of 32-bit slots in the memory control unit 9724 and the rearrangement unit 925, and thus the memory control unit 924 and the rearrangement unit. The slot synchronization signal input to 925 is indicated. The rearrangement unit 925 rearranges and outputs 32-bit image data R, G, and B from the memory control unit 924 so as to conform to the input format of the address driver (6 in FIG. 6).

Meanwhile, the power controller 93 processes the image data signals R, G, and B input from the error diffusion unit 912 to display the number of all discharge-cells in the plasma display panel 1 in FIG. 6. A load ratio, which is a ratio of the number of discharge-cells to be estimated, is predicted in each frame unit, and the corresponding discharge recovery control data APC is input to the XY controller 94. The XY control unit 94 operates in accordance with the discharge recovery control data APC and the built-in drive sequence from the power control unit 93 to output the X drive control signal S _X and the Y drive control signal S _Y. do.

FIG. 10A illustrates frame data input to the subfield matrix unit 922 by the logic controller 62 of FIG. 9. Referring to FIG. 10A, each of 16-bit image data R, G, and B input to the subfield matrix unit 922 has a structure in which data of different subfields is simultaneously input. FIG. 10B illustrates frame data output from the subfield matrix unit 922 in the logic controller 62 of FIG. 9. Referring to FIG. 10B, each of 16-bit image data R, G, and B output from the subfield matrix unit 922 has a structure in which data of the same subfield is simultaneously input.

11 illustrates an internal configuration of the matrix buffer unit 923 in the logic controller 62 of FIG. 9. Referring to FIG. 11, the matrix buffer part 923 includes a red delay element 11R, a green delay element 11G, and a blue delay element 11B. The red delay element 11R delays the 16-bit red image data R input from the subfield matrix unit 922 by an input time of 16 clock pulses and outputs the same to the positions of the first to sixteenth bits. Meanwhile, the 16-bit red image data R input from the subfield matrix unit 922 is directly output to the positions of the 17th to 32nd bits. Accordingly, the 16-bit red image data R from the subfield matrix unit 922 is output as the 32-bit red image data R. FIG. The same applies to the green and blue image data G and B. Here, the same reset signal RS, clock signal CLK40, second vertical synchronization signal V _SYNC2 , and second horizontal synchronization signal H _SYNC2 are input to each of the delay elements 11R, 11G, and 11B.

The internal structure of the red memory control unit 924R in the memory control unit 924 is shown in the logic control unit 62 of FIG. The internal structure and operation of the red memory control unit 924R are equally applied to the green memory control unit and the blue memory control unit (not shown). Referring to FIG. 9, a reset signal RS, a clock signal CLK40, a third vertical synchronization signal V _SYNC3 , and a third horizontal synchronization signal as a control input signal for controlling the operation of the red memory controller 924R. (H _SYNC3 ), slot sync signal S _SYNC , and data enable signal EN. Of course, these control signals are equally input to the green memory control section and the blue memory control section, which are not shown.

The red memory control unit 924R includes an initialization control unit 101, a write control unit 102, a read control unit 103, a selection control unit 104, three port control units A105, B105, and C105, and three port buffers. (A106, B106, C106), and an output selector 107. The initialization control unit 101 inputs a control signal for initializing each of the memories RFM1, RFM2, and RFM3 to the selection control unit 104 when power is applied or a reset signal RS is applied. The write control unit 102 inputs a control signal for the write operation of each of the memories RFM1, RFM2, and RFM3 to the selection control unit 104. The read control unit 102 inputs a control signal for the read operation of each of the memories RFM1, RFM2, and RFM3 to the selection control unit 104. The selection controller 104 selectively controls the three port controllers A105, B105, and C105 according to control signals from the controllers 101, 102, and 103, and flags corresponding to the output data. Output the signal. Accordingly, each port control unit A105, B105, C105 controls the initialization, write and read operations of the corresponding red frame-memory RFM1, RFM2, RFM3. Each of the port buffers A106, B106, and C106 temporarily stores the 32-bit red image data R from the matrix buffer unit (923 in Figs. 9 and 11), and corresponding frame-memory memories (RFM1, RFM2) for red. Or the 32-bit red image data R from the corresponding red frame-memory memories RFM1, RFM2 and RFM3 are temporarily stored and output to the output selector 107. Accordingly, the output selector 107 processes two frame data input from two port buffers A106-B106 or B106-C106 or C106-A106 to output single frame data corresponding to the in-display method. do.

FIG. 13 shows an operation sequence of the red memory control unit 924R of FIG. 12. This operation sequence is performed by the green control unit (not shown) and the blue control unit in the memory control unit 924 in the logic control unit 62 of FIG. 9. The same applies to the memory control unit (not shown).

Referring to FIG. 13, the operation sequence of the red memory controller 924R includes three operation modes performed in units of frames. These three modes of operation are continuously repeated.

In the first mode ("00"), the nth (n is an integer of 3 or more) frame red data input from the matrix buffer unit 923 is written to the first red frame-memory RFM1 (step M001), The n-th and n-th frame red data recorded in the second and third frame-memories RFM2 and RFM3 are read (steps M002 and M003) and processed to correspond to the in-display method. The (n-2) 'frame red data is formed and output to the reordering unit (925 in FIG. 9) as red data for address discharge of the (n-2)' frame.

In the second mode ("01"), the n + 1th frame red data input from the matrix buffer part 923 is written to the second red frame-memory RFM2 (step M012), and the third and The n-th and n-th frame red data recorded in the first red frame-memory memories RFM3 and RFM1 are read (steps M013 and M011) and processed so that the n-th corresponding to the in-display method is displayed. 1) 'frame red data is formed and output to the rearrangement unit 925 as red data for address discharge of the (n-1)' th frame.

In a third step, the n + 2th frame red data input from the outside is written to the third red frame-memory RFM3 (step M103), and simultaneously with the first and second red frame-memory RFM1. The n'th and nth + 1th frame red data recorded in the RFM2 is read (steps M101 and M102) and processed to form an n'frame red data corresponding to the in-display method of the n'th frame. The red data for address discharge is output to the rearrangement unit 925.

In summary, new frame data is written to the remaining one frame-memory while two frame data recorded in the two frame-memory are read out and processed into single frame data corresponding to the in-display-address scheme. Since the operation is continuously performed in units of frames, data for address discharge may be continuously output.

FIG. 14A illustrates frame red data input to the red memory controller 924R of FIG. 12. FIG. 14B illustrates frame red data that is processed and output by the frame red data of FIG. 14A by an address driving method during display by the red memory controller 924R of FIG. 12.

Referring to FIGS. 14A and 14B, a first frame corresponding to the address driving method during display is displayed by the first frame red data FR1 and the immediately preceding frame red data (not shown) input to the red memory controller 924R. Red data of (FR1) is generated. Similarly, the red data of the second frame FR2 corresponding to the address driving method during display is generated by the first frame red data FR1 and the second frame red data FR2 input to the red memory controller 924R. Is generated. Since the operation is continuously performed in units of frames, data for address discharge may be continuously output. Accordingly, the display quality of the moving image can be improved also by the in-display driving method.

As described above, according to the in-display address driving method of the plasma display panel according to the present invention, two frame data recorded in two frame memories are read out into single frame data corresponding to the in-display address method. During processing, new frame data is written to the remaining one frame-memory. Since the operation is continuously performed in units of frames, data for address discharge may be continuously output. Accordingly, the display quality of the moving image can be improved also by the in-display driving method.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

Claims (2)

A method of driving a plasma display panel having a three-electrode surface discharge structure by an in-display method, N-th and n-th frame data recorded in the second and third frame-memories while simultaneously writing n-th (n is an integer of 3 or more) frame data input from the outside into the first frame-memory A first step of forming and outputting (n-2) 'frame data corresponding to the display-address method by reading and processing the data as data for address discharge of the (n-2)' frame; The n + 1th frame data input from the outside is written to the second frame-memory, and the n-1th and nth frame data recorded in the third and first frame-memory are read and processed. A second step of forming (n-1) 'frame data corresponding to the display-address method and outputting the data as address discharge for the (n-1)' frame; And The n + 2th frame data input from the outside is written into the third frame-membrane, and the nth and n + 1th frame data recorded in the first and second frame-memory are read and processed. And a third step of forming n 'frame data corresponding to the in-display method and outputting the n' frame data as data for address discharge of the n 'frame. The method of claim 1, A method of driving an in-display display of a plasma display panel in which steps (a), (b), and (c) are performed on each of red image data, green image data, and blue image data input from the outside.