KR100374483B1 - Spreading system using balanced duo-binary encoder and decoder, and its application to spreading method - Google Patents

Abstract

The present invention relates to a baseband spreading system of a direct spreading code division multiple access (DS / CDMA) system, and more particularly, to a duo-binary. The present invention relates to a diffusion system using a balanced double binary decoder that reduces peak / average power ratio and facilitates the design of a radio frequency circuit.

The balanced double binary decoder of the present invention includes a first double binary code means for receiving input data and generating a double binary signal, a second double binary code means for receiving inverted input data and generating a double binary signal, and A transmitter which multiplies and modulates each of the dual binary signals by multiplying orthogonal carriers and spreading codes, and transmits them together; It is composed of a balanced double binary decoder that multiplies the received double binary spreading signal by the orthogonal carrier and the spreading code to remove the carriers, and then takes and subtracts the absolute value of each of the signals. According to the present invention, input data is selectively transmitted depending on whether a positive signal or a negative signal is used, and both synchronous and asynchronous demodulation methods can be used, and the peak / average power ratio is 1, thereby reducing the burden of RF circuit design.

Description

Diffusion system using a balanced double binary coder and its diffusion method {SPREADING SYSTEM USING BALANCED DUO-BINARY ENCODER AND DECODER, AND ITS APPLICATION TO SPREADING METHOD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a baseband spreading system of a DS / CDMA system, and in particular, by using a balanced duo-binary decoder, the peak / average power ratio is reduced to reduce the radio frequency (RF). A diffusion system using a balanced double binary decoder that facilitates circuit design, and a diffusion method thereof.

FIG. 1 illustrates a spreading system using a conventional pilot channel, in which only a pilot channel and one data channel are used. 1 assumes that all transceivers in a system have the same structure without distinguishing between a base station and a terminal. Such a system can be conceived in a system in which a terminal and a terminal directly communicate with each other in a distributed system such as satellite communication. In consideration of the receiving side, the transmitting side transmits data and pilot at the same time. Thus, the data and pilot signals share the transmit RF power. In other words, the conventional spreading system transmits two codes simultaneously to distinguish the pilot channel and the data channel, so that when a subscriber transmits two codes, the total capacity of the system is reduced by half. This means that no matter how much the output of the transmission increases on the individual subscriber side, the transmission signals of different users act as interference signals, which leads to a saturation of capacity, and the interference noise signal is closely related to the number of codes being transmitted in the system. . Thus, the conventional spreading system has twice as many transmission codes as the number of users and generates twice the interference noise. Also, the spreading system using the conventional pilot channel has a peak 1.4 V, the lowest to transmit the same power. Because it operates at 0 V, a radio frequence power amplifier should be designed for 1.4 V at which peak power is transmitted, and 0 V should be transmitted at transient minimum power. However, RF power amplifiers are less efficient for low power outputs such as 0V.

Figure 2 shows a conventional double binary decoder, in detail a double binary encoder having a double binary code means (1) for receiving data and generating a double binary signal; It consists of a double binary decoder 2 for demodulating the double binary signal. The double binary code means 1 takes the data as an input of a modulo-2 adder 11 (for example, an exclusive OR) and delays the modulo-2 adder 11 delayed by the time delay means 12. A pre-processing code means (10) having a modulo-2 adder (11) and said time delay means (12) for making another output of < RTI ID = 0.0 > And a digital filter means (20) for generating a double binary signal by summing the output of the modulo-2 adder (11) and the output of the modulo-2 adder (11) delayed by the time delay means (21). do. The dual binary decoder includes: an absolute value measuring device 30 which takes an absolute value of the received binary signal; And an inverter 40 for inverting the absolute value.

3 is a diagram showing the variation of each partial waveform of a conventional double binary decoder.

The conventional double binary decoder does not need to know the carrier phase of the double binary signal exactly. That is, if the carrier exactly matches or exactly inverts the received signal, there is an advantage that no error occurs in data transmission. However, depending on the level (High / Low) of the input data, an off state (for example, a mute) state of the signal may exist, which may cause problems in code search / tracking and carrier tracking. have.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to transmit only one number of transmission codes so that only the number of transmission codes of the entire system exist, and the peak / average power ratio is 0 dB. By reducing the burden on RF circuit design. Another object of the present invention is to provide a system for balancing the instantaneous output signal power by allowing a constant signal power to be present on the line regardless of the level of the input signal.

1 is a block diagram of a diffusion system according to the prior art.

2 is a block diagram of a double binary decoder according to the prior art.

3 is a signal change diagram showing the operation of the double binary decoder of FIG.

4 is a block diagram of a balanced double binary decoder according to the present invention.

5 is a block diagram of an asynchronous demodulation spreading system using the balanced double binary decoder of FIG.

FIG. 6A is a block diagram of a synchronous demodulation spreading system using the balanced double binary decoder of FIG. 4; FIG.

FIG. 6B is a schematic diagram of another synchronous demodulation spreading system using the balanced dual binary decoder of FIG. 4; FIG.

7 is a block diagram of a carrier recovery circuit for synchronous demodulation according to the prior art.

8A is a waveform of an input signal of the diffusion system of FIG. 6A.

8B is a waveform of a received signal of a PN_I0 channel of the spreading system of FIG. 6A.

8C is a waveform of a received signal of the PN_I1 channel of the spreading system of FIG. 6A.

FIG. 8D is a waveform (waveform for determination) in the spreading system of FIG. 6A (absolute value of PN_I1 signal-absolute value of PN_I1 signal)

9A is a signal diagram of the diffusion system according to FIG. 1;

9b is a signal diagram of a diffusion system according to the invention of FIG.

*** Description of the symbols for the main parts of the drawings ***

10: preprocessing code means 20: digital filter

400: double binary code means 640, 650: balanced double binary coder

The balanced double binary coder of the present invention comprises: an in-phase channel having first double binary code means for receiving input data and generating a double binary signal, and a modulation means for multiplying the double binary signal by an in-phase carrier; An inverter for inverting the negative signal of the input data, second double binary code means for receiving the input data inverted by the inverter and generating a double binary signal, and a modulation means for multiplying the double binary signal by an orthogonal phase carrier; An orthogonal phase channel provided; And an adder for adding the modulated in-phase channel signal and the modulated quadrature phase channel signal, and another balanced bi-decoder decoder according to the present invention comprises: an in-phase carrier removing means for multiplying a received double-binary signal by an in-phase carrier; An in-phase channel having an absolute value meter which takes an absolute value of the double binary signal transmitted from said carrier removing means; An orthogonal phase channel comprising: an orthogonal phase carrier removing means for multiplying the received dual binary signal by an orthogonal phase carrier, and an absolute value measuring instrument for taking an absolute value of the double binary signal transmitted from the carrier removing means; And a subtractor that subtracts the absolute value of the in-phase channel from the absolute value of the quadrature channel.

4 is a schematic diagram of a balanced double binary decoder, in which a balanced double binary encoder 40 and a double binary decoder 41 are formed, and the double binary encoder 40 receives input data and generates a double binary signal. An in-phase channel having a first double binary code means (400) and modulation means (421) for multiplying the double binary signal by an in-phase carrier (cos wt); An inverter 420 for inverting the input data, a second double binary code means 410 for receiving a data inverted by the inverter and generating a double binary signal, and a quadrature phase carrier (sin) to the double binary signal; an orthogonal phase channel having modulation means 422 multiplying wt); And an adder 423 that adds the modulated in-phase channel signal and the modulated quadrature phase channel signal, wherein the balanced double binary decoder 41 multiplies the received double binary signal by the in-phase carrier (cos wt). An in-phase channel having a phase carrier removing means (424) and an absolute value measuring instrument (427) which takes an absolute value of the double binary signal transmitted by the in-phase carrier removing means (425); Orthogonal phase carrier removing means 426 multiplying the received double binary signal by a quadrature phase carrier sin wt and an absolute value taking an absolute value of the double binary signal transmitted by the orthogonal phase carrier removing means 426. A quadrature phase channel having a meter 428; And a subtractor 430 which subtracts the in-phase channel signal from the absolute value of the quadrature phase channel. The first double binary code means 400 and the second double binary code means 410 are composed of preprocessing code circuits 405 and 415 and digital filter 406 and 416. The preprocessing code circuits 405 and 415 use the data as inputs to the modulo-2 adders 401 and 411, and the modulo-2 delayed by the time delay means 402 and 412. Modulo-2 adders 401 and 411 which take outputs of adders 401 and 411; And the time delay means 402, 412, the digital filter means 406, 416, the output of the modulo-2 adder 401, 411, and the time delay means 403. And an adder 423 summing the outputs of the modulo-2 adders 401 and 411 delayed by 413.

The balanced double binary decoding system is a modified form of a double binary decoder for application to a diffusion system. The balanced double binary decoder is defined as a circuit in which the double binary decoder removes an off state of the signal (a phenomenon in which the transmission output is temporarily muted when the input data is 1). Regardless of (1,0), it refers to a system in which a constant signal power exists on a line to maintain instantaneous output balance. Referring to FIG. 4, input data is transmitted through an upper channel (I channel, in-phase), and the input data is also transmitted through an inverter 420 and a lower channel (Q channel, quadrature). -phase)). The carriers may be transmitted using different frequencies. However, when cos wt and sin wt are classified, it is assumed that the carrier phase is synchronized. In FIG. 4, the input data has two levels of high / low. When the input data is high, the transmission of the upper path is turned off and the lower path roll signal is transmitted. In contrast, when the input data is low, the lower path is turned off and the input data is transmitted through the upper path. That is, a signal exists in one channel regardless of the level of the input data. In addition, the system has a transmission scheme similar to that of a general Orthogonal Modulation (BFSK), so that the BER performance is the same as that of the BFSK.

Spreading systems using balanced double binary decoders can be configured as quadrature spreading or binary spreading. FIG. 5 illustrates an asynchronous demodulation circuit of a binary spreading system using a balanced double binary decoder according to the present invention. In detail, a transmitter of the spreading system receives a first binary data to generate a double binary signal. An in-phase channel having a binary code means 501 and a spreading means 504 for generating a spread signal by multiplying the double binary signal generated by the first double binary code means 501 with a spread code PN_I0; ; An inverter 503 for inverting input data, second double binary code means 502 for receiving the inverted input data and generating a double binary signal, and generating by the second double binary code means 502 An orthogonal phase channel having spreading means 504 for generating a spreading signal by multiplying the spread binary code by the spreading code PN_I1; An adder (506) for adding the in-phase channel signal and the quadrature phase channel signal; A carrier modulating means 507 for multiplying the added signal by a carrier wave (cos wt), wherein the receiving part of the spreading system despreads the received signal by despreading codes PN_I0 and PN_I1, respectively. 508 and 509; A carrier wave (cos wt +) is applied to each of the signal despread by the despread code PN_I0 and the signal despread by the despread code PN_I1. ), (sin wt + In-phase carrier removal means (510), (512), orthogonal phase carrier removal means (511), (513) multiplied by; Absolute of the signals transmitted from the in-phase carrier removing means 510 and the quadrature phase carrier removing means 511 and the signals transmitted from the in-phase carrier removing means 512 and the quadrature phase carrier removing means 513 Absolute value meters 514, 515, 516, 517, each taking a value; Square root 518, which calculates the square root of the absolute values of the absolute value measuring devices 514, 515, and sums them, and sums the square root of the absolute value of the absolute value measuring devices 516, 517, respectively. A square root 519 for obtaining the square root; And a subtractor 520 which subtracts the value of the square root 518 from the value of the square root 519.

That is, the transmitter multiplies the input data by the two signals output through the balanced double binary code means 501 and 502, respectively, the two spreading codes PN_I0 and PN_I1 to form a spreading signal. The spreading signals are combined and multiplied by the carrier wave (cos wt) to output the I channel.

Looking at the path upward of the receiver, the carrier signal (cos wt +) after the received signal is multiplied by the spreading code (PN_I0). ), (sin wt + ) Is multiplied by the receiver, Since the phases are out of phase, the components are separated into the I and Q channels, so that the And sin Appears. After taking the absolute values of the low frequency components of the I and Q channels, square each signal to extract the energy of the received signal of the upper path. When the same process is performed on the lower path, the energy of the received signal is extracted. The two received signals are compared, and the data of the path where the large energy is input is inverted to determine the output data.

Fig. 6A shows a synchronous demodulation circuit using a balanced double binary decoder according to the present invention. In detail, the transmitting section of the synchronous demodulation circuit includes data alteration means 600a which can alternately select input data; Balanced double binary coders (640, 650) for generating double binary signals from the selected data; Carrier modulation means (612, 613) for multiplying the double binary signals transmitted by the balanced double binary coders (640, 650) by carriers (cos wt) and (sin wt), respectively; And an adder 614 for summing the modulated signals, the receiver of the synchronous demodulation circuit having a carrier wave (cos wt +) to the received signal, respectively. ), (sin wt + Carrier removal means (615, 616) for removing the carrier by multiplying The despreading code 617, 618 and the carrier removing means 616, which despread by multiplying the despreading codes PN_I0 and PN_I1 by the carrier removing means 615, respectively, despread the code. Despreading means (619, 620) for multiplying (PN_Q0) and (PN_Q1) to despread; Absolute value measuring units (621) and (622) each taking an absolute value of a signal transmitted from the despreading means (617) and (618); A subtractor 625 which subtracts the value of the absolute value meter 621 from the value of the absolute value meter 622; Absolute value measuring instruments (623) and (624) each taking an absolute value of a signal transmitted from said despreading means (619) and (620); A subtractor 626 which subtracts the value of the absolute value measuring instrument 623 from the value of the absolute value measuring instrument 624; And data alternating means (627a) for selecting any one of the outputs of the subtractor (625) and (626). In the balanced double binary encoder 640, spreading codes PN_I0 and PN_I1 are used, and in the balanced double binary encoder 650, spreading codes PN_Q0 and PN_Q1 are used.

Referring to the transmitter of FIG. 6A, input data is alternately inputted once in an upper path and once in a lower path. Data input to the upper path is separated and transmitted again to the upper path and the lower path. At any given time, signals exist in only one of the two paths. The signal in each path occupies half the bandwidth of the input signal. Each path is spread with spread codes PN_I0 and PN_I1, added to each other, and multiplied by a carrier wave (cos wt) to complete processing of the transmitter for the I channel. After the Q channel is processed like the I channel, the Q channel can extract the output signal like the I channel.

FIG. 6B illustrates that input data is simultaneously input to the I channel and the Q channel, unlike FIG. 6A. In detail, FIG. 6B connects the data alteration means 600a instead of 600b, and the data alteration means 627a. Instead, the adder 627b is connected.

The spreading codes PN_I0, PN_I1, PN_Q0, and PN_Q1 shown in Figs. 5 and 6A and 6B select and use codes that are orthogonal or semi-orthogonal to each other. That is, a shifted code for a single source noise code (Pseudo Noise Code), a code multiplied by 101010 ....., a PN code that is not related to each other, and a Walsh code is directly added to the source PN code. Codes generated by multiplication can be used for each spreading code. FIG. 7 illustrates a carrier recovery circuit for synchronous demodulation according to the prior art, and recovers a carrier used in the carrier removing means in an embodiment of the present invention. In other words, the received signals all have four paths. There is a phase difference. The two path signals of the I channel of the transmitter are despread by despreading means 701, 702, 703, and 704, respectively, and then a baseband filter ( ) Through (705), (706), (707), (708) and through squarers (709), (710), (711), (712) Frequency, then through a frequency distribution circuit (÷ 2) The carrier frequency and phase of are restored. The restored carrier coincides with the phase of the original received signal ( ) Or reverse phase + π), but it is irrelevant to the restoration of the input data. The carrier of the Q channel is also recovered in the same manner as the I channel.

Of a spreading system using the balanced double binary decoder The BER performance for is the same as for BFSK. This means that when the input data is +1, only the signal corresponding to +1 is spread and transmitted, and when the input is -1, the signal corresponding to -1 is also spread and transmitted, and the receiver receives +1 and 0. By adding or by adding -1 and 0 (one of the forward / reverse phase signals of each of the received signal I / Q channels is always zero) and compare the final sum result to +1 or close to -1. This is because the demodulation method is similar to that of the BFSK which selects the higher energy of the two signals during data restoration.

8A, 8B, 8C and 8D show simulation waveforms of a spreading system using a baseband balanced double binary decoder. FIG. 8A shows the waveform of the input data, FIG. 8B shows the Intergrate Dump result waveform of the received signal of the PN_I0 path, FIG. 8C shows the Integrate Dump result waveform of the received signal of the PN_I1 path, and FIG. 8D shows FIG. 8C. The waveform when the absolute value of FIG. 8B is subtracted from the absolute value of (waveform for determination) is shown.

FIG. 9A is a signal diagram of a diffusion system according to the prior art, in which a signal (Walsh0 + Data * Walsh1) is multiplied by (PN Code) to be output as a transmission signal. For any instantaneous time, the transmit signal is + 2V, 0V, -2V, the peak absolute voltage is 2V, and the total time absolute average voltage is 1V because of the 0V time interval. Therefore, the peak / average voltage ratio is 2V / 1V = 2.

FIG. 9B is a signal diagram of the spreading system of FIG. 5 in which (PN_I0) is selected for input data and (PN_I1) is selected for inverted input data. For each instantaneous time, the transmit signal is + 1V and -1V, so the peak absolute voltage is 1V and there is no time span where 0V lasts, so the total time absolute average voltage is 1V. Therefore, the peak / average voltage ratio is 1V / 1V = 1.

Comparing the diffusion system according to the present invention and the diffusion system according to the prior art is shown in Table 1.

In the present invention, referring to Table 1, the transmission power and the number of subscribers of the system are the same as compared to the conventional spreading system, but only one code (data channel) is used for data transmission without using a pilot code in a channel per subscriber. It has the advantage of reducing the number of transmission codes to reduce the interference noise, and the 0dB peak / average power ratio facilitates high frequency circuit design.

In addition, the present invention has the advantage that asynchronous demodulation and synchronous demodulation are possible.

Claims (32)

First double binary code means for receiving input data and generating a double binary signal; An inverter for inverting the input data; A second double binary code means for receiving input data inverted by the inverter and generating a double binary signal; The first and second double binary code means each having the data as the first input of a modulo-2 adder and the output of the modulo-2 adder delayed by a first time delay means as a second input. Preprocessing code means having a low-2 adder and said first time delay means; And means for generating the double binary signal by summing the output of the modulo-2 adder and the output of the modulo-2 adder delayed by a second time delay means. delete The method of claim 1, And said modulo-2 adder is an exclusive OR. The method of claim 1, And said first time delay means and said second time delay means are one time delay means and not separate. A first absolute value measuring device which takes an absolute value of the binary signal received from the first channel; A second absolute value measuring device which takes an absolute value of the binary signal received from the second channel; And a subtractor for subtracting the absolute value of the first channel from the absolute value of the second channel. A spreading system comprising: a channel having a first double binary code means for receiving input data and generating a double binary signal, and a spreading means for generating a spread signal by multiplying the double binary signal by a first spreading code; A multiplier for generating a double binary signal by receiving an input data inverted by the inverter, and generating a spreading signal by multiplying the double binary signal by a second spreading code; A balanced double binary encoder comprising an orthogonal channel having a spreading means, an adder for adding the channel signal and the orthogonal channel signal, and a modulation means for multiplying a signal transmitted from the adder with a modulation wave, In this case, the first and second double binary code means each use the data as a first input of a modulo-2 adder, and output the output of the modulo-2 adder delayed by a first time delay means as a second input. Preprocessing code means comprising a modulo-2 adder and said first time delay means; And means for summing the output of the modulo-2 adder and the output of the modulo-2 adder delayed by a second time delay means to generate the double binary signal. The method of claim 6, And said modulating wave is an in-phase modulating wave. The method of claim 6, And said modulated wave is a quadrature phase modulated wave. The method of claim 6, The balanced double binary coder (hereinafter, referred to as a first balanced double binary coder) uses an in-phase modulated wave as the modulation wave, and the same parallel double binary coder as the first balanced double binary coder (hereinafter, referred to as a second balanced double binary coder). ) Is connected in parallel to the adder for adding the signal of the first balanced double binary encoder and the signal of the second double binary encoder, The second balanced double binary encoder includes a third double binary code means for receiving the input data and generating a double binary signal, and a spreading means for generating a spread signal by multiplying the double binary signal by a third spreading code. and; An inverter for inverting the input data, fourth double binary code means for receiving the input data inverted by the inverter and generating a double binary signal, and multiplying the double binary signal by a fourth spreading code to generate a spread signal An orthogonal channel having diffusion means; An adder for adding the channel signal and the orthogonal channel signal; And modulation means for multiplying a signal transmitted from the adder by a quadrature phase modulated wave. delete The method of claim 9, And a data alteration means for alternating said input data to send to said first balanced double binary coder and said second balanced double binary coder. The method of claim 9, And said input data is simultaneously transmitted to said first balanced double binary coder and said second balanced double binary coder. delete The method of claim 6, And said modulo-2 adder is an exclusive OR. First despreading means and second despreading means for multiplying the received signal by a first spreading code and a second spreading code respectively to despread; An in-phase carrier removing means for multiplying each of the signals transmitted from the first despreading means and the second despreading means by an in-phase carrier, and an absolute value measuring instrument that takes an absolute value of the signal from which the carrier is removed, respectively. A first in-phase channel and a second in-phase channel; Orthogonal phase carrier removing means for multiplying a signal transmitted from said first despreading means and said second despreading means by an orthogonal phase carrier, and an absolute value measuring instrument that takes an absolute value of the signal from which said carrier is removed, respectively; A first quadrature phase channel and a second quadrature phase channel; A first square root unit that squares the first in-phase channel signal and the first quadrature phase channel signal to obtain a square root of the sum of the first in-phase channel signal and the first quadrature phase channel signal; A second square root root to obtain a square root of the sum of squares of the second in-phase channel signal and the second quadrature phase channel signal; And a subtractor for subtracting the value due to the first square root from the value due to the second square root. In-phase carrier removing means and quadrature phase removing means for multiplying the received signal by the in-phase carrier and the quadrature phase carrier, respectively; Despreading means for multiplying a signal transmitted from the in-phase carrier removing means by a first spreading code and a second spreading code, respectively; and absolute value measuring instruments for obtaining absolute values of the signals transmitted from the despreading means. A first in-phase channel and a second in-phase channel; Despreading means for multiplying a signal transmitted from the quadrature phase carrier removing means by a third spreading code and a fourth spreading code, respectively; and absolute value measuring instruments for obtaining absolute values of the signals transmitted from the despreading means. A first orthogonal phase channel and a second orthogonal phase channel; a first subtractor for subtracting an absolute value of the first in-phase channel signal from an absolute value of the second in-phase channel signal; And a balanced double binary decoder having a second subtractor which subtracts the absolute value of the first quadrature phase channel signal from the absolute value of the second quadrature phase channel signal. The method of claim 16, And data alternating means for alternating one of the signals transmitted from said first subtractor and said second subtractor. The method of claim 16, And an adder for adding a signal transmitted from said first subtractor and said second subtractor. The method according to claim 9 or 16, And the first spreading code, the second spreading code, the third spreading code and the fourth spreading code are each orthogonal to each other. The method of claim 19, Wherein the first spreading code, the second spreading code, the third spreading code and the fourth spreading code are shifted codes for one source PN code. The method of claim 19, Wherein the first spreading code, the second spreading code, the third spreading code and the fourth spreading code are codes of a source PN code multiplied by 101010... The method of claim 19, And the first spreading code, the second spreading code, the third spreading code and the fourth spreading code are composed of PN codes unrelated to each other. The method of claim 19, And said first spreading code, said second spreading code, said third spreading code and said fourth spreading code are codes of a source PN code multiplied by a Walsh code. Generating a double binary signal with a positive signal of input data, and simultaneously generating a double binary signal after inverting a negative signal of the input data; Modulating by multiplying each of the double binary signals by a carrier; And a summation summing the modulated double binary signals. The method of claim 24, The generating of the first and second dual binary signals may include: receiving, by a modulo-2 adder, an output of the modulo-2 adder delayed by the input data and a time delay means; Summing the output of the modulo-2 adder and the output of the modulo-2 adder delayed by a time delay means. The method of claim 24, And spreading by multiplying each of the double binary signals by different spreading codes after the first and second double binary signal generation steps. The method of claim 25, And a data selection step of alternately selecting the input data before generating the double binary signal, the same as the third double binary generation step and the second double binary signal generation step that are identical to the first double binary signal generation step. And additionally inputting the input data to the first and second binary binary generation steps or the third and fourth binary binary generation steps according to the selection of the data selection step. Spreading method using balanced double binary coder. The method of claim 26, Equilibrium double binary, wherein the input data includes the first double binary generation step, the second double binary generation step, the third double binary generation step, and the fourth double binary generation step without the data selection step. Spreading method using an encoder. First and second carrier removal steps of removing carriers by multiplying the received dual binary signals by different carriers, respectively; A first and second absolute value measuring step of taking absolute values of the double binary signals from which the carrier is removed; And a first subtraction step of subtracting the other from one of the absolute values. The method of claim 29, First and second despreading steps of multiplying the received double binary signals by different spreading codes, respectively, before the first and second carrier removal steps; A first square root step of adding squared absolute values in the first and second carrier removal steps after the first despreading step and the first and second absolute value measuring steps, respectively; and the first after the second despreading step And a second square root step of adding squares of the absolute values in the second carrier removing step and the first and second absolute value measuring steps, respectively; And a second subtraction step of subtracting the value of the first square root step from the value of the second square root step in place of the first subtraction step. The method of claim 29, First and second despreading steps of multiplying and spreading different spreading codes after the first carrier elimination step, respectively; Steps; A third absolute value measuring step due to the second despreading steps and a fourth absolute value measuring step due to the fourth despreading step; The second subtraction step and the second absolute value measurement absolute value are subtracted from the absolute value of the third absolute value measurement step instead of the first subtraction step. A third subtraction step of subtracting the absolute value in the absolute value measuring step; And a data selection step of alternately selecting one of the second and third subtraction steps. The method of claim 30, And an addition step of adding values of the second and third subtraction steps instead of the data selection step.