KR100374335B1 - Circuit for isolating board of bus system - Google Patents

Abstract

PURPOSE: A circuit for isolating a board of a bus system is provided to isolate a processor board from a global bus system and to make normal processors use a bus when a fault is generated in the corresponding processor board. CONSTITUTION: A control unit generates a control bit which indicates a state of a processor board and each address bit which is an identification of the processor board. A buffer stores the control bit and the address bits. A unit checks the control bit and the address bits, and creates a parity bit. A unit receives control channel information of the control bit, the address bits, and the parity bit, converts the control channel information into a serial data stream, and outputs the serial data stream to a bus. A master board includes the above elements. In addition, a slave board includes a unit which is connected to the bus in parallel and converts control channel information of the serial stream in parallel, and a control unit which checks board identification of the converted control channel information. The master board analyzes states of the processor boards and isolates an abnormal processor board from the bus.

Description

Board Isolation Circuit of Bus System

The present invention relates to a system employing a global bus, and more particularly to a circuit that can isolate a failed board in the event of a bus failure.

In general, a system employing a global bus has many microprocessor boards connected in parallel on a global bus, and an arbitrary processor becomes a master to arbitrate and communicate with a plurality of processors. 1 shows a general configuration of a system employing a global bus. In FIG. 1, the master A and the master B have a dual active (standby) configuration, and the master board generates ACTCLK and FS. The microprocessor boards include an arbitor logic and may acquire a bus license by bus arbitration when the global bus is in an idle state. FIG. 2 shows bus arbitration timing in a global bus system such as FIG. In FIG. 2, PI denotes IDs of microprocessor boards.

The global bus is a structure in which multiple microprocessor boards are connected in parallel to a common bus and have an opportunity to transmit data when they become masters of the global bus. In general, such a global bus structure is used in an exchange system, in which case the global bus uses signals such as ASTCLK, FS, DATACLK, and BUSALM. Such signals are defined as follows. ASTCLK is a clock that is always provided by the master board of the global bus, as shown in Figure 2. The other boards of the global bus are synchronized to this clock. As shown in FIG. 2, the FS is operated by loading its board address into a counter register of a local arbiter logic as a system counter synchronization signal, and occupying the global bus when timed out. Have a chance to Seize AST is a bus occupancy signal that the processor board on the global bus occupies the global bus. Therefore, as shown in FIG. 2, when the AST signal is inserted, other boards cannot occupy the bus. DATA is information transmitted by the processor board occupying the global bus. DATACLK is a synchronous clock of the DATA. BUSALM is a signal that initializes the entire global bus when no global bus is available, i.e., when there is no response because an abnormal status occurs in the global bus.

However, in the case of using the conventional global bus arbitration method as described above, when an abnormal state occurs, the BUSALM signal is generated to initialize the entire bus system. In this case, although the remaining processor boards are operating normally, the entire system is initialized, thereby degrading the performance of the system. Therefore, if any processor board connected in the global bus system fails, it is desirable to isolate the corresponding processor board from the bus system and control the operation of the remaining processor boards.

Accordingly, an object of the present invention is to provide a circuit that can isolate a corresponding processor board from a global bus system and control normal buses to use a bus when an arbitrary processor board fails in the global bus system.

In order to achieve the objects of the present invention, a plurality of processor boards are commonly connected to a bus, and a bus system comprising a master board for controlling bus usage rights of the processors; A control unit for generating control bits indicating the state of the processor board and address bits which are identification information of the processor board, a buffer for storing the control bits and the address bits, and a parity bit by examining the control bits and the address bits output from the buffer. And means for generating a control bit and an address bit and the parity bit outputted from the buffer, and receiving the control channel information, converting the control channel information into a serial data stream, and outputting the serial data stream to the bus. A master board; A controller connected in parallel to the bus and parallel converting the control channel information of the serial stream, the board identification information of the parallel converted control channel information, and a control unit for controlling a corresponding function by checking the self-identification information temporary control bits. Comprising a processor board consisting of: characterized in that to isolate the processor board of the abnormal state on the bus by analyzing the state of the processor board in the master board.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the same parts in the figures represent the same reference signs wherever possible.

In the present invention, when a bus failure occurs in an inability to communicate with a global bus system, when one processor board occupies a bus and an abnormal state is not recovered, or an error is repeatedly repeated when occupying a global bus, a global bus is used. A control channel (S-ch) is added to isolate the processor board from the global bus system. That is, in the present invention, when the master of the global bus system occupies the bus, that is, when there is initialization information in the control channel S-ch in the board into which the bus occupancy signal AST is inserted, the corresponding processor board initializes itself to initialize the global bus. Isolate myself from the system. At this time, the control channel S-ch data output in synchronization with the ASTCLK has the configuration as shown in FIG.

The control channel S-ch data generation occurs for the maintenance of the global bus in the master board A or the master board B. As shown in FIG. 3, the control channel S-ch data has a high logic state, and the start of the control channel S-ch data starts with a start bit transitioned to a low logic state. In addition, the control bit is composed of 2 bits, and can control the slave board in four states. The slave board decodes the control bits C1-C2 of the control channel S-ch and takes a corresponding action. In addition, in FIG. 3, the PI address bits are used as board identification numbers on the global bus, and are used when the master board A or the master board B selectively controls the slave board. The parity bit is a parity for a bit stream of control channel S-ch data, and a master board A or a master board B is generated.

4 is a diagram showing the configuration of a circuit for generating the control channel S-ch according to the present invention, in which a control & address setting part 41 is connected to a data bus and a control bit output from a controller of a master board. Input and save board ID. The setting unit 41 is an 8-bit latch F (374 octal latch) and can be configured as shown in FIG. The setting unit 41 receives and latches two bits of control bits for controlling the state of the board and five bits of address bits of the board ID. As shown in FIG. 5, the 1Q-2Q terminals output 2 bits of control bits, the 3Q-7Q outputs 5 bits of board ID, and the 8Q terminal is not used. The setting unit 41 performs a function of setting the control channel S-ch data.

The parity check unit 42 generates and outputs a parity bit by checking the control channel S-ch data output from the setting unit 41. 6 shows the configuration of the parity generating unit 42, which may be configured as an exclusive oar gate 61-68. The parity generator 42 generates odd parity, and generates odd parity by checking the number of " 1 " of the control bit and board ID information.

The control channel generator 43 adds the parity generated by the parity generator 42 to the control information output from the setting unit 41, converts the parallel control channel S-ch data into serial data, and outputs the stream data. 7 shows the configuration of the control channel generator 43. The shift register 71 is an 8-bit parallel control channel S-ch composed of 2 bits of control bits, 5 bits of board ID and 1 bit of parity. Input data and convert to serial stream data by ASTCLK. The flip-flops 73-74 are cleared and preset by signals output from the s1 terminal of the shift register 71, and the control channel S is serially converted to the shift register 71 in synchronization with the ASTCLK and output. -ch Print the data.

Looking at the operation of the present invention with reference to the configuration of Figures 4-7, the master board A or master board B of the global bus system determines that the transmit (TX) and receive (RX) states are abnormal on the global bus. In other words, if an error condition occurs in a large amount, the state of the global bus is checked through the control channel S-ch. When outputting the control channel S-ch stream from the master board, the controller of the master board writes the control bits C1 and C2 and addresses A1 to A5 for the corresponding board IDs in the setting unit 41. Addresses A1-A5 of the control bits C1 and C2 and the corresponding board IDs are shown in Table 1 below.

Table 1 Control bit configuration of corresponding control channel S-ch stream

Assuming the board ID of a specific board on the global bus is OX20, the board ID addresses A1-A5 become "10100". When the control bits C1 and C2 are "00", "00001001" is written to D31-D24 of the setting section 41. Here, the D24 bit is used as the S1 control value of the shift register 71 of the control channel product 43. At initialization, it is set to "1". At this time, if the board having the above and the board ID is operated in an abnormal state, the master board sets "OX09" as described above in the setting unit 41. Then, the setting unit 41 outputs control bits C1 and C2 through the 1Q-2Q terminals, and outputs board ID addresses A1 to A5 through the 3Q-7Q terminals. The parity generator 42 generates an parity bit PRTY by exclusively ORing the control bits and the board ID address bits outputted through the 1Q-7Q terminals of the setting unit 41. The parity bit PRTY generated at this time becomes odd parity as described above.

The shift register 71 of the control channel generator 43 includes control bits C1 and C2 output from the 1Q-7Q terminals of the setting unit 41, board ID addresses A1-A5, and parity bits PRTY output from the parity generator 42. Input parallel data of 8 bits. At this time, since the shift register 71 connects the 8Q terminal of the setting unit 41 to the S1 terminal, the 8-bit C1-C2, A1-A5 and PRTY data as described above are paralleled by the output of 8Q applied to the S1 terminal. The data is loaded in parallel in synchronization with the ASTCLK and shifted to output a serial data stream through the qh terminal. The control channel S-ch data serially converted at the qh terminal of the shift register 71 is transmitted on the global bus in synchronization with the ASTCLK through the flip-flops 73 and 74.

Then, the processor boards connected on the global bus receive the control channel S-ch data, convert the data into parallel data, decode the same, and analyze the control bits C1-C2 when the board ID address A-A5 is its own ID. The corresponding control function will be performed. In this case, when the control bits C1 to C2 are "01", the processor board having the corresponding board ID address disables the output enable terminal of the TX driver transmitting to the global bus. Blocks global bus transfers from the failing processor board.

As described above, in a system in which a plurality of processor boards are connected to a global bus to transmit information, it is possible to quickly deal with a global bus failure and to selectively control one of the boards connected to the global bus. have. As a result, if a particular processor board fails in a global bus system, the processor board can be isolated from the bus, improving system performance and improving global bus maintenance.

1 is a diagram showing a general configuration of a system employing a global bus.

2 is a diagram illustrating arbitration timing of a conventional global bus system.

3 illustrates a configuration of a control channel defining states of processor boards in accordance with the present invention.

4 is a diagram illustrating a configuration of a circuit for transmitting a control channel in a global bus system according to the present invention.

5 is a diagram showing the configuration of the setting section in FIG.

6 is a diagram showing the configuration of the parity generation unit in FIG.

FIG. 7 is a diagram showing the configuration of the control channel generation unit in FIG.

Claims (1)

In a bus system comprising a plurality of processor boards are commonly connected to the bus, the master board for controlling the bus right of the processors, A control unit for generating control bits indicating the state of the processor board and address bits which are identification information of the processor board, a buffer for storing the control bits and the address bits, and a parity bit by examining the control bits and the address bits output from the buffer. And means for receiving control channel information from the buffer and address bits and the parity bits output from the buffer, receiving the control channel information, converting the control channel information into a serial data stream, and outputting the control channel information to the bus. With the master board Means for parallel-converting control channel information of a serial stream connected to the bus, inspecting board identification information of the parallel-converted control channel information, and controlling the corresponding function by checking the self-identification information temporary control bits. With processor boards configured, The board isolation circuit of the bus system, characterized in that to isolate the processor board in the abnormal state by analyzing the state of the processor boards in the master board.