KR100372656B1 - Metal line of semiconductor device and method for forming the same - Google Patents
Metal line of semiconductor device and method for forming the same Download PDFInfo
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- KR100372656B1 KR100372656B1 KR1019950054638A KR19950054638A KR100372656B1 KR 100372656 B1 KR100372656 B1 KR 100372656B1 KR 1019950054638 A KR1019950054638 A KR 1019950054638A KR 19950054638 A KR19950054638 A KR 19950054638A KR 100372656 B1 KR100372656 B1 KR 100372656B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/091—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
Abstract
Description
본 발명은 반도체 소자의 제조공정에 관한 것으로서, 특히 금속배선의 측면으로의 노치 및 동공의 형성을 방지하는 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device, and more particularly, to a method for forming a metal wiring of a semiconductor device for preventing the formation of notches and holes on the side of the metal wiring.
금속배선은 반도체 소자에서 반도체의 도핑된 영역과 전도막을 전기적으로 연결시켜 주는 역할을 하는 배선으로서, 불순물 이온이 주입된 폴리실리콘이나 알루미늄이 주로 사용되고 있다. 또한, 열적인 안정성과 집적도의 증가로 인한 낮은 저항성을 이유로 전이금속과 실리콘의 화합물인 실리사이드가 금속배선으로서의 사용이 점점 증대되고 있다.Metal wiring is a wiring that electrically connects the doped region of the semiconductor and the conductive film in the semiconductor device, and polysilicon or aluminum implanted with impurity ions is mainly used. In addition, the use of silicide, which is a compound of transition metal and silicon, as metal wiring is increasingly increasing because of low resistance due to thermal stability and increased density.
이러한 금속배선을 형성하기 위한 방법으로는 물리적인 증착법인 스퍼터링법과 화학적인 증착법인 화학기상증착법이 주로 사용된다.As a method for forming the metal wiring, sputtering, which is a physical vapor deposition, and chemical vapor deposition, which is a chemical vapor deposition, are mainly used.
일반적으로 금속배선 패턴은 금속막을 하부의 절연막 전면에 증착한 후, 감광막 마스크를 이용하여 식각하여 제거하는 방법에 의하여 형성된다.In general, the metal wiring pattern is formed by depositing a metal film on the entire surface of the lower insulating film, and then etching and removing the metal film using a photosensitive film mask.
이러한 금속배선 중, 알루미늄은 반도체 소자의 배선공정에서 그 사용빈도가 높은데, 상기 알루미늄막에 감광막을 도포하여 마스크를 형성하다 보면, 감광막의 노광시 알루미늄막에서 반사된 빛에 의하여 노광이 되지 말아야 할 감광막의 소정 부분이 노광되어 감광막 마스크 패턴은 원래의 의도한 설계대로 되지 못하는 경우가 발생하였다. 이는 결과적으로 금속배선의 패턴에 영향을 주어 금속배선이 부분적으로 네킹되거나, 서로 단락되는 문제를 유발시킬 수 있는 소지가 되었다.Among these metal wires, aluminum is frequently used in the wiring process of semiconductor devices. When a photosensitive film is applied to the aluminum film to form a mask, the aluminum should not be exposed by the light reflected from the aluminum film. When a predetermined portion of the photoresist film is exposed, the photoresist mask pattern may not be as originally intended. As a result, the metal wires may be partially necked or shorted with each other by affecting the pattern of the metal wires.
또한, 알루미늄 막의 노출되는 입계(grain boundary)에는 많은 빈 격자점(vacancy)이 존재하는데, 이 격자점에는 알루미늄막과 후속공정에서 알루미늄막 위에 형성될 윗층과의 열팽창계수 차이에 의하여 알루미늄으로 응력이 전이 되어 노치 및 동공이 발생하는 문제점이 존재한다.In addition, there are many vacancy points at the exposed grain boundary of the aluminum film, which is stressed by the aluminum due to the difference in the coefficient of thermal expansion between the aluminum film and the upper layer to be formed on the aluminum film in a subsequent process. There is a problem that transitions occur and notches and pupils occur.
상기한 문제점을 해결하기 위하여 알루미늄 입계에 형성된 빈 격자점을 채워줄 수 있고, 알루미늄 막에 비하여 빛의 흡수도가 높으면서 낮은 저항을 갖는 Ti/TiN이중층의 반사 방지막을 상기 알루미늄 막위에 증착한 다음, 금속배선 패턴을 형성하는 방법이 사용되고 있는데, 첨부한 도면 제 1 도는 이러한 반사 방지막이 알루미늄 막 위에 형성된 금속배선막의 단면도로서, 미도시된 반도체 기판의 상부에 절연막이 형성되고, 절연막(1) 위에는 알루미늄막(2)과 Ti/TiN막(3)의 금속배선 패턴이 형성된다.In order to solve the above problems, it is possible to fill the empty lattice points formed in the aluminum grain boundary, and the anti-reflection film of the Ti / TiN double layer having a higher resistance to light and lower resistance than the aluminum film is deposited on the aluminum film, and then A method of forming a wiring pattern is used. FIG. 1 is a cross-sectional view of a metal wiring film in which such an anti-reflection film is formed on an aluminum film. An insulating film is formed on a semiconductor substrate, not shown, and an aluminum film is formed on the insulating film 1. A metal wiring pattern of (2) and the Ti / TiN film 3 is formed.
도면에서 알 수 있는 것처럼, 반사 방지막은 금속막 패턴의 형성시 감광막을 투과한 빛을 흡수하여 원하지 않는 부위의 감광막이 노광되는 것을 방지해 주는 역할을 하는 동시에 알루미늄 막(2) 상부 표면의 빈 격자점을 채워주므로써, 노치(notch) 및 동공(void)의 발생을 방지하기 위하여 형성되었다.As can be seen from the figure, the anti-reflection film absorbs the light passing through the photoresist film during formation of the metal film pattern, thereby preventing exposure of the photoresist film at an undesired area and at the same time, an empty lattice on the upper surface of the aluminum film 2. By filling the dots, it was formed to prevent the occurrence of notches and voids.
그러나, 이 방법 또한 상기 반사 방지막과의 열팽창계수 차이로 인하여 발생하는 응력 때문에 만족할 만한 성과를 거두지 못하고 있는 실정이다.However, this method also has not achieved satisfactory performance due to the stress generated by the difference in thermal expansion coefficient with the anti-reflection film.
따라서, 본 발명의 목적은 금속배선막 위에 열팽창계수의 차이에 의하여 발생한 응력이 알루미늄의 금속배선막에 직접 인가되는 것을 막기 위한 충격 흡수 재료인 복합재료를 이용하므로써, 금속배선에서의 노치 및 동공의 발생 문제를 해결할 수 있는 금속배선과 그것의 형성방법을 제공하기 위한 것이다.Accordingly, an object of the present invention is to provide a notch and pupil in a metal wiring by using a composite material which is a shock absorbing material for preventing the stress generated by the difference in thermal expansion coefficient on the metal wiring film from being directly applied to the metal wiring film of aluminum. An object of the present invention is to provide a metal wiring and a method of forming the same that can solve a generation problem.
이와 같은 목적은 달성하기 위한 본 발명의 금속배선 형성방법은 반도체 기판 상부에 형성된 절연막 위에 알루미늄 금속막을 소정 두께로 증착하는 단계; 상기 알루미늄 금속막 위에 후속공정에서 덮여지는 막과의 열팽창계수 차이에 의한 응력의 흡수하기 위한 충격 흡수막을 소정 두께로 증착하는 단계; 상기 충격 흡수막 위에 빛의 반사를 방지하는 반사 방지막을 증착하는 단계; 상기 반사 방지막 위에 감광막 마스크 패턴을 형성하여 노출된 반사 방지막, 알루미늄 복합재료막 및 알루미늄막을 식각하여 금속배선패턴을 형성하는 단계를 포함하는 것을 특징으로 한다.The metal wire forming method of the present invention for achieving the above object comprises the steps of depositing an aluminum metal film to a predetermined thickness on the insulating film formed on the semiconductor substrate; Depositing a shock absorbing film having a predetermined thickness on the aluminum metal film for absorbing stress due to a difference in coefficient of thermal expansion with a film covered in a subsequent process; Depositing an anti-reflection film to prevent reflection of light on the shock absorbing film; And forming a metal wiring pattern by etching the exposed anti-reflection film, the aluminum composite material film, and the aluminum film by forming a photoresist mask pattern on the anti-reflection film.
본 발명의 다른 목적을 달성하기 위한 반도체 소자의 금속배선은 반도체 기판위에 형성된 절연막 위에 알루미늄의 금속배선막과 상기 알루미늄 금속배선막 위에 노광시 빛의 방지를 막기 위한 반사방지막이 적층된 반도체 소자의 금속배선에 있어서, 상기 알루미늄 금속배선막과 반사방지막의 사이에 상기 알루미늄 막 위에 형성되는 다른 막과의 열팽창 계수 차이에 의한 응력을 흡수하는 충격 흡수막을 구비한 것을 특징으로 한다.The metal wiring of the semiconductor device for achieving the another object of the present invention is a metal of the semiconductor device in which a metal wiring film of aluminum on the insulating film formed on the semiconductor substrate and an antireflection film for preventing the light when exposed to the aluminum metal wiring film is laminated. The wiring is characterized in that a shock absorbing film is provided between the aluminum metal wiring film and the anti-reflection film to absorb stress due to a difference in coefficient of thermal expansion between the other film formed on the aluminum film.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 설명한다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
첨부한 도면 제 2 도는 본 발명의 실시예에 따른 금속배선의 측면에서 발생하는 노치나 동공의 발생을 방지할 수 있는 금속배선 형성방법을 설명하는 공정 흐름도이다.2 is a flowchart illustrating a method of forming metal wirings capable of preventing the generation of notches or pupils generated from the side surfaces of the metal wirings according to an embodiment of the present invention.
먼저, (가)도면에 도시한 바와 같이, 반도체 기판(미도시)위에 형성된 절연막(1) 상에 알루미늄(2)의 금속배선을 스퍼터링법에 의하여 소정 두께로 증착한다. 증착된 알루미늄막(2) 위에 충격 흡수재인 알루미늄-그래파이트(Al-graphite)의 복합재료(3)를 스퍼터링 법에 의하여 10 내지 70Å의 두께범위로 증착한다. 상기 Al : 그래파이트의 조성비는 50 : 50으로 하는 것이 바람직하다.First, as shown in (a), a metal wiring of aluminum 2 is deposited to a predetermined thickness on the insulating film 1 formed on a semiconductor substrate (not shown) by the sputtering method. On the deposited aluminum film 2, a composite material 3 of aluminum-graphite, which is an impact absorber, is deposited in a thickness range of 10 to 70 kPa by the sputtering method. It is preferable that the composition ratio of Al: graphite is 50:50.
다음으로, 상기 알루미늄 복합재료막(3) 위에 TiN의 반사 방지막(4)을 스퍼터링법에 의하여 소정 두께만큼 형성한다.Next, a TiN antireflection film 4 is formed on the aluminum composite film 3 by a sputtering method to a predetermined thickness.
이 후, 상기 반사 방지막(4) 위에 감광막을 소정 두께로 도포하고, 노광 및 현상하여 감광막 마스크를 형성한 다음, 노출된 반사 방지막(4), 알루미늄 복합재료막(3) 및 알루미늄 금속막(2)을 식각하여 제거한 다음, 감광막을 제거하므로써 (나)와 같은 금속배선 패턴을 형성한다.Subsequently, a photoresist film is applied on the antireflection film 4 to a predetermined thickness, exposed and developed to form a photoresist mask, and then the exposed antireflection film 4, the aluminum composite material film 3, and the aluminum metal film 2 ) Is removed by etching, and then the photoresist film is removed to form a metal wiring pattern as shown in (b).
상기한 방법으로 형성되는 알루미늄 복합재료막의 개략적인 미세구조를 제 3 도에 도시하였다.A schematic microstructure of the aluminum composite film formed by the above method is shown in FIG.
도면에서 기지(matrix) 입자는 알루미늄 금속이고,는 그래파이트 입자로서, 그래파이트 입자는 알루미늄 기지에 고용되지 않으므로, 알루미늄 기지에 그래파이트 입자가 균일하게 분산되는 것을 알 수 있다.Matrix particles in the drawings are aluminum metal, Is a graphite particle, and since graphite particles are not dissolved in the aluminum matrix, it can be seen that graphite particles are uniformly dispersed in the aluminum matrix.
상기 미세구조는 알루미늄-그래파이트 복합재료막의 증착을 위하여 스퍼터링 장치에서 타겟으로 사용되는 알루미늄-그래파이트 복합재료에서도 동일하게 나타난다.The microstructure is the same in the aluminum-graphite composite material used as a target in the sputtering apparatus for the deposition of the aluminum-graphite composite film.
본 발명의 다른 실시예로는 층격흡수재를 Al-Pb의 합금을 사용하는 것이다.Another embodiment of the present invention is to use an Al-Pb alloy as the layered absorber.
이 방법 역시 제 2 도와 같은 순서로서 진행되므로, 제 2 도를 참조하여 설명하면 다음과 같다.Since this method also proceeds in the same order as in FIG. 2, it will be described with reference to FIG.
먼저, (가)도면에 도시한 바와 같이, 반도체 기판(미도시)위에 형성된 절연막(1) 상에 알루미늄(2)의 금속배선을 스퍼터링법에 의하여 소정 두께로 증착한다. 증착된 알루미늄막(2) 위에 충격 흡수재인 알루미늄-납(Al-Pb)의 혼합막(3)을 스퍼터링 법에 의하여 30 내지 70Å 두꼐범위로 증착한다. 이때, 상기 Al : Pb의 체적분율은 50 : 50으로 하는 것이 바람직하다.First, as shown in (a), a metal wiring of aluminum 2 is deposited to a predetermined thickness on the insulating film 1 formed on a semiconductor substrate (not shown) by the sputtering method. On the deposited aluminum film 2, a mixed film 3 of aluminum-lead (Al-Pb), which is an impact absorbing material, is deposited in a thickness range of 30 to 70 kPa by the sputtering method. At this time, the volume fraction of Al: Pb is preferably set to 50:50.
다음으로, 상기 알루미늄과 납의 혼합막(3) 위에 TiN의 반사 방지막(4)을 스퍼터링법에 의하여 소정 두께만큼 형성한다.Next, a TiN antireflection film 4 is formed on the mixed film 3 of aluminum and lead by a sputtering method to a predetermined thickness.
이 후, 상기 반사 방지막(4) 위에 감광막을 소정 두께로 도포하고, 노광 및현상하여 감광막 마스크를 형성한 다음, 노출된 반사 방지막(4), 알루미늄과 납의 혼합막(3) 및 알루미늄 금속막(2)을 식각하여 제거한 다음, 감광막을 제거하므로써 (나)와 같은 금속배선 패턴을 형성한다.Subsequently, a photoresist film is coated on the antireflection film 4 to a predetermined thickness, exposed and developed to form a photoresist mask, and then the exposed antireflection film 4, a mixed film 3 of aluminum and lead, and an aluminum metal film ( 2) is etched and removed, and then the photoresist film is removed to form a metal wiring pattern as shown in (b).
상기한 방법으로 형성되는 알루미늄과 납의 합금막은 상온에서 고용도가 매우 작기 때문에 제 3 도의 (나)에 도시한 미세구조도에서 알 수 있는 것처럼, 알루미늄 기지에 납입자(로 표시)가 고루 분산되어 있다. 이 때 납은 거의 순수한 상태로 존재하므로 후속공정에서 증착되는 상부막과의 열팽창 계수의 차이에 의하여 인가되는 응력을 쉽게 흡수하여 노치 및 동공의 발생을 방지하여 준다.Since the alloy film of aluminum and lead formed by the above method has a very small solid solution at room temperature, as shown in the microstructure diagram shown in FIG. Are evenly distributed. At this time, since the lead is almost pure, the stress applied by the difference in the coefficient of thermal expansion with the upper film deposited in the subsequent process is easily absorbed to prevent the generation of notches and pupils.
상기 제 2 실시예에서 충격 흡수만을 위해서는 납의 막만을 사용하는 것이 더욱 효과적이지만은 여기에서 알루미늄과 납 혼합막을 사용하는 이유는 그 위에 형성되는 반사 방지막과의 응착(adhesion)특성을 유지시키기 위한 것이다.Although it is more effective to use only a lead film only for shock absorption in the second embodiment, the reason why an aluminum and lead mixed film is used here is to maintain adhesion characteristics with the antireflection film formed thereon.
이상에서 설명한 바와 같이, 본 발명의 반도체 소자의 금속배선 형성방법은 후속공정시 열팽창 계수 차이에 의하여 발생하는 응력을 방지하기 위하여 알루미늄막과 반사 방지막 사이에 알루미늄과 그래파이트의 복합재료를 사용하거나 알루미늄과 납과의 혼합막을 사용하므로써, 응력의 영향을 방지할 수 있다. 따라서, 본 발명은 금속배선막에서 노치 및 동공의 발생을 억제하여 소자의 신뢰성을 향상시키는 효과를 제공한다.As described above, the metal wiring forming method of the semiconductor device of the present invention uses a composite material of aluminum and graphite or between the aluminum film and the anti-reflection film in order to prevent the stress caused by the difference in thermal expansion coefficient during the subsequent process By using a mixed film with lead, the influence of stress can be prevented. Accordingly, the present invention provides the effect of suppressing the generation of notches and pupils in the metal wiring film to improve the reliability of the device.
여기에서는 본 발명의 특정 실시예에 대해서 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로이해할 수 있다.Although specific embodiments of the present invention have been described and illustrated herein, modifications and variations can be made by those skilled in the art. Accordingly, the following claims may be understood to include all modifications and variations as long as they fall within the true spirit and scope of the present invention.
제 1 도는 종래의 실시예에 따른 금속배선 패턴의 단면도1 is a cross-sectional view of a metallization pattern according to a conventional embodiment.
제 2 도는 본 발명의 실시예에 따른 금속배선 패턴의 공정 흐름도.2 is a process flow diagram of a metallization pattern in accordance with an embodiment of the present invention.
제 3 도는 제 2 도의 실시예에 따른 충격 흡수막의 미세구조도.3 is a microstructure of the shock absorbing film according to the embodiment of FIG.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 절연막 2 : 알루미늄막1 insulating film 2 aluminum film
3 : 충격 흡수막 4 : 반사 방지막3: shock absorption film 4: antireflection film
Claims (9)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950054638A KR100372656B1 (en) | 1995-12-22 | 1995-12-22 | Metal line of semiconductor device and method for forming the same |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950054638A KR100372656B1 (en) | 1995-12-22 | 1995-12-22 | Metal line of semiconductor device and method for forming the same |
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| KR100372656B1 true KR100372656B1 (en) | 2003-04-26 |
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