KR100368333B1 - Method for managing history information of circuit product - Google Patents

Abstract

PURPOSE: A method for managing history information of a circuit product is provided to manage history information of a circuit product using a chip enable signal and a serial data input/output function in the case that the history information of a circuit product is stored in a memory of a system including many circuit products simultaneously. CONSTITUTION: A CPU(24) outputs a chip enable signal and converts the product history memory(23) into an operable state. An address signal, a read command, and a clock pulse are applied to the product history memory(23). Product history information stored in the product history memory(23) is read adapted to a synchronization of the clock pulse and managed. The CPU(24) applies the chip enable signal to an interface unit(21) and stops a matching operation with respect to asynchronous serial data being inputted and output through a connector.

Description

How to manage history information of circuit products

The present invention relates to a method of managing history information of a circuit product, and more particularly, to a method of managing history information of a circuit product that enables the management of history information of each circuit product using a serial data input / output function in a system in which a plurality of circuit products are configured at the same time. It is about.

In general, in the past, the history management of each circuit product constituting the exchanger or other system, that is, the product history information such as serial number, product name, manufacturing date, etc. is attached to the outside of the circuit product by a bar code, or The product history information can be read and used when needed.In this case, if the product history information is stored in a barcode, the product history information is read using a barcode scanner by reading the product history information. If the product history information is stored in the internal memory, the product history information could be read by reading the information stored in the memory by using a circuit configured to manage the product history information. .

However, when a plurality of circuit products are interconnected to form a system, if the history information of each circuit product is stored in a bar code, the history information of each product cannot be read by a barcode scanner, so most of the circuit products are stored in the internal memory. do.

As described above, when the history information of each circuit product is stored in the internal memory, the configuration of the circuit for managing product history information for managing the history information of the circuit product is shown in FIG. 11), an address decoder 12, a buffer 13, a plurality of serial / parallel conversion sections 14, and a plurality of product history memory sections 15, respectively.

The CPU 11 applies a control command for retrieving the product history information for each product history memory unit 15 and the address signal of each serial / parallel conversion unit 14 to the address decoder 12, and the buffer 13 The product history information that is authorized from) is transmitted to the upper processor or used by itself.

The address decoder 12 controls the buffer 13 and the corresponding serial / parallel converter 14 in accordance with an address signal and a control command applied from the CPU 11.

The buffer 13 temporarily stores parallel data applied from the serial / parallel converter 14 and applies the stored parallel data to the CPU 11 under the control of the address decoder 12.

Each serial / parallel converter 14 converts serial data applied from the product history memory unit 15 into parallel data under the control of the address decoder 12 and applies the converted parallel data to the buffer 13. .

Each product history memory unit 15 stores product history information such as a serial number, a product name, and a manufacturing date of a corresponding circuit product.

The product history information retrieval operation in the history information management circuit of the conventional circuit product configured as described above is as follows.

For example, in a system having a plurality of product history memory units 15 each storing history information of a circuit product, the product history information of a specific circuit product is stored in the upper processor or the CPU 11 during operation of the system. If necessary, the CPU 11 reads the history information of the necessary circuit products and transfers them to the upper processor or uses them on its own. First, the CPU 11 needs the upper processor or itself through the address bus and the data bus. When the control command for retrieving the history information of the circuit product and the address signal of the serial / parallel conversion unit 14 are applied to the address decoder 12, the address decoder 12 is applied to the address signal applied from the CPU 11; After selecting one serial / parallel conversion section 14 corresponding thereto, the serial / parallel conversion section 14 selects the corresponding serial / parallel conversion section 14 to the corresponding product history memory section 15. (READ) is applied to the command.

Accordingly, the product history memory unit 15 applies pre-stored product history information to the serial / parallel conversion unit 14 according to a read command applied from the serial / parallel conversion unit 14. Since the information is applied in the form of serial data, the serial / parallel conversion section 14 converts the serial data applied from the product history memory section 15 into parallel data and then converts the converted parallel data into the address decoder 12. It applies to the buffer 13 according to control.

At this time, the buffer 13 temporarily stores the parallel data applied from the serial / parallel converter 14 and applies the parallel data to the CPU 11 under the control of the address decoder 12.

Accordingly, the CPU 11 receives parallel data, that is, product history information from the buffer 13, and transmits the same to the upper processor or may use the same.

However, since the history information management of the conventional circuit product uses a method of reading the corresponding product history memory unit 15 through the serial / parallel conversion unit 14, a separate buffer 13 or a serial / parallel conversion unit ( 14) must be added, and an address decoder 12 is required to control this, which complicates the circuit configuration.

As described above, the history information management of the conventional circuit product uses a general memory reading method, so that a separate device is required, and thus, a circuit configuration is complicated and a manufacturing cost for configuring the circuit product is high.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to effectively manage each product history information when the history information of the circuit products is stored in the product history memory unit in a system in which a plurality of circuit products are configured at the same time. The chip enable signal and serial data input / output functions are used to manage the history information of the circuit product.

1 is a block diagram illustrating a circuit for managing history information of a conventional circuit product.

2 is a block diagram of a circuit for managing history information of a circuit product according to the present invention;

Explanation of symbols on the main parts of the drawings

21: interface unit 22: inverter

23: product history memory section 24: CPU

A feature of the present invention for achieving the above object is, in the history information management method of a circuit product for storing and managing history information for each circuit product configured in the system at the same time in the product history memory unit, predetermined in the CPU Outputting a chip enable signal to convert the product history memory unit into an operable state; Applying a predetermined address signal, a read command and a clock pulse to the product history memory unit; The present invention provides a method for managing history information of a circuit product, the method including managing product history information stored in the product history memory unit in synchronization with the clock pulse and using the same as necessary.

The above-described method for managing history information of a circuit product includes outputting a predetermined chip enable signal from the CPU to switch the product history memory unit to an operable state, and simultaneously applying the chip enable signal to an interface unit, thereby providing a connector. The method may further include stopping the matching operation on the asynchronous serial data input / output through the terminal.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In the system having a serial data input / output function according to the present invention, the configuration of a circuit for managing history information of a circuit product is shown in FIG. 2 as shown in FIG. 2. A product history memory section 23 and a CPU 24 are provided.

The interface unit 21 matches serial data input / output through the connector to the CPU 24.

The inverter 22 inverts the chip enable signal applied from the CPU 24 and applies the inverted chip enable signal to the chip enable port / CE of each product history memory unit 23.

Each product history memory unit 23 stores product history information such as a serial number, a product name, and a manufacturing date of a corresponding circuit product.

The CPU 24 controls the operation state of the interface unit 21 and each of the product history memory units 23 to perform serial data communication through the corresponding interface unit 21, or the product stored in the product history memory unit 23. It manages the history information.

The product history information retrieval operation in a circuit for managing history information of a circuit product in a system having a serial data input / output function according to the present invention configured as described above will be described in detail as follows.

First, the CPU 24 determines a state of operation of the interface unit 21 and the product history memory unit 23 by generating a chip enable signal having a 'high' or 'low' level and outputting the generated chip enable signal. If the CPU 24 generates and outputs a chip enable signal having a 'low' level, the chip enable signal having a 'low' level is applied to the interface unit 21 and the inverter 22. At this time, the interface unit 21 is operable according to the chip enable signal of the 'low' level applied from the CPU 24, the serial data input / output port (SI / SO) of the CPU 24 Asynchronous serial data communication is performed by interfacing the input / output serial data, respectively, and the corresponding inverter 22 inverts the 'low' level chip enable signal applied from the CPU 24 to 'high'. Level enable chip enable signal is applied to the chip enable port (/ CE) of the product history memory unit 23, the corresponding product history memory unit 23 is applied to the chip enable port (/ CE) Since the enable signal is at the 'high' level, the operation stops.

If the CPU 24 generates and outputs a chip enable signal having a 'high' level, the chip enable signal having a 'high' level is applied to the interface unit 21 and the inverter 22. At this time, the interface 21 is in the operation stop state because the chip enable signal applied from the CPU 24 is a 'high' level, the corresponding inverter 22 of the 'high' level applied from the CPU 24 The chip enable signal is inverted to apply a chip enable signal having a 'low' level to the chip enable port (/ CE) of the product history memory unit 23, and the corresponding product history memory unit 23 is a chip enable port. Since the chip enable signal applied to (/ CE) is 'low' level, the chip enable signal is switched to an operational state.

At this time, the CPU 24 applies an address signal and a read command to the address port ADDR of the corresponding product history memory unit 23 through the serial data output port SO in order to read the history information of the circuit product. In addition, when a clock pulse is generated and applied to the clock port CLK of the corresponding product history memory unit 23, the corresponding product history memory unit 23 stores the history of circuit products stored therein according to the applied address signal. Information is synchronized with a clock pulse to be applied to the serial data input port SI of the CPU 24 through the data port DATA.

Accordingly, the CPU 24 receives serial data, that is, history information of the circuit product from the product history memory unit 23, and transfers the data to the upper processor or may use the same.

On the other hand, when the chip enable signal is distinguished and used for each product history memory unit 23 in the CPU 24, the history information of a plurality of circuit products can be managed as one CPU 24.

The CPU 24 outputs an address signal and a read command through the serial data output port SO in the program. The address port ADDR of the product history memory section 23 is used in a program using a routine such as "PUTCHAR". The address signal and the read command can be applied, and at this time, the product history memory unit 23 executes a routine such as "GETCHAR" of the program in accordance with the applied address signal. It is applied to the serial data input port SI of the CPU 24 through the data port DATA.

As described above, when the CPU 24 generates and outputs a chip enable signal for converting the product history memory unit 23 in which the history information of the circuit product is stored into an operable state, the corresponding product history memory unit is output. 23 is switched to an operable state, and at this time, an address signal, a read command, and a clock pulse are applied to read the history information of the circuit products required by the CPU 24, and the corresponding product history memory section 23 is applied. The product history information stored in is read in synchronization with the clock pulse.

In addition, since the present invention uses an asynchronous signaling method using a serial data input / output port (SI / SO) provided by the CPU 24, a corresponding product is not required without a separate protocol conversion or a separate device configuration for serial data communication. The history information of the circuit products stored in the history memory section 23 can be read and used as necessary.

As described above, in the present invention, when the history information of the circuit product is stored in the product history memory unit, a plurality of circuit products are managed by managing the history information of the circuit product using the chip enable signal and the serial data input / output function. At the same time, it is possible to effectively manage each product history information in the system.

Claims (2)

In the history information management method of a circuit product for storing and managing the history information for each circuit product that is configured at the same time a plurality of systems in the product history memory unit, Outputting a predetermined chip enable signal from a CPU to convert the product history memory unit into an operable state; Applying a predetermined address signal, a read command and a clock pulse to the product history memory unit; And managing the product history information stored in the product history memory unit in synchronization with the clock pulses to use them as needed. The method of claim 1, Matching operation for asynchronous serial data input / output through a connector by outputting a predetermined chip enable signal from the CPU to switch the product history memory unit to an operable state and simultaneously applying the chip enable signal to an interface unit. The method of claim 1, further comprising the step of stopping the operation.