KR100366999B1 - ADSL Subscriber Multiplexing interface for ATM Switching System - Google Patents

Abstract

The present invention relates to an ADSL subscriber multiplexing matching module of an ATM switching system configured to accommodate a subscriber using an asymmetric digital subscriber line (ADSL) in an ATM switching system. The present invention relates to a local switching subsystem and a central switching service system. In the ATM switching system, it is matched with one of the various subscriber matching modules of the local switching service system. The ADSL subscriber matching module handles an ATM cell multiplexer, four ATM layer processors per module, and four ADSL subscribers per board. It consists of 16 board ADSL subscriber processing unit, and is connected to subscriber switch network module with IMI for data connection and LTSI for clock connection to provide asymmetric ATM service to ADSL subscribers. Can connect up to 256 ADSL subscribers and provides high speed to remote ADSL subscribers Has the effect of providing data services.

Description

ADSL Subscriber Multiplexing interface for ATM Switching System

The present invention provides an asymmetric digital subscriber line (hereinafter referred to as ADSL) of an ATM switching system configured in an ATM switching system to provide various ATM services to an asymmetric digital circuit subscriber in an asynchronous transmission mode (ATM) switching system. It relates to a subscriber registration module.

In the conventional ADSL subscriber multiplexing matching module, different ADSL subscriber processing devices are used for ADSL subscribers having different speeds. The ADSL subscriber multiplexing matching module can be connected only outside the exchange system as a bulky equipment and not mounted in the exchange system.

Therefore, there is a problem that can not be controlled by the maintenance control module inside the system as the ADSL subscriber processing device according to the speed of the ADSL subscriber must be used and connected outside the switching system.

Meanwhile, as a prior patent, the US patent “Customer premises ADSL signal distribution arrangement (Apri 18, 1995, registration number US5408260) connects a plurality of ADSL terminals to a coaxial cable and uses a different frequency band from a cable TV to distribute signals in a subscriber's home. In order to provide convenient facilities, it consists of Passive Coupler (PC), SummingPoint (SP), ADSL Terminal Unit (ATU), Service Module (SM), and connects multiple ADSL terminals through coaxial cable to function as ADSL terminals in the SM. By performing the above, a plurality of ADSL terminals are connected to the coaxial cable, and the cable TV and the frequency band are different so that the service can be performed without relocating the wiring and signals in the subscriber's home, but the present invention provides an ADSL subscriber multiplexing matching module. There is a significant difference.

In order to solve the above problems, an object of the present invention is to provide an ADSL subscriber multiplexing matching module that can be mounted in an ATM switching system to accommodate subscribers using ADSL in an ATM switching system.

In order to achieve the above object, the present invention, STM-1, DS3, DS1, DS1E, ADSL subscriber to the subscriber switch network connecting the subscriber matching module, STM-1 and STM-4 relay line matching to connect the relay network to the subscriber switch network Module, subscriber switch network module which connects subscriber matching module, relay line matching module and subscriber control module to connect to switch network module, subscriber control that collects alarms of each module in local switching system and performs maintenance control and call connection control A plurality of local switching subsystems with modules, and a central switching subsystem for interconnecting the local switching subsystems and performing overall control of the system.

The present invention has an ADSL subscriber multiplexing module in an ATM switching system, which can accommodate ADSL subscribers of different speeds, and is configured in the same shape as a board used in an exchange system so as to be mounted in the switching system. The ADSL subscriber multiplexing matching module, which can be controlled by the maintenance control module inside the system, is constructed through the network.

1 is a block diagram of an ATM switching system according to the present invention;

2 is a block diagram of an ADSL subscriber multiplexing matching module to which the present invention is applied;

3 is a block diagram of an ADSL subscriber processing apparatus according to the present invention;

* Explanation of symbols for main parts of the drawings

1100, 1200: Local Switching Subsystem

1110, 1210: subscriber matching module 1111: ATM cell multiplexing device

1112: ATM layer processing apparatus

1113a to 1113d: ADSL subscriber processing device

1113a1: ADSL protocol processor 1113a2: ATM physical layer processor

1113a3: transmitting cell charging unit 1113a4: receiving cell processing unit

1113a5: central control unit 1113a6: control signal matching unit

1113a7: transceiver cell bus matching unit 1120, 1220: relay line matching module

1130, 1230: subscriber switch network module

1140, 1240: subscriber control module 2000: central switching subsystem

2100: network synchronizer module 2200: maintenance control module

2300: connection switch network module

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an ATM switching system according to the present invention, which is composed of one central switching subsystem 2000 and a plurality of local switching subsystems 1000.

The local switched subsystems 1100 and 1200 are STM-1 (155 Mbps) subscribers, DS3 (45 Mbps) subscribers, DS1 (1.5 Mbps) subscribers, DS1E (2 Mbps) subscribers, ADSL (8M-1M, 640 kbps to 64 kbps) subscribers. Subscriber matching module (1110, 1210), STM-1 (155Mbps) relay line, STM-4 (622Mbps) relay line connecting module (1120, 1220) and subscriber control module for connecting the subscriber switch network to the subscriber switch network Subscriber switch network modules (1130, 1230), which connect to the connected switch network module, collect the alarms of each module in the local switching subsystem, and the connection with the subscriber switch network is made through an internal module connection (IMI). The number of IMIs connected depends on the speed of the trunk line.

The central switching subsystem 2000 interconnects the local switching subsystems 1100 and 1200 and performs overall control of the system. The central switching subsystem 2000 generates a network synchronization clock for synchronization of the entire switching system network. Intermodule Timing Interface (IMTI) and Central Timing Clock (Interim Timing Interface) and Central Timing Clocks of the same period, respectively, for the network modules 1130 and 1230, the connected switch network module 2300, and the maintenance control module 2200, respectively. Signal Synchronizer Module 2100 for supplying Signal Interface (hereinafter referred to as CTSI), Connected Switch Network Module 2300 for interconnecting Subscriber Switch Networks and having a connection with a Maintenance Control Module, Maintenance Control Function of the entire Switching System And a maintenance control module 2200 for performing an operation management function, and the connection between each module and the connection switch network is made through the IMI.

2 is a block diagram of an ADSL subscriber multiplexing matching module to which the present invention is applied, and includes an ATM cell multiplexer 1111, an ATM layer processor 1112, and an ADSL subscriber processor 1113a to 1113d to accommodate 256 subscribers. It processes ATM cell and provides high speed data service to ADSL subscriber.

The ATM cell multiplexer 1111 transmits 234.74 Mbps differential signal serial data to and from a subscriber switch network module through an internal access module (IMI), receives a clock of 46.9494 MHz from the subscriber switch network module, It also communicates with the maintenance control module for central control.

The four ATM processors 1112a to 1112d communicate with each other via IMI as 234.74Mbps differential signal serial data, and multiplex the data to the subscriber switch network module to perform the reverse function.

The 46.9494 MHz clock received from the subscriber switch network module is synthesized, buffered, and supplied to the four ATM layer processing units 1112a to 1112d.

In addition, the function alarm signals AFUNA0 to AFUNA3 and the hernia alarm signals AOFFA0 to AOFFA3 of the ATM floor processor are input from the ATM floor processor as a logic high signal, and the hernia alarm signal Off_Alm and the function alarm signal are received. (Fun_Alm) is an alarm collector and outputs a logic high signal.

The ATM layer processing units 1112a to 1112d transmit and receive differential signal serial data of 234.74Mbps with the ATM cell multiplexer 1111 through a switch network module and an IMI, and the ADSL subscriber processing units 1113a to 1113d transmit and receive cell buses. And via a control signal bus.

The transmit / receive cell bus transmits the transmit cell 16-bit data TCELL0 to TCELL15 and the transmit cell start signal TSOC ^* indicating the start of the transmit cell to the ADSL subscriber processor, and receives the receive cell 16-bit data RCELL0 to RCELL15 16 ADSL subscriber processing devices receiving the cell start signal RSOC ^* indicating the start of the cell from the ADSL subscriber processing units 1113a to 1113d and receiving cell reception request signals CRREQ0 ^{* to} CRREQ15 ^* requesting reception of the cell. When received from the polling, if a certain order is reached, the ADSL subscriber processor requesting the reception of the cell transmits a cell reception permission signal (CRACK0 ^{* to} CRACK15 ^* ) to allow the reception of the cell.

If the received cell is an Operation Administration and Maintenance (hereinafter referred to as OAM) cell, it processes the operation maintenance function and sends a response OAM cell to the ADSL subscriber.

The address signal EA1 to EA11, the data signals ED0 to ED7, and the address signal indicating that the address signals are valid for accessing the DPRAM in the ADSL subscriber processing units 1113a to 1113d through the control signal bus are valid. Send and receive a signal EAS ^* , a data valid signal EDS ^* indicating that the data signal is valid, and a read / write signal ER ^* W specifying data read and write.

The main clock (23.4747 MHz) for synchronizing the clocks in the module and the cell bus clock (11.7373 MHz) for synchronizing the transmission and reception cell buses are supplied to the ADSL subscriber processing units 1113a to 1113d.

Also, the function alarm signals FUNA0 to FUNA15 and the hernia alarm signals OFFA0 to OFFA15 of the ADSL subscriber processing units 1113a to 1113d are input from the ADSL subscriber processing unit as a logic high signal, and the function alarm signal AFUNA is received. The and off alarm signal (AOFFA) is output as a logic high signal to the ATM cell multiplexer.

The ADSL subscriber processing apparatuses 1113a to 1113d receive the transmitting cell 16-bit data and the transmitting cell start signal from the ATM layer processing apparatus through the transmit / receive cell bus and receive the receiving cell 16-bit data and the receiving cell start signal to the ATM layer processing apparatus. send.

In addition, the cell reception request signal for requesting the reception of the cell is sent to the ATM processing apparatus, and the cell reception permission signal is received.

The control signal bus receives address signals, address valid signals, data valid signals, read / write signals, frequency clocks, and cell bus clocks from ATM layer processing devices, sends and receives data signals, and functions to match zero ports. An alarm signal and a hernia alarm signal are sent to the ATM floor processing apparatus.

3 is a block diagram of an ADSL subscriber processing apparatus according to the present invention, and is connected to an ATM layer processing apparatus through a transmission / reception cell and a control bus signal.

The central control unit 1113a1 includes a 32-bit processor that generates data signal lines, address signal lines, and control signal lines, buffers them, and supplies them to the local bus, and combines these signals to devices and registers belonging to each part of the subscriber matching device. It designates the address for the program and configures the ROM to store the program and the RAM for storing various data to control the whole ADSL subscriber processing device.

In addition, a clock generator of 49.152 MHz and 25 MHz is provided to buffer and divide them, and to supply them to the local bus 1113a8, the transmit cell processor 1113a3, and the receive cell processor 1113a4, at the time of power supply and manual reset by a reset switch. It generates a reset signal and supplies it to the local bus.

It also has serial input / output function and provides terminal connection function for debugging through RS-232 communication port.

In addition, the transmitting cell processing unit 1113a3 is connected to the local bus 1113a8, receives the 16-bit transmission cell from the transmitting / receiving cell bus matching unit 1113a7, converts it into 8 bits, and in the case of a point-to-point transmission cell, each subscriber immediately It transmits to the transmission cell packet, and in the case of point-to-multipoint transmission, converts the virtual path identifier (VPI) and the virtual channel identifier (VCI) to be converted and temporarily stored in the transmission cell packet, and outputs them to the ATM physical layer processor 1113a2. Have

The ATM physical layer processing unit 1113a2 is composed of four units, one for each subscriber, converts the parallel transmission cell received from the transmission cell PIP to serial processing, and performs the ATM physical layer processing to transmit to the ADSL protocol processing unit 1113a1, and receives from the ADSL protocol processing unit. One serial data cell is converted in parallel, and the ATM physical layer reception process is performed and outputted to the reception cell processor 1113a4.

It handles the functions according to the ATM physical layer standard and if there is no user cell, it automatically sends and receives idle cells and maintains connection with ADSL subscriber at all times.

The ADSL protocol processor 1113a1 is configured with four subscribers, one for each subscriber, and performs ADSL transmission on the serial data cell received from the ATM physical layer processor 1113a2 according to a modulation scheme, and outputs the ADSL downstream to the ADSL subscriber line. The ADSL upstream stream inputted from the ADSL subscriber line is subjected to ADSL reception processing and output to the ATM physical layer processing unit 1113a2.

The receiving cell processor 1113a4 is connected to the local bus, and analyzes the received cell inputted from the ATM physical layer processor 1113a2 in 8 bits, converts the received cell into 16 bits, temporarily stores the received cell in the receiving cell packet, and transmits and receives a cell bus matching unit ( 1113a7).

In addition, it has a test cell transmit packet and a test cell receive packet, and has a function of temporarily storing its own loopback test cell.

The transmit / receive cell bus matching unit 1113a7 forms a loopback path to send the test cell received from the receiving cell envelope unit to the transmitting cell control unit when performing its own loopback test under the control of the receiving cell control unit. Receives and buffers the receiving cell from the ATM layer processing apparatus through a transmit / receive cell bus and transmits the received cell to the transmitting cell control unit.

The control signal bus matching unit 1113a6 is connected to the local bus 1113a8 to connect 11 bits of local address signals, various control signals AS ^* , DS ^* , R ^* W, and 8 bits of data signals, and a control signal bus. It is connected to the ATM layer processing device to receive 11-bit address signals (EA1 to EA11) and various control signals (EAS ^* , EDS ^* , ER ^* W), and send and receive 8-bit data signals (ED0 to ED7). Both ports are configured to communicate with the ATM layer processor.

The main clock and the cell bus clock are supplied from the control signal bus, divided and controlled, and supplied to the transmitting cell processing unit 1113a3 and the receiving cell processing unit 1113a4 through the local bus.

As described above, the present invention, under the control of the maintenance control module in the ATM switching system, can be connected to 256 ADSL subscribers per ADSL subscriber multiplexing module, it is possible to provide a high-speed ATM data service to remote ADSL subscribers There is.

Claims (8)

In the asymmetric digital subscriber line (ADSL) subscriber multiplexing matching module of an asynchronous transmission mode (ATM) switching system, Subscriber matching module for connecting STM-1, DS3, DS1, DS1E, ADSL subscribers to subscriber switch network, Relay line matching module for connecting STM-1 and STM-4 relay lines to subscriber switch network, The subscriber matching module and relay line matching module And a subscriber switch network module that connects the subscriber control module to the switch network module, and a subscriber control module that collects alarms of each module in the local switching system and performs maintenance control and call connection control. and; And a central switching subsystem for interconnecting the local switching subsystems and performing overall control of the system. The system of claim 1, wherein the central exchange subsystem A network synchronizing module for generating the network synchronizing clock for the purpose of synchronizing the entire switching system network and supplying the internal module timing clock and the central timing clock of the same period to the subscriber switch network module, the connected switch network module, and the maintenance control module, respectively; A connection switch network module interconnecting the subscriber switch networks and having a connection with a maintenance control module; The asymmetric digital subscriber line multiplexing matching module of the ATM switching system, characterized in that consisting of a maintenance control module for performing the maintenance control function and the operation management function of the entire switching system. The method of claim 1, wherein the subscriber matching module It is connected to subscriber switch network module of local switching subsystem by internal connection module (IMI) for data connection and central timing clock (CTSI) for clock connection. An ATM cell multiplexer connected to a module timing signal interface (MTSI) for IMI and clock access to multiplex ATM cells and vice versa; Receive MTSI clock data transmission and reception through the ATM cell multiplexer and the IMI, and transmit and receive cell data through the ADSL subscriber processor and the transmit and receive cell bus, control message communication via a control bus, the ATM cell multiplexer An ATM layer processor for synthesizing and dividing the MTSI clocks received from the apparatus and supplying a main clock and a cell bus clock necessary for the ADSL subscriber multiplexing matching module; ADSL subscriber processing device connected to the ATM layer processing device through a transmission / reception cell bus and a control signal bus for data and message communication, and directly connected to an ADSL subscriber to process ADSL protocol function and ATM cell physical layer function of transmission / reception data. Asymmetric digital subscriber line multiplexing matching module of the AT switch system, characterized in that consisting of. 4. The apparatus of claim 3, wherein the ADSL subscriber processor is It is equipped with a certain bit processor to generate and buffer data, address and control signal lines and supply them to the local bus, and combine these signals to address the devices and registers belonging to each part in the subscriber matching device and to store the program. A central controller configured to control the entire ADSL subscriber processor by configuring a RAM for storing data and various data; After being connected to the local bus and receiving a predetermined bit transmission cell from the transmission / reception cell bus matching unit and converting the predetermined bit transmission cell into a predetermined bit, the point-to-point transmission cell is immediately transmitted to the transmission cell envelope for each subscriber, and in the case of point-to-multipoint transmission, the virtual to be converted A transmission cell processor for temporarily storing the PPI and the virtual channel identifier (VCI) table in the transmission cell envelope and outputting the result to the ATM physical layer processor; It consists of a plurality of subscribers, one for each subscriber, and converts the parallel transmission cells received from the transmission cell envelope to serial and ATM physical layer processing, and transmits them to the ADSL protocol processing unit, and converts the serial data cells received from the ADSL protocol processing unit into parallel and An ATM physical layer processing unit configured to output an ATM physical layer reception process to a receiving cell controller; Each of the subscribers has a predetermined number of serial data cells received from the ATM physical layer processing unit, and performs ADSL downlink processing by ADSL transmission line according to the modulation scheme, and outputs them to the ADSL subscriber line, and ADSL upstream input from the ADSL subscriber line. An ADSL protocol processor configured to output an ADSL reception process to the ATM physical layer processor; A receiving cell processing unit which is connected to the local bus and analyzes a receiving cell inputted by a predetermined bit from an ATM physical layer processing unit, converts the received cell into a predetermined bit, temporarily stores the received cell in a receiving cell packet, and outputs the received cell to a transmit / receive cellbus matching unit; Under the control of the receiving cell control unit, a loopback path is formed to send the test cell received from the receiving cell encapsulation unit to the transmitting cell control unit during its loopback test, and when not in the loopback test, the loopback path is transmitted from the ATM processing apparatus through the transmit / receive cell bus. Transceiving cell bus matching unit for receiving and buffering the cell and transmitting it to the transmitting cell control unit, receiving and buffering the receiving cell from the receiving cell encapsulation unit and delivering the buffer to the ATM layer processing apparatus; And Connected to the local bus and connected to a predetermined bit local address signal, various control signals, and predetermined bit data signal, and connected to an ATM layer processing apparatus via a control signal bus to receive a predetermined bit address signal and various control signals, An asymmetric digital subscriber line multiplexing matching module of an ATM switching system, comprising: a control signal bus matching unit configured to transmit and receive data signals of a predetermined bit and configure both ports to communicate with the ATM layer processing apparatus. The method of claim 4, wherein the central control unit It has a certain number of frequency clock generators and buffers and divides them and supplies them to the local bus and transmit / receive cell processing units.It generates and resets the manual reset reset signal to the local bus when the power is supplied and by the reset switch. Asymmetric digital subscriber line multiplexing matching module of the ATM switching system characterized in that it provides a terminal connection function for debugging through the RS-232C communication port. The method of claim 4, wherein the ATM physical layer processing unit An asymmetric digital subscriber line multiplexing matching module of an ATM switching system, which processes a function according to the ATM physical layer standard and automatically transmits and receives an idle cell when there is no user cell, thereby maintaining a connection with an ADSL subscriber. The method of claim 4, wherein the receiving cell processing unit An asymmetric digital subscriber line multiplexing matching module of an ATM switching system, comprising: a test cell transmitting packet and a test cell receiving packet; The method of claim 4, wherein the control signal bus matching unit Asymmetric digital subscriber line multiplexing matching module of an ATM switching system, characterized in that the main clock and the cell bus clock are supplied from the control signal bus, divided and controlled, and supplied to the transmitting cell processing unit and the receiving cell processing unit through a local bus.