KR100361374B1 - Method for retrying matching in sun bus and vme bus - Google Patents

Abstract

PURPOSE: A method for retrying a matching in a SUN bus and a VME bus is provided to increase a use rate of a SUN bus and a VME bus by evading a collision of data caused by a cycle duplication and reducing a retrial rate of a SUN bus master when masters of the SUN bus and the VME bus execute a read/write cycle of data for a data transmission. CONSTITUTION: A master on a VME bus supplies a bus use request signal to an arbiter through the VME bus and waits a bus use permission signal. If the bus use permission signal is generated from the arbiter and supplied to the master, the master generates an address strobe and a data transmission direction signal and supplies the signal to a retrial control unit through the VME bus for executing a reading or writing to a slave on a SUN bus. The retrial control unit checks whether a data transmission direction signal is for a read or a write, and judges whether an access to a SUN bus master is retried. While the VME bus master executes a writing operation(Sv_m_write), if the master of the SUN bus accesses for a reading or a writing, the retrial control unit generates a signal for a retrial, and permits the master of the SUN bus to operate a reading(Ss_m_read) or writing(Ss_m_write) in accordance with a data transmission direction(S_rd).

Description

How to retry registration on Sunbus and VMBus.

The present invention relates to the matching of a SUN bus and a VME bus, and more particularly, when the masters of both buses perform a cycle of writing and reading data for data transfer. The present invention relates to a matching retry method in sunbus and vembus to avoid collision of data.

FIG. 1 shows a retry operation state transition diagram in the conventional sun bus and V-embus matching. Data is transmitted using the state transition diagram.

That is, when both masters do not have any action on the Sbus and VMEbus, the master of the VMEbus (RQ) writes or reads data first. In order to transmit the data, that is, the MBM transmits a bus use request signal to the arbiter 105 through the VMEbus and waits for a permission signal therefrom.

When the permission signal is received from the arbiter, the master RQ of the MBM bus starts to write / read data by generating an address through the MBM bus.

The MB then begins reading data from the bus.

As such, the Sunbus master (s-r0) is in the middle of the bus master (RQ) performing write and read cycles for data transfer, or during the use of an interrupt or VMEbus. ), The retry control unit transmits a response signal (S-ack) for retry on the sunbus (Sbus), and processes all accesses of the sunbus master (S-RQ) to be retried. .

However, the retry control unit having such a retry operation state transition diagram in the conventional sunbus and VMS bus matching, as described above, reads or writes whether the operation of the master of the VME bus is performed. As a result of processing without distinguishing the recognition, there is a problem in that the usage of the sunbus is reduced by requiring too many retries from the masters of the sunbus, thereby causing a decrease in the input / output performance of the entire system.

Accordingly, an object of the present invention is to increase the cycle when both masters of Sbus and VMEbus perform cycles of writing and reading data for data transfer in view of such a conventional problem. It provides a matching retry method in Sunbus and Vbus that avoids data collisions and decreases the Sunbus master's retry rate, thereby increasing the bus utilization rate.

The matching retry method in the sunbus and VMBus of the present invention for achieving the above object is whether to retry the access of the Sunbus master by distinguishing whether the data transfer of the bus master is read or write. Determining; When the divided VMS master has access to read and write the Sunbus master in the write operation state, the VMS performs the write and read cycles to the slaves on the bus without retrying. Providing data; If the VMS master identified in the above step has read access status and there is access for writing to the Sunbus master, VM transfers data to the slave on the bus so that the Sunbus master performs the write cycle without retrying. Making a step; Retrying the operation when the divided V-Master master accesses the Sunbus master in a read operation state and reads; Retrying the operation if the sun bus master is approaching while the V bus master is receiving a bus license; Retrying the read operation of the master if there is an approach of the Sunbus master during the interrupt processing cycle on the V-Am.

Hereinafter, described in detail with reference to the accompanying drawings of the present invention.

FIG. 2 is a logic diagram showing a retry control device in a sunbus and VMS matching according to the present invention. As shown in FIG. A sunbus master 101 which provides the sunbus 102 with an access start signal S_sel and a data transmission direction signal S_rd to give or read data to 107 or 108; An address strobe V_as, a data transfer direction signal vwrite, a bus use request signal V_br, and an interrupt request signal for giving or reading data to a slave 107 present on the bus of the sun bus master 101 A V-bus master 103 for transmitting V_int) through the V-bus 104; The bus usage request signal V_br provided from the VMS master 103 is received and the bus usage permission signal V_bg is transmitted to the master 103 of the VMS 104 and the bus driving notification signal ( an arbiter 105 for transmitting vbgn); When the interrupt request signal V-int is input from the master 103 on the V bus 104, an interrupt recognition signal iack, which is a signal that an interrupt has been received, is transmitted to the master 103 on the V bus 104. An interrupt processor 106 for transmitting; The address strobe V_as input from the master 103 of the VMS 104, the data transmission direction signal vwrite, and the bus drive notification signal provided from the arbiter 105 and the interrupt processor 106. (vbgn) generates a retry signal S_ack according to the interrupt recognition signal iack, requests a master 101 on the sunbus 102 to retry, and transmits an access start signal S_sel and data input therefrom. The retry control unit 100 permits reading and writing according to the direction signal S_rd.

As described above, the operation and effect of the present invention constituted in detail will be described below with reference to FIG.

In the ready state in which no operation occurs on the VMS 104 and the Sunbus 102, the master 103 on the VMS 104 first sends a bus use request signal V_br. The bus 104 is provided to the arbiter 105 to wait for a bus permission signal V_bg therefrom.

Then, when the bus use permission signal V_bg is generated from the arbiter 105 and provided to the master 103 through the V bus 104, the master 103 is a slave 107 on the sun bus 102. In order to perform or write data for the data transmission to or to generate the address strobe (V_as) and the data transmission direction signal (vwrite) is provided to the retry control unit 100 through the V bus (104) .

The retry control unit 100 distinguishes whether the data transmission direction signal (vwrite) input through the VBus 104 is read or write to reestablish the access of the master 101 on the sun bus 102. The attempt signal S_ack is generated to determine whether to retry.

That is, the master 103 of the pair of V-bus 104 generates an address strobe V_as to perform a write operation, and the retry control unit 100 sets the data transfer direction signal vwrite to "0". If the retry control unit 100 determines that the master 103 on the VBus 104 is writing, it transitions to the Sv_m_write state.

In this manner, when the V-Master master 103 has an access for reading or writing the master 101 on the Sunbus 102 in the state of writing (Sv_m_write), that is, the master of the Sunbus 102. When the 101 provides the retry control unit 100 with the access signal S_sel and the data transmission direction signal S_rd through the sunbus 102 for reading or writing, the retry control unit 100 is configured to have the current V value. Since the M-Master master 103 is performing a write operation, a signal S_ack is generated for retry, and the master on the Sunbus 102 causes a data transmission direction signal (S_ack) without retrying. According to S_rd, the read (Ss_m_read) or write (Ss_m_write) operation is allowed.

That is, in FIG. 3, three states Sv_m_write, Ss_m_read, and Ss_m_write proceed simultaneously.

When the data transfer direction signal S_rd of the sun bus master 101 is "0", it is a write operation, and when it is "1", it is a read operation.

The retry signal S_ack generated by the retry controller 100 is a signal transmitted and received between the master 101 and the slave in data transmission on the sun bus 102 and has a value of "100" in the case of retry.

On the other hand, when the master 103 on the V bus 104 generates a data transfer direction signal vwrite to " 1 " to perform a read (Sv_m_read) operation, the master 101 on the sun bus 102 is operated. Generates a "0" of the access start signal S_sel and the data transmission direction signal S_rd for writing to the retry control unit 100, the retry control unit 100 retries in the same manner as described above. The master 101 on the sunbus 102 is allowed to write (Ss_m_write) according to the data transmission direction signal S_rd without generating the signal S_ack and retrying the sunbus master 101. .

In addition, when the operation of the master 103 on the V bus 104 is read (Sv_m_read) by the method described above, if the access of the master 101 on the sun bus 102 is also read (Ss_m_read). The retry control unit 100 generates a retry signal S_ack "100" to cause the master 101 on the sun bus 102 to retry (Ss_rerun).

In addition, the retry control unit 100 receives the bus driving notification signal vbgn from the arbiter 105 and transmits the bus license right even while transmitting the bus permission signal V_bg to the VMS master 103. Since the master 103 on the obtained V bus 104 does not know whether to perform a write operation or a read operation, the access of the sun bus master 101 also generates a retry signal S_ack "100" and tries again. (Ss_rerun).

In addition, there may be a read operation access from the Sunbus master 101 while receiving the interrupt recognition signal iack from the interrupt processing unit 106 that processes the interrupt request signal V_int on the VMS 104. Even in this case, the retry control unit 100 generates a retry signal S_ack "100" to retry the read operation of the sunbus master 101 (Ss_rerun).

That is, the operation of FIG. 3 will be described with reference to FIGS. 4 through 6, and the masters 101 and 103 on the sun bus 102 and the V bus 104 are present in the slave bus ( 107 and 108), if you don't do the proper mediation when trying to get or get data, the cycles of each other become entangled and dead-locked.

Accordingly, the present invention is implemented in the electrically programmable logic device (EPLD) through HDL (Hardware Description Language) as an algorithm that can improve the overall performance compared to the prior art while eliminating the deadlock state.

When the Sunbus 102 or VMS 104 master 101 or 103 performs a write operation, the data is stored in the first-in, first-out (FIFO) to terminate the operation of the Sunbus or VMS. After acquiring the license of VMB or Sunbus, the master (101 or 103) on both buses simultaneously transfers data from the first-in, first-out to the slave (107 or 108) of VMB or Sunbus. No need to use

When the masters 101 and 103 of the sun bus 102 or the V bus 104 perform the read operation, the V bus must obtain the right to use the V bus 104 or the sun bus 102, and then V The bus cycle can be normally terminated only after obtaining data from the slaves 107 or 108 on the bus 104 or the sun bus 102 and storing the data in the first-in, first-out manner, and then simultaneously using the two buses.

In the prior art, when a bus cycle occurs on a V bus, all accesses to the sun bus master are to be retried, but in the present invention, the sun bus 102 may be distinguished by retrying according to the characteristics of each bus cycle. Minimize the retry rate of the master (101).

That is, the bus cycle may be classified into cases such as FIGS. 4 to 6.

That is, first, as shown in FIG. 4, when the read operation of the master 103 on the V bus 104 and the write operation of the master 101 on the sun bus 102 occur at the same time, the V When the bus master 103 is overlapped with the write operation (Ss_m_write) of the sun bus master 101 during the read (V_as, vwrite) operation (Sv_m_read), the sun bus master 101 is the sun bus 102 Since the user has the right to write, the write operation is performed first, and then the V-Master master 103 obtains the sunbus right to perform a read operation on the slave 107.

This does not cause retry of the sunbus master 101.

Second, as shown in FIG. 5, when the writing of the master 103 on the V bus 104 and the writing of the master 101 on the sun bus 102 simultaneously occur, the sun bus master 101 The write operation Ss_m_write and the write operation Sv_m_write of the VMS master 103 are bus cycles when the buses do not need to be used at the same time.

The Sunbus master 101 needs to recover the Sunbus license after obtaining data from the first-in, first-out, and obtain the license of the VBus 104, but since it is being used by the VBMaster 103, After the bus master 103 stores the data in the first-in, first-out, it waits to recover the bus and transmits the data.

Similarly, the data stored by the V-Master master 103 obtains the Sunbus license and transfers it to the slave.

This does not cause retry of the sunbus master 101.

Thirdly, when the read operation of the sun bus master 101 and the write operation of the V bus master 103 occur at the same time, the operation is performed in the same manner as the first one.

Finally, the read operation of the sun bus master 101 and the read operation of the V bus master 103 occur simultaneously.

In this case, when the masters 101 and 103 of two buses simultaneously perform a read operation (Ss_m_read) (Sv_m_read), deadlocks occur while waiting for each other because two buses must be used at the same time in order to end the cycle. do.

Lee Sun-woo Sunbus master 101 is in a retry state (Ss_rerun).

That is, the retry control unit 100 generates a retry signal S_ack "100" to retry.

Iack and vbgn of FIG. 3 show the progress of the interrupt cycle on the VMB 104 and the permission to use the bus.

That is, even in this case, the sunbus master 101 is retried.

As described in detail above, according to the present invention, when both masters of Sunbus and VMEbus perform cycles of writing and reading data for data transfer, data of duplicated cycles are generated. By avoiding collisions and reducing the retry rate of the sunbus master, the sunbus utilization is increased and the use of the V-bus is also increased.

1 is a state transition diagram showing a retry operation state in the conventional sun bus and V-embus registration.

2 is a logic diagram showing a retry control device in matching sun buses and V buses of the present invention.

3 is a transition state diagram of an operation of a retry controller in matching sunbus and v-ambus according to FIG. 2;

4 is a signal flow diagram when the read operation of the V-Master bus and the write operation of the Sunbus master according to FIG. 2 overlap.

FIG. 5 is a signal flow diagram in the case where the write operation of the V-Master bus and the write operation of the Sunbus master according to FIG. 2 overlap.

6 is a signal flow diagram in the case where the read operation of the V-bus master and the read operation of the sun bus master according to FIG. 2 overlap.

***** Explanation of symbols for main parts of drawing *****

100: retry control unit 101: Sunbus master

102: Sunbus 103: VM Master

104: VMB 105: Arbitrator

106: interrupt processing unit 107: Sunbus slave

108: vmbus slave

Claims (2)

Determining whether to retry access of the Sunbus master by distinguishing whether the data transfer direction of the VMS master or the Sunbus master is read or write; Retrying the operation if the sun bus master is approaching while the V bus master is receiving a bus license; And retrying the read operation of the master when the sunbus master approaches the interrupt processing cycle on the VMB. The Sunbus master of claim 1, wherein the sunbus master performs a write and read cycle without retrying when there is an access for reading and writing the sunbus master in a write operation state. Providing the data to the slave on the bus so that the MB is configured; Sending data to a slave on a bus such that the bus bus performs a write cycle without retrying when the bus master has an access for writing the sun bus master in a read operation state; And retrying the operation when the access of the sun bus master is read in the read operation state of the divided V bus masters.