KR100355455B1 - ATM Switching Apparatus having Dynamic QoS control - Google Patents

Abstract

The present invention relates to an ATM switch device having a dynamic quality of service control, which extracts an AMT cell from a transmitted physical medium, classifies the cell using an identifier of the connection information, and provides an interface for switching in the switch fabric. Provides a line interface card (LIC), a switch fabric (SF) providing a switching service by providing a physical delivery path to the output LIC to transfer between them, call control and connection management for the channel connected to the LIC It consists of call processing unit (CP), operation maintenance and system operation processor processing unit that manages maintenance and switching system maintenance of ATM network, and provides various quality of service (QoS) while providing differentiated exchange service according to service priority. Priority is given to each input cell flow in the front end to provide a providing switch structure. And a routing processor for switching the cells of the rear end of the input cell to a desired output port by classifying them according to the classification and managing the buffers for the exchange service. There is an effect that can facilitate the operation management of.

Description

ATM Switching Apparatus having Dynamic QoS control

The present invention relates to an ATM switch device with dynamic quality of service control.

The present invention provides an ATM-LAN switching system in a private network, an ATM local exchange in an public network, an ATM access node, an ATM cross connector, and the like. In addition to the system configuration of the system can be applied to all the systems that require switching ATM.

First of all, services in the Broadband Integrated Service Digital Network (hereinafter referred to as B-ISDN) communication network environment are referred to as Constant Bit Rate (hereinafter referred to as CBR) according to the traffic management standard of ATM Forum. Real Time-Variable Bit Rate (hereinafter referred to as RT-VBR), Non Real Time-Variable Bit Rate (hereinafter referred to as NRT-VBR), Available Bit Rate (hereinafter referred to as RT-VBR) ABR) and Unspecified Bit Rate (hereinafter referred to as UBR) are classified into service attributes.

These features are distinguished between real-time processing services that allow some loss of data but are sensitive to propagation delay, and very sensitive to cell loss, which allows propagation delay.

Therefore, the service method of a queue must respond dynamically according to such a difference of traffic attributes, and an effective switch which performs a differential exchange between services having different priorities even for services of the same attribute is needed.

In the case of a common shared memory switch, the QoS function can be provided by controlling the order of reading / writing all input / output ports to one shared memory.

However, this architecture is suitable to provide this functionality, but must have a separate function or identifier for the ability to replicate the multicasting service cell, and to avoid congestion occurring in any switching path that occurs when implementing a symmetric switch. Difficult to control

In addition, there is a problem in that m timeslots have to be wasted in order to duplicate m cells at the input or duplicate the cells at the output for any m cell duplication.

FIG. 1 is a schematic diagram of a switch structure. A line interface card extracts an ATM cell from a transferred physical medium, classifies the cell using an identifier of the connection information, and provides an interface for exchange in a switch fabric. Card (hereinafter referred to as LIC) 10 and a switch fabric (Switch Fabric, hereinafter referred to as SF) 20 providing physical exchange paths to the output LICs desired to be transmitted between them and the LICs 20, and to the LICs. Call Processor (CP) 30 for call control and connection management for connected channels, Operation and Administration for managing ATM network maintenance and switching system maintenance ( 40) and a system management processor (hereinafter referred to as SMP) processor 50.

Typically, the LIC 10 converts a signal transmitted from an optical medium into an electrical signal, identifies a cell boundary from the signal, and restores a cell flow from the restored cell flow to a desired output according to the connection information of the corresponding connection table of each cell. A routing tag is added to the switch fabric 20 to be switched.

Conversely, the cells switched from the switch fabric 20 are transmitted in the transmission frame again in the LIC 10.

The use of such a general line interface block has a problem that it has priority and is out of control over many connections established on one input link.

The speed of the link to be accommodated according to the BISDN implementation is very diverse, and particularly has the characteristics of high speed.

Initial speeds of B-ISDN deployment were STM-1 grades of 155Mbps and 622Mbps, but channel speeds of 2.5Gbps, 10Gbps and even 100Gbps are required according to the needs of Gigabit Transport Network.

Due to the characteristics of such high speed and the construction of a more economical service network, a lower speed link such as 2.5Mbps and 51Mbps is being accommodated in an ATM system.

Therefore, the ATM switching system is required a switching method that can effectively accommodate the above various channel rates.

However, most of the existing switching schemes are single channel switching schemes in which the input / output ports of the switch network have a one-to-one relationship.

In this method, the output port has one link physically and logically, and bandwidth allocation and routing path determination in the switch network are handled independently for each port.

However, multi-channel switching method is required to provide switching service for input / output link with n × V speed by using switch network with basic speed V. Distribution of cells by each virtual connection There is an additional need for multiplexing and demultiplexing devices to use the same physical link.

For this reason, the configuration of the system is complicated and the cost of implementation is high.

In this structure, the incoming cell can be provided with a routing path through any port in the same logical group. Therefore, the cell has more opportunities in the path cell configuration, and the maximum bandwidth of the links belonging to one logical port can be used. This makes it possible to effectively use the available band of the system.

Therefore, the multicasting switching feature is used for routing.

Recently, a switching scheme providing several multichannel switching functions has been proposed, but the order preservation scheme of cells, which is one of important operating characteristics in providing multichannel switching, is not clear and inefficient.

In order to solve the above problems, an object of the present invention is to provide a switch structure capable of performing a differential exchange to a service having a different priority even in a service having an attribute such as a traffic attribute.

In order to achieve the above object, the present invention provides a line interface card that extracts an AMT cell from the transferred physical medium, classifies the cell using an identifier of the connection information, and provides an interface to be exchanged in a switch fabric. LIC), a switch fabric (SF) providing a switching service by providing a physical delivery path to the output LICs to be transferred between them, and a call processing unit (CP) for call control and connection management for a channel connected to the LIC. It is composed of operation maintenance and system operation processor processing unit that manages maintenance of ATM network and switching system maintenance, and provides various service quality (QoS), and provides switch service that provides differentiated exchange service according to service priority. For this purpose, each input cell flow in the front-end is sorted according to priority and the exchange service is Priority classification processor 300 that manages the buffer, characterized in that it comprises a route processor 400 that is responsible for the switching of the rear end of the cells of said input cell to a corresponding output port desired.

The present invention has a structure of classifying cells according to priority and performing cell exchange according to the priority, and the size of a buffer corresponding to each priority level in call admission control (CAC). It can be controlled by using and its storage level information. On the contrary, it is easy to manage I / O link in terms of resource management because the distribution of currently available resources can be known at a time.

In addition, a function of generating a backpressure request signal to the input traffic transmitting device according to the load state of the input / output port and temporarily sending traffic to the corresponding output port according to the flow control request signal from the output traffic receiving device. It provides a backpressure buffering function which is stored in the memory device, and it is intended to double the performance of the switching device and to make the operation of the device easier.

Therefore, the present invention has the characteristic that the cell order is maintained without any special mechanism, and if the order of cells is not preserved in the switch network itself, a complicated additional function for preserving the cell order at the system level is required, and even the service endpoint ) Additionally requires the ability to reorder the cells.

However, the present invention has the property that the cell order is maintained without any special mechanism.

1 is a general switch structure diagram,

2 is a buffering structure diagram of an interface card according to the present invention;

3 is a QoS buffering structure diagram of an ATM switch fabric to which the present invention is applied;

4 is an ATM switch fabric structure diagram with dynamic quality of service control according to the present invention;

5 is a detailed structural diagram of a priority classification processing unit according to the present invention;

6 is a detailed structural diagram of a routing processing unit according to the present invention;

* Explanation of symbols for main parts of the drawings

10: line interface card 11: user parameter control unit

12: constant bit rate real-time variable bit rate unit

13 non-real-time variable bit rate unit 14: non-specific bit rate unit

15, 200: scheduler 20: switch fabric

30: call processing unit 40: maintenance operation management unit

50: system operation processor 100: QoS class

300: priority classification processing unit 310: S / P conversion function unit

320: access control unit 330: QoS buffer

331: boundary pointer 332: loss sensitivity data queue

340: priority scheduler 350: buffer control unit

360: record pointer 370: read pointer

400: routing processing unit 411: output aggregation control unit

412 routing and aggregation crosspoint network

413 backplane control unit 421 synchronous circuit

422: routing crosspoint subnet

423: address control flag generator 424: aggregation crosspoint subnet

425: OPIU 426: BPFCU

427: ILCC 428: CIU

429: output group broadcasting device

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a buffering structure diagram of an interface card according to the present invention, and services in a BISDN environment are classified into CBR, RT-VBR, RT-VBR 12, NRT-VBR, ABR 13, UBR 14, and the like. Similar attributes are collected and divided into three types of attributes, which are then stored in three separate buffers. Prior to this, a user parameter controller is provided to monitor whether the user parameter set is maintained, and through this, the normal cell is stored in a buffer corresponding to the property to which the self belongs.

They are distinguished by real-time processing services that allow some loss of data but are sensitive to propagation delay, and very sensitive to cell loss.

Therefore, if the connection setting is already made and the traffic parameter of the corresponding connection is determined, the UPC 11 function module monitors and controls the compliance of the incoming traffic.

The traffic passed in compliance with this is divided into CBR, RT-VBR (12) buffer for real time processing, and NRT-VBR and ABR (13) for non-real time processing. UBR traffic 14 that does not require is stored separately.

Therefore, delay sensitive traffic must be handled in real time, in which case the buffer size can be relatively small.

However, traffic that is non-real time but sensitive to cell loss requires a large buffer size because it must be stored according to the link state.

For complete QoS processing, each buffer must be maintained for each VCC / VPC connection, but this becomes too complicated for connection management and service, and the buffer structure becomes complex.

Although it is not more perfect than this, it is possible to satisfy service priority because it is classified simply by the relative attributes of connections that are already connected and serviced.

In the scheduler of FIG. 2, the buffer is read according to the storage degree of each of the three group buffers and the state information from the switch fabric.

The serviced cell flow is sent to the switch fabric, which receives cells from the N LICs 10 and is classified and stored in the QoS buffer of FIG.

As shown in FIG. 3, the cells sent to each LIC are classified and stored in N QoS classes according to service priority information at the switching system level added in front of each corresponding cell.

The QoS class 100 is divided into three groups for each LIC 10, and each group is divided into (N-1) / 2 priorities except for the UBR 14.

In the case of UBR 14, the priority is the lowest, but the priority is also divided among them.

The cells stored in the buffers that are physically separated according to the priorities are exchanged and serviced by a specific scheduling policy according to the state information of each QoS buffer 330.

As shown in FIG. 3, the buffer of each class may vary in size when a large number of connections for a specific service are required during call control and connection admission control at the exchange apparatus. The information is provided when determining how much available resources are available above the service characteristics and priorities of calls that require connection establishment.

With such a simple configuration that QoS can be dynamically controlled during such service operation, FIG. 4 shows an embodiment of a 16 × 16 switch.

The number of I / O ports is limited to 16, which can be further expanded in terms of the implementation function.

As shown in the embodiment of FIG. 4, the switch structure mainly classifies each input cell flow of the front end according to the priority, and priority classifying block (Priority Sorting) managing the buffer for the exchange service according to the priority. Block 300 is divided into a routing block 400 which is responsible for switching the cell of the rear end to the desired output port.

In an embodiment, IP0 may be input as serial data having a sync frame in dedicated signals IP15 input from 16 LICs, and may be input in parallel data format of a specific byte for ease of implementation.

In this case, a separate control signal for distinguishing cell synchronization is always required.

The inputted cell flow is converted into parallel data so that the cells inputted from all 16 input ports through the S / P conversion function unit 310 can be classified into 16 priority classes.

Then, the access controller 320 analyzes the corresponding cell and waits in the buffer (Q0 to Q15) 330 of the corresponding class by using the QoS information added before it.

Since Q0 has the highest priority, Q0 has the opportunity to transmit with the highest priority without delay, and its size is also the smallest.

However, Q15's buffer has the lowest priority, making it harder to transmit than other classes.

And they must be very large because they receive transmission opportunities when other buffers are not available for servicing.

The size of each buffer depends on the priority and the number of channels currently connected to each class, and varies with traffic distribution.

However, the size of the entire buffer is physically fixed in size, and is divided into classes within the size.

The cells classified in this way are read according to the priority by the priority scheduler 300.

The cell read from the priority classification processing unit 300 is routed to a desired output port according to the routing tag information added before the cell in the routing block.

As shown in FIG. 5, the priority classification processor converts the serial data stream into parallel data first, multiplexes it, and sends the same to the access controller 320 as QoS information.

The access control unit 320 controls to view information on the QoS level of the cell and to store the information in the priority buffer.

In this case, each buffer is composed of one shared memory, a write pointer 360 indicating a write address of each buffer, a read pointer 370 indicating a read address, and a buffer of each buffer. There is a boundary pointer 331 for separating the boundaries.

The access control unit 320 determines which buffer the currently input cell is stored in and enables the write point of the buffer.

The cell data is then stored in the memory at the address indicated by that point.

In addition, the boundary pointer 331 maintains information on boundaries divided according to the size of the corresponding buffer at an initial stage. If a buffer of a certain priority needs to be further increased, the boundary pointer 331 may be changed by moving the boundary of an adjacent buffer. It is possible.

Also, when determining whether to accept a connection of a channel during operation, it is determined whether to accept a report on the storage level of the priority buffer for the connection.

The priority scheduler reads cells from each buffer and sends them to the routing processor for switching services.

Since Q0 is the highest priority here, even one cell is read first.

However, Q15 is the lowest priority because it is the same as UBR, which provides the lowest priority and services when no other traffic exists.

The priority scheduler can also be controlled by external processes and can be modified by applying specific service algorithms.

6 shows a detailed structure and an embodiment of a routing processor.

Port0 in Port15 of Input Data represents IN15-IN0 of FIG. 5, and Output Data represents OP15-Op0.

In order to ensure high performance while simultaneously providing multi-channel and multi-casting functions, the switching device 400 provides a multi-channel switching and multicasting switching function by configuring a plurality of cross-point switch elements and a checker board. Routing Crosspoint Subnet (RCSU) 422, which performs a function that performs a function of only a limited number of feedback paths of cells Address Control Flag Generator (ACFG) 423 which provides a screening function, and Concentration Crosspoint Subnet (hereinafter referred to as CCSU) that aggregates cells by receiving flag information from the ACFG. Feedback output ring for returning selected cells back to the switch input via CCSU (Recirculation Path) A recirculation path interface unit (hereinafter referred to as RPIU) 421 for providing time synchronization between cells fed back through a feedback output link and cells inputted through a switch, and address information of grouped output ports. An output group address broadcasting unit (hereinafter referred to as OGABU) 429 is provided.

Approximate operating characteristics of the apparatus composed of the above functional blocks are as follows.

The OGABU 429 inputs the output port grouping address information received from the system controller at the time of system initialization or service to the RCSU 422.

The input address information is used to compare the destination address of the input cell to determine the routing path of cells input in the RCSU 422 to the destination output port.

Cells inputted through input link IN15-IN0 and cells inputted through recirculation path rule are outputted by comparing their destination address with output port grouping address from OGABU 429 in RCSU. The path to the output port on the link or the path to the CCSU 424 on the bypass link is assigned.

The cells assigned the path to the output port are output through the output link directly through the OPIU 425, but the cells assigned the path to the bypass link are inputted to the CCSU 424 so that only R cells having a limited link number The selector is input to the synchronizing circuit (RPIU) 421 through the feedback output link, and the synchronizing circuit provides a function of adjusting a time difference so as to be synchronized with cells newly input through the input links IN15-IN0.

The feedback cells whose time difference is adjusted are inputted together with the cells newly input to the switching device via the feedback input link again in the RCSU to repeat the above operation process.

In other words, the apparatus of the present invention is configured as a switch having an externally N input port or a switch having a characteristic of a shared memory corresponding to R cells internally. Becomes N + R = M.

Up to N cells of these M cells are provided with a switching path to the output port for output, and the unallocated cells are input to the input of the CCSU 424 via the feedback path link to select only dual R cells. After the synchronization process, it is input to the RCSU 422 again to have a path assignment competition with newly input cells and output ports.

As described above, the present invention is a service switch of the queue dynamically corresponding to the difference of the various service traffic attributes in the switching network, and even if the service of the same attribute is an effective switch that performs the differential exchange of services with different priorities. ATM switch can be more suitable for the multimedia age to provide a variety of traffic in the future.

That is, the present invention is divided into a priority class classification block (Priority Sorting Block) for classifying each service priority at the front end of the switch and a routing block for controlling the switching service according to each priority classified therein and connected in the system. Processed according to each set service priority.

Therefore, since various priorities can be handled, even the same service can give different classes to each other, so that various services can be provided from a network operator.

In addition, the relationship between the input and output ports of the switch to have a multi-channel function to dynamically configure the number of the receiving link in the group unit of the input and output link of the switch to allow links having different speeds through one switch network.

In addition, by accommodating the copy function of the cell to provide the multicasting function and simultaneously processing the copy function and the routing function of the cell in one network, it reduces the type of network required to configure the switching device and at the same time the existing switching Like the device, the control required between the copy network and the routing network has the effect of excluding the configuration of a complicated and large table.

Claims (5)

A line interface card (LIC) that extracts ATM cells from the transferred physical media and identifies them using the identifier for the connection information and provides an interface for exchange in the switch fabric. Switch fabric (SF) to provide exchange service by providing physical forwarding path, call processing unit (CP) to manage call control and connection for channel connected to LIC, maintenance of ATM network and maintenance of switching system In order to provide a switch structure that provides a variety of quality of service (QoS) while providing different services according to the service priority, which consists of an operation maintenance and system operation processor processing unit that manages A priority classification processor for classifying each input cell flow of the SF front end according to priority and managing a buffer for an exchange service; And a routing processing unit which is responsible for switching a cell of a rear end of the input cell input according to priority to a desired output port. The method of claim 1, wherein the priority classification processing unit, An S / P conversion function for converting into parallel data so as to process cells inputted from all ports and classify them into classes of priority; An access control unit which receives the converted data, analyzes the corresponding cell, classifies and waits in the corresponding class buffer using the quality of service information added in front of it; And a priority scheduler which reads the classified cells according to the priority and routes the classified cells to a desired output port according to routing tag information added to the front of the cell in the routing block. The method of claim 2, wherein the class buffer of the access control unit, A write pointer pointing to the write address of each buffer; A read pointer pointing to a read address; ATM switch device having a dynamic quality of service control, characterized in that consisting of a boundary pointer for distinguishing the size of each buffer. The method of claim 2, wherein the priority scheduler, ATM switch device having a dynamic quality of service control, which can be controlled by an external process, can be changed by applying a specific service algorithm. The method of claim 1, wherein the routing processing unit, A routing crosspoint subnet (RCSU), which comprises a plurality of crosspoint switch elements and a checkerboard shape to provide multichannel switching and multicast switching functions; An address control flag generator (ACFG) that performs a function of selecting only cells of a limited number of feedback paths among the cells that are connected to the RCSU and are eliminated from the competition for the same output port; An aggregation crosspoint subnet (CCSU) that receives flag information from the address control flag generator and aggregates cells; A feedback output link for returning selected cells back through the crosspoint subnet to a switch input; A synchronization circuit (RPIU) for providing temporal synchronization between the cells fed back through the feedback output link and the cells newly input to the switch; And an output group address broadcasting synchronization circuit for providing address information of grouped output ports.