KR100343940B1 - Cache anti-aliasing during a write operation using translation lookahead buffer prediction bit - Google Patents

Abstract

In a data processor with a set associative cache, the virtual address is generated at the central processing unit. The virtual address has a virtual page number and a virtual offset. The virtual page number is converted to a physical page number. At least one of the converted bits contains information about the cache set to be written. The virtual page number is modified by the translated cache set bits. The cache is then accessed using the modified virtual page number. In this way, cache performance is improved and accurate segment prediction is maintained, while eliminating the possibility of aliasing during cache write operations.

Description

Cache anti-aliasing during a write operation using translation lookahead buffer prediction bit}

The present invention relates to a data processor, and more particularly, to a method and system for determining a set value of a word to be written to a cache in a data processor having a set associative cache.

In typical data processors, a central processing unit (CPU) relies on memory to store and extract information. System memory is organized according to memory hierarchy. The memory layer includes registers, caches, physical memory, and virtual memory. In general, registers formed near the CPU within the processor allow for quick access and are most commonly active while the CPU is running. Caches located on both on-chip and off-chip provide an intermediate interface between registers and off-chip physical and virtual memory that are slower than registers. The cache temporarily stores data written to and read from the memory, which enables efficient CPU access.

In operation, the CPU accesses data written to off-chip memory or writes data to off-chip memory by referencing the fast on-chip cache. If the requested data is immediately available in the cache, a cache hit occurs. Otherwise, cache misses occur and data extraction from time-consuming off-chip memory is required. A common goal of modern CPU architectures is to optimize cache hit rates.

In modern systems, the size of off-chip memory is much larger than the size of on-chip cache. For this reason, a mapping technique is used that maps cache and memory. Mapping techniques can generally be divided into direct cache mapping and virtual cache mapping. Each is published on page 7 of pages 454-527 of the book "Computer Organization Design" published by Morgan Kaufmann in 1994 and written by Patterson and Hennessy.

The simplest cache structure allocates each memory location to its cache location or cache block. This cache structure is called a cache mapped directly in the art. Each memory address has a cache index associated with a cache tag. The cache index identifies the cache block with which the memory is associated. Cache tags uniquely identify each memory location that has access to a cache block.

When a virtual address is used to access the cache, the cache at that time is called a virtual cache. When a physical address is used to access the cache, the cache at that time is called a physical cache. When using a virtual address, translation to a physical address is required. Modern CPU architectures often use virtual address technology.

Virtual memory is arranged into a number of pages each referenced by a page index. An offset is used with the page index to refer to the virtual memory location. When the size of one virtual memory page is smaller than the size of the cache and different virtual addresses are mapped to the same physical address, two or more identical physical address entries may exist simultaneously in a given cache. This phenomenon is known as cache aliasing in this technical field. Modern systems must address the issue of cache aliasing.

Conventional methods for eliminating cache aliasing include techniques for predicting physical addresses for virtual addresses using pseudo-set associative caches, and reading the same index tag and updating the cache. Invalidating the same tag when identical, and allocating the same cache when the virtual address and the physical address are composed of lower overlapping bits. Each of the above techniques has many problems in cache allocation techniques such as high cache loss and poor performance when invalidating the contents stored in the cache.

The technical problem to be solved by the present invention is to provide a technique for solving the cache aliasing problem in the cache write operation as a method of overcoming the problems of the prior art.

1 is a block diagram illustrating a preferred cache structure in accordance with the present invention.

2 is a block diagram of a translation lookahead buffer (TLB) including a cache set prediction bit generator in accordance with the present invention.

3 is a timing diagram illustrating timing at the generation of cache write and set prediction bits in accordance with the present invention.

One aspect of the present invention for achieving the above technical problem relates to a method for determining a set value of a word to be written to the cache in a data processor having a set associative cache. The virtual address is generated at the central processing unit. The virtual address has a virtual page number and a virtual offset. The virtual page number is converted to a physical page number. At least one bit of the converted bits contains information about the cache set to be written. The virtual page number is modified using the translated cache set bits. The cache is then accessed using the modified virtual page number.

In a preferred embodiment, after accessing the cache using the modified virtual page number, the translated physical page number is compared with the modified virtual page number to determine if a cache hit has occurred. Upon conversion, a set prediction bit is generated that is an indication of the cache set to be written. The set prediction bit may be one bit or may be a plurality of bits.

By the present invention, cache performance is improved without expanding the cache size. And, by using the set prediction bits during the write operation of the cache, accurate segment prediction can be maintained.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present specification, for the convenience of description, signals performing the same role through the drawings are denoted by the same reference numerals.

1 is a block diagram of a cache structure representing a preferred embodiment of the present invention. The CPU 20 executes instructions and processes data in accordance with the implemented technology. In general, the most efficient means of exchanging data and instructions between the CPU 20 and the memory 54 is through the on-chip cache 24. When the CPU 20 wants to read a word from the first cache 24A, the CPU 20 generates a virtual address VA, for example, VA <41: 0>. The virtual address VA includes a page index, eg VA <41:14> and an offset, eg VA <13: 0>. Here, <x: y> is a nomenclature commonly used in the art to indicate bit positions x and y in a data word or address word. The page index contains information about the physical address of the data to be accessed. The offset represents the block 25A of the first cache 24A to be accessed. During a cache read, the cache tag 25A is compared with the page index in the comparator 30 to access the cache block 25A according to the offset and to determine whether it is a cache hit or a cache miss. When a cache hit occurs, the CPU 20 may use the corresponding data 32 from the first cache 24A. If a cache miss occurs, the data is retrieved from the memory 54. In FIG. 1, the translation from virtual memory address VA <41:14> to physical memory address PA <31:14> is done in a translation lookahead buffer (TLB) 22. This conversion process is described in more detail below.

In modern CPU architectures it is often desirable to use a cache larger in size than the width of the virtual page offset. Increasing the size of the cache helps improve overall system performance, but can also cause problems. For example, in the set associative cache structure shown in FIG. 1, the cache 24 includes 8K cache blocks 25A and 25B, respectively, so that two cache sets 24A and 24A become total 16K cache blocks. 24B). On the other hand, the offset portion of the address word may consist of only 8K positions, VA <13: 0>. When performing a cache read, valid data can be stored in either cache set 24A, 24B. Each set is accessed by cache offsets VA <13: 0> and the corresponding tags 26A, 26B are compared with the page indexes of the virtual memory. The data in the tag that matches the page index is correct. Therefore, in this example, the cache read operation is not a problem.

However, abnormalities such as cache aliasing may occur during the cache write operation. When the CPU 20 wants to write a word to a particular cache block 25A, the CPU 20 generates a virtual address VA containing the cache offset positions VA <13: 0>. However, cache 24 includes two cache sets 24A, 24B, each indexed according to cache index <13: 0>, twice as many as the virtual address offset position. For this reason, it is unknown whether the CPU wants to write to the first cache set 24A or to the second cache set 24B.

The present invention solves the cache aliasing problem in such a way that the proper cache set is always predicted during cache write operations without degrading system performance.

In particular, a TLB 22 is used that includes a set prediction bit generator 28. TLB is commonly used in CPU architecture to perform efficient address translation between virtual address (VA) and physical address (PA). As described in Patterson's book page 491, cited earlier, the TLB acts as a cache to keep track of recently used translation entries between virtual and physical memory. Each time a TLB is referenced, the TLB hit or TLB miss is determined in the same manner as in the data cache described above. If a miss occurs, the translation entry is taken from the page table (previously stored in memory) into the TLB, which can then be referenced. When the TLB reference becomes a hit, the virtual address VA is mapped to the physical address PA. The resulting physical address PA is compared with cache tags 26A and 26B at comparator 30. If a cache hit occurs, the CPU may use the associated data 32.

2 is a detailed block diagram of the translation lookahead buffer (TLB) 22 of the present invention. In a preferred embodiment, the TLB 22 has a content addressable memory (CAM) 52 and a random access memory (RAM) 52. The virtual address VA is input to the CAM 50 and the output 51 of the CAM is used to reference the corresponding RAM 52 address. The output of the RAM 52 indicates the physical address PA corresponding to the virtual address VA.

The TLB of the present invention further includes a set prediction bit register 28 that includes a large number of addressable locations corresponding to the locations of the various CAMs 50. When the cache is filled during the cache read, the set bits of the physical address PA, for example bit 14, are stored in the TLB 22 and the set prediction bit register 28 and written. For example, if data is stored in the first cache set 24A, the set prediction bit ABP is set to '0'. On the other hand, if data is stored in the second cache set 24B, the set prediction bit ABP is set to '1'.

Referring again to FIG. 1, during a cache write, the CPU generates a virtual address VA that includes page indexes VA <41:14> and offsets VA <13: 0>. The virtual address VA is immediately input into the TLB 22, and the corresponding set prediction bit APB is output from the set prediction bit register 28. The set prediction bit (APB) is associated with the virtual address VA and overwrites bit 14 before the virtual address VA is used to access the cache 24. This process occurs during the translation of the virtual address (VA) into a physical address (PA). For example, during cache write, if two cache blocks have the same tag tag0, tag1, the set prediction bit ABP is used to select the correct block, and only the correct block is updated.

3 is a timing diagram illustrating timing at the time of cache write and set prediction bit (APB) generation in accordance with the present invention. The clock signal CLK represents a standard system clock. At time t ₀ , the virtual address VA becomes available as an input to the TLB 22. The virtual address VA is input to the CAM 50 at the rising edge of the clock signal CLK at time t ₀ . After one clock cycle, the corresponding physical address PA becomes available as an output of the TLB 22. The prior art relies on the physical address PA in solving the aliasing problem of cache writes. However, the present invention uses the set prediction bit register 28 which immediately generates the set prediction bit (APB) available at time t ₁ . The tags 26A and 26B are modified immediately, and the appropriate cache set 24A and 24B is accessed with the modified page number. In contrast to the prior art, this modification is made within the same clock cycle as when the virtual address VA becomes available for caching. In the prior art, it depends on the physical address available during the next clock cycle. In this way, the appropriate cache set is always accessed, thus cache aliasing is eliminated.

Although the present invention has been shown and described with reference to preferred embodiments, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

For example, a sophisticated architecture may have multiple cache configurations, such as separate caches for the data bus and instruction bus. The present invention equally well applies to such systems.

In another embodiment, when two or more cache sets are used, the set prediction bit (APB) may consist of a plurality of bits.

By the present invention, the possibility of aliasing during a cache write operation is eliminated, while cache performance is improved and accurate segment prediction is maintained.

Claims (10)

In a data processor having a set associative cache, A) generating, at the central processing unit, a virtual address comprising a virtual page number and a virtual offset and which will be written to the cache; B) converting the virtual page number into a physical page number, wherein at least one of the converted bits includes information regarding a cache set to be written; C) modifying the virtual page number using the converted cache set bits before cache access; And And d) accessing said cache using said modified virtual page number. The method of claim 1 wherein the method is And after step D), comparing the physical page number with the modified virtual page number to determine if a cache hit has occurred. The method of claim 1, wherein the step B) Generating a set prediction bit that is an indication of the cache set. The method of claim 3, wherein the set prediction bits 10. A method of determining a set value of a word to be written to a cache, characterized by comprising a plurality of bits. The method of claim 1, wherein the step D) And a method for determining a set value of a word to be written to the cache, wherein the converted physical page number is earlier than an available time point. In a data processor having a set associative cache, A cache comprising a plurality of assignable blocks grouped into a plurality of sets; A central processing unit including a virtual page number and a virtual offset and generating a virtual address to be written to the cache; A converter for converting the virtual page number into a physical page number wherein at least one bit of the bits to be converted includes information about a cache set to be written; And And circuitry for modifying the virtual page number using the converted cache set bits prior to cache access. The system of claim 6 wherein the system is And a comparator for comparing the physical page number with the modified virtual page number to determine if a cache hit has occurred. The method of claim 6, wherein the transducer And means for generating a set prediction bit that is an indication of the cache set. The method of claim 8, wherein the set prediction bits A set value determination system of a word to be written to a cache, characterized by comprising a plurality of bits. The method of claim 6, And the modification of the virtual page number precedes the available time of the converted physical page number.