KR100338816B1 - Method for forming SRAM MOS transistor and Thin Film Transistor gate - Google Patents
Method for forming SRAM MOS transistor and Thin Film Transistor gate Download PDFInfo
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- KR100338816B1 KR100338816B1 KR1019990058473A KR19990058473A KR100338816B1 KR 100338816 B1 KR100338816 B1 KR 100338816B1 KR 1019990058473 A KR1019990058473 A KR 1019990058473A KR 19990058473 A KR19990058473 A KR 19990058473A KR 100338816 B1 KR100338816 B1 KR 100338816B1
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000010409 thin film Substances 0.000 title claims abstract description 15
- 239000010408 film Substances 0.000 claims abstract description 18
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- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 230000000873 masking effect Effects 0.000 claims abstract description 4
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- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 230000008021 deposition Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000010586 diagram Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 1
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- 238000005468 ion implantation Methods 0.000 description 1
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- 230000003068 static effect Effects 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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Abstract
SRAM의 MOS 트랜지스터 및 박막 트랜지스터(TFT)의 게이트전극 형성방법에 대해 개시한다. 본 발명의 제조 방법은 소자분리막이 형성된 반도체 기판 상부에 게이트절연막 및 제 1도전층을 순차적으로 적층하며, NMOS 트랜지스터가 형성될 제 1영역을 마스킹한 후에 PMOS TFT가 형성될 제 2영역에 패드 절연막을 형성하며, 기판 전면에 제 2도전층을 증착한 후에, 제 1영역의 제 2도전층 및 제 1도전층을 패터닝하여 NMOS 트랜지스터의 게이트전극을 형성하며, 제 2영역의 제 2도전층을 패터닝하여 PMOS TFT의 게이트전극을 형성함으로써, NMOS 트랜지스터와 PMOS TFT의 게이트전극을 동일한 프로세스에서 형성함으로써 SRAM 제조 공정의 단계를 줄일 수 있다.A method of forming a gate electrode of an MOS transistor and a thin film transistor (TFT) of an SRAM is described. In the manufacturing method of the present invention, the gate insulating film and the first conductive layer are sequentially stacked on the semiconductor substrate on which the device isolation film is formed, and after masking the first region where the NMOS transistor is to be formed, the pad insulating film is formed in the second region where the PMOS TFT is to be formed. After the deposition of the second conductive layer on the entire surface of the substrate, the second conductive layer and the first conductive layer of the first region are patterned to form a gate electrode of the NMOS transistor, and the second conductive layer of the second region is formed. By patterning to form the gate electrode of the PMOS TFT, the steps of the SRAM manufacturing process can be reduced by forming the NMOS transistor and the gate electrode of the PMOS TFT in the same process.
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히 SRAM(Static Random Access Memory) 셀의 부하 소자(load device)로 채용하는 박막 트랜지스터(thin film transistor: 이하 'TFT'라 함)와 셀의 MOS 트랜지스터의 게이트전극을 동시에 형성할 수 있는 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, a thin film transistor (hereinafter referred to as a TFT) and a MOS transistor of a cell that are employed as a load device of a static random access memory (SRAM) cell. The present invention relates to a manufacturing method capable of forming the gate electrode at the same time.
일반적으로, 반도체 메모리 장치로서 SRAM은 DRAM(Dynamic Random Access Memory)에 비하여 메모리 용량에서는 떨어지지만, 고속이 가능하고 사용하기 쉽기 때문에 중·소용량의 메모리 분야에서 널리 사용되고 있다. SRAM의 메모리 셀은 일반적으로 2개의 전송 트랜지스터, 2개의 구동 트랜지스터, 및 2개의 부하소자로 이루어지는 2개의 플립플롭 (Flip Flop)회로로 구성된다. 기억정보는 플립플롭의 입,출력단자간의 전압차, 즉 실제로는 노드(node)에서의 부유용량에 축적된 전하로써 보존된다. 이 전하는 일정전원(VCC)으로부터 부하소자인 부하 MOS트랜지스터 또는 부하 저항을 통하여 항상 보충되고 있으므로, DRAM에서처럼 리플레쉬(refresh)기능은 불필요하게 된다.In general, as a semiconductor memory device, SRAM has a lower memory capacity than DRAM (Dynamic Random Access Memory), but is widely used in the medium and small memory fields because of its high speed and ease of use. The memory cell of an SRAM generally consists of two flip-flop circuits consisting of two transfer transistors, two drive transistors, and two load elements. The memory information is preserved as the voltage difference between the input and output terminals of the flip-flop, that is, the charge accumulated in the floating capacity at the node. This charge is always supplemented from a constant power supply (V CC ) through a load MOS transistor or a load resistor, which is a load element, so that a refresh function is unnecessary as in DRAM.
한편, SRAM의 메모리 셀은 셀을 구성하는 부하 소자로서, 디플레이션(depletion) NMOS 트랜지스터를 사용할 경우 그 소비전력이 매우 크기 때문에 오늘날 거의 사용되지 않고, 그 대신에 고저항 부하 소자로서 PMOS TFT를사용하게 되었다.On the other hand, memory cells of SRAM are rarely used today because of their large power consumption when using deflation NMOS transistors as a load element constituting the cell. Instead, PMOS TFTs are used as high resistance load elements. It became.
도 1은 SRAM 셀의 일반적인 회로도로서, 부하 소자로 PMOS 박막트랜지스터를 사용한 CMOS SRAM을 도시한 회로도이다.FIG. 1 is a general circuit diagram of an SRAM cell, showing a CMOS SRAM using a PMOS thin film transistor as a load element.
이를 참조하면, 종래 PMOS TFT를 갖는 풀 CMOS SRAM의 셀은 각각 전원전압(Vcc) 단자에 직렬로 연결되어 풀업 역할을 하는 부하 소자인 제 1 및 제 2PMOS TFT(16,18)와, 상기 접지 단자와 PMOS TFT(16,18)에 사이에 각각 연결되어 풀다운 역할을 하는 제 1 및 제 2NMOS 트랜지스터(20,22)로 이루어진다.Referring to this, cells of a full CMOS SRAM having a conventional PMOS TFT are first and second PMOS TFTs 16 and 18, which are load elements that are connected in series to a power supply voltage (Vcc) terminal and serve as pull-ups, respectively, and the ground terminal. And first and second NMOS transistors 20 and 22, respectively, connected to and between the PMOS TFTs 16 and 18 to serve as pull-downs.
그리고, 상기 풀 CMOS SRAM은 워드라인(WL)에 응답하여 비트라인(BL,/BL)의 데이터를 전송하는 NMOS형태의 제 1 및 제 2전송 트랜지스터(12,14)를 포함한다.The full CMOS SRAM includes first and second transfer transistors 12 and 14 of NMOS type which transfer data of bit lines BL and / BL in response to word lines WL.
여기서, 상기 제 1전송 트랜지스터(12)의 소오스에 제 1PMOS TFT(16) 및 제 1NMOS 트랜지스터(20)의 공통 노드가 연결되어 있다.Here, a common node of the first PMOS TFT 16 and the first NMOS transistor 20 is connected to the source of the first transfer transistor 12.
또한, 상기 PMOS TFT 및 NMOS 트랜지스터의 게이트전극은 상호 공통 연결되며 이 게이트전위는 서로 교차된 다른 PMOS TFT 및 NMOS 트랜지스터의 공통 노드를 통해서 다른 쪽 전송 트랜지스터의 소오스에 인가된다.In addition, the gate electrodes of the PMOS TFT and the NMOS transistor are commonly connected to each other, and the gate potential is applied to the source of the other transfer transistor through the common node of the other PMOS TFT and the NMOS transistor crossed with each other.
이러한 PMOS TFT를 갖는 SRAM 셀은 고속화, 고집적화, 저전압화에 대한 요구를 만족시키기 위하여 낮은 대기 전력, 저전압 하에서 셀 안정성 및 소프트 에러에 대한 내성 등 장점들을 구비하여 차세대 셀로서 많이 이용될 가능성을 가지고 있다.In order to satisfy the demand for high speed, high integration, and low voltage, an SRAM cell having such a PMOS TFT has many advantages as a next-generation cell with advantages such as low standby power, cell stability under low voltage, and resistance to soft errors. .
하지만, 종래 PMOS TFT를 갖는 SRAM의 제조 공정은 통상의 NMOS 트랜지스터를 제조한 후에, 풀업 소자로 동작하는 PMOS TFT를 제조하고 있다. 이는 서로 다른 소자 구성으로 이루어진 NMOS 트랜지스터와 PMOS TFT를 별도의 공정으로 나누어 제조하기 때문에 SRAM 제조 공정이 다소 복잡해졌다.However, in the conventional manufacturing process of an SRAM having a PMOS TFT, after manufacturing a conventional NMOS transistor, a PMOS TFT that operates as a pull-up element is manufactured. This makes the SRAM manufacturing process somewhat complicated because NMOS transistors and PMOS TFTs having different device configurations are manufactured in separate processes.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 NMOS트랜지스터와 PMOS TFT를 동시에 형성할 수 있어 제조 공정의 단계 수를 단축할 수 있는 SRAM의 MOS 트랜지스터 및 박막 트랜지스터의 게이트전극 형성방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a gate electrode of a MOS transistor and a thin film transistor of an SRAM, which can simultaneously form an NMOS transistor and a PMOS TFT to solve the above problems of the prior art. To provide.
도 1은 SRAM 셀의 일반적인 회로도로서, 부하 소자로 PMOS 박막트랜지스터를 사용한 CMOS SRAM을 도시한 회로도,1 is a general circuit diagram of an SRAM cell, and a circuit diagram showing a CMOS SRAM using a PMOS thin film transistor as a load element.
도 2a 내지 도 2f는 본 발명의 일실시예에 따른 SRAM의 MOS 트랜지스터 및 박막 트랜지스터의 게이트전극 형성방법을 나타낸 공정 순서도.2A to 2F are flowcharts illustrating a method of forming a gate electrode of an MOS transistor and a thin film transistor of an SRAM according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
100: 실리콘 기판100: silicon substrate
102: 소자분리막102: device isolation film
104: 게이트절연막104: gate insulating film
106: 제 1도전층106: first conductive layer
107,111,112: 포토레지스트 패턴107,111,112: photoresist pattern
108: 패드 절연막108: pad insulating film
110: 제 2도전층110: second conductive layer
G: NMOS 트랜지스터의 게이트전극G: gate electrode of NMOS transistor
G': PMOS TFT의 게이트전극G ': gate electrode of PMOS TFT
상기 목적을 달성하기 위하여 본 발명은 박막 트랜지스터를 포함하는 SRAM의 제조방법에 있어서, 소자분리막이 형성된 반도체 기판 상부에 게이트절연막 및 제 1도전층을 순차적으로 적층하는 단계와, MOS 트랜지스터가 형성될 제 1영역을 마스킹한 후에 박막 트랜지스터가 형성될 제 2영역에 패드 절연막을 형성하는 단계와, 기판 전면에 제 2도전층을 증착하는 단계와, 제 1영역의 제 2도전층 및 제 1도전층을 패터닝하여 MOS 트랜지스터의 게이트전극을 형성하는 단계와, 제 2영역의 제 2도전층을 패터닝하여 박막 트랜지스터의 게이트전극을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of manufacturing an SRAM including a thin film transistor, the method comprising sequentially depositing a gate insulating film and a first conductive layer on a semiconductor substrate on which an isolation layer is formed; After masking the first region, forming a pad insulating film in the second region where the thin film transistor is to be formed, depositing a second conductive layer on the entire surface of the substrate, and forming the second conductive layer and the first conductive layer in the first region. Patterning to form a gate electrode of the MOS transistor, and patterning a second conductive layer of the second region to form a gate electrode of the thin film transistor.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명의 일실시예에 따른 SRAM의 MOS 트랜지스터 및 박막 트랜지스터(TFT)의 게이트전극 형성방법을 나타낸 공정 순서도로서, 이를 참조하면 본 발명은 NMOS트랜지스터 게이트 전극 프로세스 중에 PMOS TFT의 게이트전극을 형성할 수 있다.2A to 2F are flowcharts illustrating a method of forming a gate electrode of an MOS transistor and a thin film transistor (TFT) of an SRAM according to an embodiment of the present invention. Referring to the present invention, the present invention relates to a PMOS TFT during an NMOS transistor gate electrode process. A gate electrode can be formed.
우선, 본 발명의 제조 공정은 도 2a에 도시된 바와 같이, 반도체 기판으로서 실리콘기판(100)에 소자분리 공정(isolation process)을 실시하여 소자의 활성 영역과 비활성 영역을 구분하는 소자분리막(102)을 형성한다. 여기서, A는 이후 NMOS 트랜지스터가 형성될 예정인 제 1영역이고, B는 이후 PMOS TFT가 형성될 예정 인 제 2영역이다.First, as shown in FIG. 2A, the manufacturing process of the present invention performs an isolation process on a silicon substrate 100 as a semiconductor substrate to separate an active region and an inactive region of a device. To form. Here, A is a first region where an NMOS transistor is to be formed later, and B is a second region where a PMOS TFT is to be formed later.
그 다음, 도 2b에 도시된 바와 같이, 소자분리막(102)이 형성된 기판 상부에 게이트절연막(104) 및 제 1도전층으로서 도프트 폴리실리콘(106)을 순차적으로 적층한다. 그리고, NMOS 트랜지스터가 형성될 제 1영역(A)을 마스킹하고 TFT가 형성될 제 2영역(B)을 개방하기 위한 마스크를 이용한 사진 공정을 진행하여 상기 결과물에 포토레지스트 패턴(107)을 형성하고, WF6가스를 이용하여 선 세정 공정을 실시한다.Next, as shown in FIG. 2B, the doped polysilicon 106 is sequentially stacked as the gate insulating film 104 and the first conductive layer on the substrate on which the device isolation film 102 is formed. Then, the photoresist pattern 107 is formed on the result by performing a photolithography process using a mask for masking the first region A in which the NMOS transistor is to be formed and opening the second region B in which the TFT is to be formed. , WF 6 gas is used for the pre-cleaning step.
도 2c에 도시된 바와 같이, 디글레이즈(deglaze) 공정을 실시하여 포토레지스트 패턴(107)에 의해 개방된 제 2영역(A)에 PMOS TFT 소자의 패드 절연막(108)을 형성한다. 이때, 패드 절연막(108)의 형성 공정은 WF6가스의 선세정 시간과 디글레이즈시 린스(rinse) 시간을 적당히 조정하면 상기 제 1도전층(106) 상부에 산화막이 형성된다. 그리고, 상기 포토레지스트 패턴(107)을 제거한다.As shown in FIG. 2C, the pad insulating film 108 of the PMOS TFT device is formed in the second region A opened by the photoresist pattern 107 by performing a deglaze process. In this case, in the process of forming the pad insulating film 108, an oxide film is formed on the first conductive layer 106 when the pre-cleaning time of the WF 6 gas and the rinse time when deglazing are properly adjusted. The photoresist pattern 107 is removed.
이어서, 도 2d에 도시된 바와 같이, 기판(100) 전면에 제 2도전층(110)으로서 도프트 폴리실리콘 또는 금속 실리사이드를 증착한다. 본 실시예에서는 텅스텐 실리사이드를 제 2도전층(110)의 물질로 이용한다.Next, as illustrated in FIG. 2D, doped polysilicon or metal silicide is deposited as the second conductive layer 110 on the entire surface of the substrate 100. In this embodiment, tungsten silicide is used as the material of the second conductive layer 110.
그 다음, NMOS 트랜지스터의 게이트 마스크를 이용한 사진 공정을 진행하여 상기 제 2도전층(110) 상부에 포토레지스트 패턴(111)을 형성한 후에, 건식 식각 공정을 이용하여 제 1영역(A)의 제 2도전층(110) 및 제 1도전층(106)을 패터닝하여 NMOS 트랜지스터의 게이트전극(G)을 형성한다.Next, the photoresist pattern 111 is formed on the second conductive layer 110 by performing a photolithography process using a gate mask of the NMOS transistor, and then a dry etching process is performed to The second conductive layer 110 and the first conductive layer 106 are patterned to form the gate electrode G of the NMOS transistor.
상기 포토 레지스트 패턴(111)을 제거한 후에, 도 2e에 도시된 바와 같이, PMOS TFT의 게이트 마스크를 이용한 사진 공정을 진행하여 상기 결과물에 포토레지스트 패턴(112)을 형성한다. 그리고, 건식 식각 공정을 이용하여 상기 포토레지스트 패턴(112)에 맞추어 제 2영역(B)의 제 2도전층(110)을 패터닝하여 PMOS TFT의 게이트전극(G')을 형성한다. 그리고, 상기 포토 레지스트 패턴(112)을 제거한 후에, NMOS트랜지스터 및 PMOS TFT의 게이트전극(G,G')에 맞추어 하부 게이트 절연막(104) 및 패드 절연막(108)을 식각한다. 이때, 제 2영역(B)에서 식각되지 않은 제 1도전층(106)인 도프트 폴리실리콘은 PMOS TFT의 기판으로 사용된다.After removing the photoresist pattern 111, as shown in FIG. 2E, a photoresist process using a gate mask of a PMOS TFT is performed to form a photoresist pattern 112 on the resultant. The second conductive layer 110 of the second region B is patterned to form the gate electrode G ′ of the PMOS TFT by using a dry etching process. After removing the photoresist pattern 112, the lower gate insulating layer 104 and the pad insulating layer 108 are etched in accordance with the gate electrodes G and G ′ of the NMOS transistor and the PMOS TFT. At this time, the doped polysilicon, which is the first conductive layer 106 not etched in the second region B, is used as the substrate of the PMOS TFT.
이후, NMOS 트랜지스터 및 PMOS TFT의 소오스/드레인 정션을 위한 이온 주입 공정을 실시하여 본 발명에 따른 SRAM 셀을 완성한다.Thereafter, an ion implantation process for source / drain junction of the NMOS transistor and the PMOS TFT is performed to complete the SRAM cell according to the present invention.
본 발명은 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적사상내에서 당 분야에서 통상의 지식을 가진자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.
상기한 바와 같이 본 발명은, NMOS트랜지스터와 PMOS TFT를 갖는 메모리 장치의 제조 방법에 있어, NMOS 트랜지스터 및 PMOS TFT의 게이트전극을 동일한 프로세스에서 진행할 수 있어 제조 공정의 단계 수를 크게 단축할 수 있는 이점이 있다.As described above, the present invention provides a method of manufacturing a memory device having an NMOS transistor and a PMOS TFT, in which the gate electrodes of the NMOS transistor and the PMOS TFT can be processed in the same process, thereby greatly reducing the number of steps in the manufacturing process. There is this.
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