KR100332745B1 - Picture-by-picture device of television receiver - Google Patents

Picture-by-picture device of television receiver Download PDF

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Publication number
KR100332745B1
KR100332745B1 KR1019940033712A KR19940033712A KR100332745B1 KR 100332745 B1 KR100332745 B1 KR 100332745B1 KR 1019940033712 A KR1019940033712 A KR 1019940033712A KR 19940033712 A KR19940033712 A KR 19940033712A KR 100332745 B1 KR100332745 B1 KR 100332745B1
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South Korea
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video signal
signal
horizontal
picture
signals
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KR1019940033712A
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Korean (ko)
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KR960028286A (en
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박중석
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엘지전자주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
    • H04N5/45—Picture in picture, e.g. displaying simultaneously another television channel in a region of the screen
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/22—Circuits for controlling dimensions, shape or centering of picture on screen
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/77—Circuits for processing the brightness signal and the chrominance signal relative to each other, e.g. adjusting the phase of the brightness signal relative to the colour signal, correcting differential gain or differential phase

Abstract

PURPOSE: A picture-by-picture device of a television receiver is provided to compress individual images in the horizontal direction and display the images in the same size and picture quality using one deflection signal. CONSTITUTION: A picture-by-picture device of a television receiver includes the first and second video signal processors(10,20), a memory read controller(26), a composite video signal output unit(30), and a horizontal and vertical driving signal output unit(40). The first video signal processor decimates a composite video signal and stores the decimated signal in a line memory. The second video signal processor decimates a composite video signal to store the signal in three field memories. The memory read controller reads the video signal stored in the line memory during the period corresponding to half of a horizontal active video period and reads the video signal stored in the field memories during the remaining period. The composite video signal output unit synthesizes the video signals output from the first and second video signal processors with each other and reproduces red, green and blue signals from the synthesized signal. The horizontal and vertical driving signal output unit receives horizontal and vertical driving signals from the first video signal processor to output horizontal and vertical deflection signals to a CPT.

Description

텔레비젼수상기의 픽쳐 바이 픽쳐 장치Picture-by-Picture Device of TV Receiver

본 발명은 텔레비젼수상기에서 확장된 피아피(Picture In Picture) 개념으로 픽쳐 바이 픽쳐(Picture by Picture) 기능을 구현하는 기술에 관한 것으로, 특히 독립적인 각각의 화상을 수평방향으로 압축한 후 하나의 편향신호를 이용하여 동일한 크기와 화질로 디스플레이하는데 적당하도록한 텔레비젼수상기의 픽쳐 바이 픽쳐 장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a technique for implementing a picture by picture function with the concept of extended in picture in a television receiver. Particularly, a single deflection is performed after each independent picture is compressed in a horizontal direction. A picture-by-picture apparatus of a television receiver adapted to display at the same size and quality using signals.

일반적인 텔레비젼수상기의 픽쳐 바이 픽쳐(더블 스크린) 수단에 있어서는 수평구동부와 수직구동부를 각각 두개씩 사용하여 원가가 상승되고, 제품의 사이즈가 커지게 되는 등의 결함이 있었다.In the picture-by-picture (double screen) means of a general television receiver, there are defects such as the cost increase and the size of the product increase by using two horizontal driving units and two vertical driving units.

따라서, 본 발명의 목적은 독립적인 각각의 화상을 수평방향으로 압축한 후 하나의 편향신호를 이용하여 동일한 크기와 화질로 디스플레이하는 장치를 제공함에 있다.Accordingly, an object of the present invention is to provide an apparatus for compressing each independent image horizontally and then displaying the same size and image quality using one deflection signal.

제1도는 상기의 목적을 달성하기 위한 픽쳐 바이 픽쳐 장치의 일실시 예시 블록도로서 이에 도시한 바와 같이, 복합영상신호(VIDEO1)를 샘플링한 후 휘도신호와 색신호를 분리하고, 그 분리된 색신호를 복조처리하여 Y,U,V 디지탈신호를 생성한 다음 상기 샘플링수의 절반 샘플로 그 Y,U,V 디지탈신호를 라인메모리에 저장하는 제1영상신호 처리부(10)와, 복합영상신호(VIDE02)를 샘플링한 후 휘도신호와 색신호를 분리하고, 그 분리된 색신호를 복조처리하여 Y,U,V 디지탈신호를 생성한 다음 상기 샘플링수의 절반 샘플로 그 Y,U,V 디지탈신호를 3개의 필드메모리에 저장하는 제2영상신호 처리부(20)와, 수평, 수직블랭킹신호를 이용하여 수평액티브 비디오구간(A)의 절반 구간동안 상기 라인메모리에 저장된 영상신호를 읽어내고, 나머지의 절반 구간동안 상기 필드메모리에 저장된 영상신호를 읽어내는 메모리 리드제어부(25)와, 상기 제1,2영상처리부(10),(20)에 출력되는 영상신호를 합성한 후 이로부터 적,녹,청색용 신호(R),(G),(B)를 복원해내는 합성영상신호 출력부(30)와, 상기 제1영상신호 처리부에서 각기 출력되는 수평구동신호(Ho)와 수직구동신호(Vo)를 공급받아 씨피티(CPT)에 수평,수직편향신호를 출력하는 수평,수직구동신호 출력부(40)로 구성한 것으로, 이와 같이 구성한 본 발명의 작용 및 효과를 첨부한 제2도 및 제3도를 참조 하여 상세히 설명하면 다음과 같다.FIG. 1 is a block diagram of an embodiment of a picture by picture apparatus for achieving the above object. As shown in FIG. 1, after sampling a composite video signal VIDEO1, a luminance signal and a color signal are separated, and the separated color signal is separated. A first video signal processor 10 for demodulating and generating a Y, U, V digital signal, and storing the Y, U, V digital signal in a line memory with half a sample of the sampling number; and a composite video signal (VIDE02). ), The luminance signal and the color signal are separated, and the separated color signal is demodulated to generate a Y, U, V digital signal, and the Y, U, V digital signal is converted into three samples with half the sample number. The second image signal processing unit 20 stored in the field memory and the horizontal and vertical blanking signals are used to read the image signal stored in the line memory during the half section of the horizontal active video section A, and the other half section. Above field Memory read control unit 25 for reading the image signal stored in the memory and the video signal output to the first, second image processing unit 10, 20, synthesized from there, the red, green, blue signal (R) ), (G), (B) receives the composite video signal output unit 30, and the horizontal drive signal Ho and the vertical drive signal (Vo) respectively output from the first video signal processor receives Consists of a horizontal, vertical drive signal output unit 40 for outputting a horizontal, vertical deflection signal to the tee (CPT), in detail with reference to FIGS. 2 and 3 attached to the operation and effect of the present invention configured as described above The explanation is as follows.

복합영상신호(VIDE01)가 아날로그(A)/디지탈(D)변환기(11)에 공급되어 샘플링클럭발생기(13)에서 출력되는 샘플클럭신호(fS1)에 의해 8bit로 샘플링되고, 그 복합영상신호(VIDE01)가 다른 한편으로는 블랭킹/편향구동신호 발생기(15)에 공급되어 이로부터 수평,수직 블랭킹신호(HBL1),(VBL1)와 수평,수직 구동신호(Ho),(Vo)가 출력된다.The composite video signal VIDE01 is supplied to the analog (A) / digital (D) converter 11 and sampled at 8 bits by the sample clock signal f S1 output from the sampling clock generator 13, and the composite video signal On the other hand, (VIDE01) is supplied to the blanking / deflection drive signal generator 15 from which the horizontal and vertical blanking signals H BL1 and V BL1 and the horizontal and vertical drive signals Ho and Vo are Is output.

상기 A/D변환기(11)에서 디지탈신호로 변환된 8bit의 영상신호는 휘도신호(Y)/색신호(C)분리 및 컬러복조부(12)에 공급되어 휘도신호와 색신호가 분리되고, 그 분리된 색신호가 복조처리되어 Y,U,V신호가 4:1:1 형태로 복원되어 12bit로 출력된다. 이때, 상기 샘플클럭신호(fS1)는 휘도신호와 색신호를 분리하는콤필터에 사용된다.The 8-bit video signal converted from the A / D converter 11 into the digital signal is supplied to the luminance signal Y / color signal C separation and the color demodulator 12 to separate the luminance signal and the color signal, and the separation thereof. The demodulated color signal is demodulated and the Y, U, and V signals are restored in a 4: 1: 1 form and output in 12 bits. In this case, the sample clock signal f S1 is used for a comb filter for separating the luminance signal and the color signal.

상기 12bit의 Y,U,V 디지탈신호는 제2도 (나)와 같은 라이트 인에이블 " 하이" 구간에 fS1/2의 주파수로 라인메모리(16)에 라이트(Write)된다. 즉, 샘플링클럭신호(fS1)로 샘플링된 데이타가 액티브라인동안 N 샘플이라면 상기 라인메모리(16)에는 N/2 샘플로 감축(decimation)되어 저장되는 것이다.The 12-bit Y, U, V digital signal is written to the line memory 16 at a frequency of f S1 / 2 in the write enable " high " section as shown in FIG. That is, if the data sampled with the sampling clock signal f S1 is N samples during the active line, the line memory 16 is reduced and stored as N / 2 samples.

한편, 복합영상신호(VIDE02)가 A/D변환기(21)에 공급되어 샘플링클럭발생기(23)에서 출력되는 샘플클럭신호(fS2)에 의해 8bit로 샘플링되고, 그 복합영상신호(V1DE02)가 다른 한편으로는 블랭킹신호 발생기(25)에 공급되어 이로부터 수평,수직 블랭킹 신호(HBL2),(VBL2)가 출력 된다.On the other hand, the composite video signal VIDE02 is supplied to the A / D converter 21 and sampled in 8 bits by the sample clock signal f S2 output from the sampling clock generator 23, and the composite video signal V1DE02 is On the other hand, it is supplied to the blanking signal generator 25 from which horizontal and vertical blanking signals H BL2 and V BL2 are output.

상기 A/D변환기(21)에서 디지탈신호로 변환된 8bit의 영상신호는 Y/C분리 및 컬러복조부(22)에 공급되어 휘도신호와 색신호가 분리되고, 그 분리된 색신호가 복조처리되어 Y,U,V신호가 4:1:1 형태로 복원되어 12bit로 출력된다. 이때, 상기 샘플클럭신호(fS2)는 휘도신호와 색신호를 분리하는 콤필터에 사용된다.The 8-bit video signal converted from the A / D converter 21 into a digital signal is supplied to the Y / C separation and color demodulator 22 to separate the luminance signal and the color signal, and the separated color signal is demodulated to Y. , U, V signals are restored in 4: 1: 1 format and output in 12bit. In this case, the sample clock signal f S2 is used for a comb filter for separating the luminance signal and the color signal.

상기 12bit의 Y,U,V 디지탈신호는 각각 4bit씩 4 × 256Kbit의 음량을 갖는 4입력 4출력의 필드메모리(26A),(26B),(26C)에 각기 라이트되는데, 이의 라이트 타임은 제2도의 (자)에서와 같은 라이트 인에이블 "하이" 구간, 제2도의 (타)와 같은 수직블랭킹신호(VBL2)의 "하이"구간에 fS2/2의 주파수에 의해 1/2로 감축되어 라이트된다.The 12-bit Y, U, and V digital signals are respectively written to the four-input four-output field memories 26A, 26B, and 26C, each having a volume of 4 x 256 Kbit, each of which is 4 bits. In the light enable " high " section as shown in (i) of FIG. 2 and the “high” section of the vertical blanking signal V BL2 as shown in (ta) of FIG. 2, the frequency is reduced by 1/2 by the frequency of f S2 / 2. Lighted.

상기 라인메모리(16)와 필드메모리(26A),(26B),(26C)의 리드 콘트롤은 메모리 리드제어부(26)에 의해 이루어지는데, 그 라인메모리(16)의 리드인에이블신호(RE1)의 "하이" 액티브구간이 제2도의 (가),(다)에서와 같이 수평액티브 비디오구간(A)의 절반구간(A/2)에 해당되고, 이 구간동안 샘플링클럭(fS1)의 주파수로 리드되므로 라인 메모리(16)에서는 수평방향으로 1/2추림된 영상신호가 출력된다.The read control of the line memory 16 and the field memories 26A, 26B, and 26C is performed by the memory read control unit 26. The read enable signal RE 1 of the line memory 16 is used. The "high" active interval of is equal to half (A / 2) of the horizontal active video interval (A), as in (a) and (c) of Figure 2, during which the frequency of the sampling clock (f S1 ) Since it is read as, the line memory 16 outputs an image signal rounded in the horizontal direction.

또한, 복합영상신호(VIDEO2)가 저장된 상기 필드메모리(26A),(26B),(26C)의 리드인에이블신호(RE2)의 "하이" 액티브구간이 제2도의 (가),(사)에서와 같이 수평액티브 비디오구간(A)의 나머지 절반구간(A/2)에 해당되는데, 이의 출력타이밍을 결정하기 위하여 제2도의 (카),(타)에서와 같이 복합영상신호(VIDEO1)의 수직블랭킹신호(VB1)와 복합영상신호(VIDE02)의 수직블랭킹신호(VB2)의 시차인 β만큼의 지연시간을 갖고 추가로 제2도의 (가),(차)에서와 같이 복합영상신호(VIDE01),(VIDE02)의 시차(D)만큼의 지연시간에 수평액티브 비디오구간의 절반구간(A/2)을 합한 γ를 더하여 즉, β+γ만큼의 지연시간을 갖은 후 제2도의 (사)에서와 같이 리드인에이블신호(RE2)를 "하이"로 출력하고, 이 구간에서 샘플링주파수(fS2)로 라인메모리(16)에 저장된 데이타를 읽어냄으로써 수평으로 1/2압축된 복합영상신호(VIDE02)가 출력된다.In addition, the "high" active section of the lead enable signal RE2 of the field memories 26A, 26B, and 26C in which the composite video signal VIDEO2 is stored is shown in (a) and (g) of FIG. It corresponds to the other half section (A / 2) of the horizontal active video section (A), as shown in (ka) and (ta) of FIG. 2 to determine the output timing thereof. It has a delay time equal to β, which is the time difference between the blanking signal V B1 and the vertical blanking signal V B2 of the composite video signal VIDE02, and further, as shown in (a) and (d) of FIG. VIDE01) and (VIDE02) delay time as the time difference (D) plus γ which is the half of the horizontal active video section (A / 2), ie, the delay time as β + γ As shown in Fig. 2, the read enable signal RE2 is output at high, and the data stored in the line memory 16 is read at the sampling frequency f S2 in this section. / 2 compressed composite video signal VIDE02 is output.

결국, 상기 라인메모리(16)와 필드메모리(26A-26C)의 출력은 복합영상신호(VIDEO1),(VIDE02)에 대해 수평으로 1/2압축되어 있으며, 스위치(SW)는 상기 리드인에이블신호(RE1)가 "하이"인 동안에 라인메모리(16)의 출력영상신호를 선택하고, 리드인에이블신호(RE1)가 "로우"인 동안에는 필드메모리(26A-26C)의 출력영상신호를 선택하여 출력하게 된다.As a result, the outputs of the line memory 16 and the field memories 26A-26C are compressed 1/2 horizontally with respect to the composite video signals VIDEO1 and VIDE02, and the switch SW is the lead enable signal. The output video signal of the line memory 16 is selected while the RE1 is "high", and the output video signal of the field memories 26A-26C is selected and output while the lead enable signal RE1 is "low". Done.

상기 복합영상신호(VIDEO2) 저장용으로 필드메모리(26A-26C)를 사용하는 이유는 복합영상신호(VIDE01)와 복합영상신호(VIDE02)가 실제로 전송될때 최대 1필드까지 지연될 수 있으므로 복합영상신호(VIDE02)를 충분히 지연시켜 복합영상신호(VIDEO1)의 동기에 맞출 수 있도록 하기 위함이다.The reason for using the field memories 26A-26C for storing the composite video signal VIDEO2 is that the composite video signal VIDE01 and the composite video signal VIDE02 may be delayed up to one field when the composite video signal VIDE01 is actually transmitted. This is to sufficiently delay (VIDE02) to synchronize with the composite video signal VIDEO1.

상기 스위치(SW)에서 합성 출력되는 12bit의 데이타는 디멀티플렉서 및 D/A변환기(31)에 의해 Y,U,V신호가 디멀티플렉싱되고, 그 U,V신호가 아날로그신호로 변환된 후 R,G,B 매트릭스(32)에서 적,녹,청색용 신호(R),(G),(B)로 변환된다.The 12-bit data synthesized and output from the switch SW are demultiplexed by the demultiplexer and the D / A converter 31, and the U, V signals are converted into analog signals, and then R, G In the matrix B, red, green, and blue signals R, G, and B are converted.

그리고, 상기 R,G,B매트릭스(32)에서 출력되는 적,녹,청색용 신호(R),(G),(B)는 증폭기(33)에 의해 디스플레이하는데 적당한 레벨로 증폭되어 씨피티(CPT)에 공급된다.The red, green, and blue signals R, G, and B output from the R, G, and B matrix 32 are amplified to a level suitable for display by the amplifier 33, and thus the CPT).

한편, 상기 수평구동부(41)는 상기 블랭킹/편향구동신호 발생기(15)에서 출력되는 수평구동신호(Ho)를 공급받아 증폭된 수평편향신호를 출력하게 되고, 수직구동부(42)는 그 블랭킹/편향구동신호 발생기(15)에서 출력되는 수직구동신호(Vo)를 공급받아 증폭된 수직편향신호를 출력하게 되며, 이 수평,수직편향신호에 의해 상기 씨피티(CPT)에 디스플레이되는 색신호(R),(G),(B)가 편향되며, 이 씨피티(CPT)의 디스플레이 형태는 상기의 복합영상신호(VIDE01),(VIDE02)의 처리과정에 의해 제3도와 픽처 바이 픽쳐 형태가 된다.Meanwhile, the horizontal driver 41 receives the horizontal drive signal Ho output from the blanking / deflection drive signal generator 15 and outputs an amplified horizontal deflection signal, and the vertical drive unit 42 blanks the signal. The vertical driving signal Vo output from the deflection driving signal generator 15 is supplied to output the amplified vertical deflection signal, and the color signal R displayed on the CPT is output by the horizontal and vertical deflection signals. , (G), (B) are deflected, and the display form of the CPT becomes the third degree and the picture-by-picture form by the processing of the composite video signals VIDE01 and VIDE02.

참고로, 하나의 화면에 하나의 복합영상신호만을 디스플레이하고자 하는 경우에는 제1영상신호 처리부(10)만을 사용하고, 제2영상신호 처리부(20)는 사용하지 않게 된다.For reference, when only one composite video signal is to be displayed on one screen, only the first video signal processor 10 is used and the second video signal processor 20 is not used.

이상에서 상세히 설명한 바와 같이, 본 발명은 두개의 복합영상신호를 각기 압축하여 저장한 후 이를 합성하여 출력하고, 하나의 편향신호를 이용하여 다른 2개의 동화면을 동일한 크기와 화질로 디스플레이함으로써 시청자에게 보다 다양한 화면을 제공할 수 있는 효과가 있으며, 특히 대형 와이드스크린에서 보다 양질의 화면을 제공할 수 있는 효과가 있다.As described in detail above, the present invention compresses and stores two composite video signals, synthesizes them, outputs them, and displays two different moving images at the same size and quality using one deflection signal. There is an effect that can provide a variety of screens, in particular the effect that can provide a better screen on a large widescreen.

제1도는 본 발명의 일실시예를 보인 텔레비젼수상기의 픽쳐 바이 픽쳐블록도.1 is a picture by picture block diagram of a television receiver according to one embodiment of the present invention;

제2도는 제1도 각부의 파형도.2 is a waveform diagram of each part of FIG.

제3도는 본 발명에 의한 픽쳐 바이 픽쳐 화면의 디스플레이 설명도.3 is an explanatory diagram of a display of a picture by picture screen according to the present invention;

*** 도면의 주요부분에 대한 부호의 설명 ****** Explanation of symbols for main parts of drawing ***

10 : 제1영상신호 처리부 11 : A/D 변환기10: first video signal processor 11: A / D converter

12 : Y/C 분리 및 컬러복조부 13 : 샘플링클럭 발생기12: Y / C separation and color demodulation unit 13: Sampling clock generator

14 : 샘플링클럭 분배기 15 : 블랭킹/편향구동신호 발생기14: sampling clock divider 15: blanking / deflection drive signal generator

16 : 라인메모리 20 : 제2영상신호 처리부16: line memory 20: second image signal processing unit

21 : A/D 변환기 11 : Y/C 분리 및 컬러복조부21: A / D converter 11: Y / C separation and color demodulation

23 : 샘플링클럭 발생기 24 : 샘플링클럭 분배기23: sampling clock generator 24: sampling clock distributor

25 : 블랭킹신호 발생기 26 : 메모리 리드제어부25: blanking signal generator 26: memory lead control unit

30 : 합성영상신호 처리부 31 : 디멀티플렉서 및 D/A변환기30: composite video signal processor 31: demultiplexer and D / A converter

32 : R,G,B매트릭스 33 : 증폭기32: R, G, B matrix 33: Amplifier

40 : 수평,수직구동신호 출력부 41 : 수평구동부40: horizontal and vertical drive signal output unit 41: horizontal drive unit

42 : 수직구동부42: vertical driving part

Claims (1)

복합영상신호(VIDE01)를 절반 수준으로 추림하여 라인메모리에 저장하는 제1영상신호 처리부(10)와, 복합영상신호(VIDE02)를 절반 수준으로 추림하여 3개의 필드메모리에 저장하는 제2영상신호 처리부(20)와, 수평, 수직블랭킹신호를 이용하여 수평액티브 비디오구간(A)의 절반 구간동안 상기 라인메모리에 저장된 영상신호를 읽어내고, 나머지의 절반 구간동안 상기 필드메모리에 저장된 영상신호를 읽어내는 메모리 리드제어부(26)와, 상기 제1,2영상처리부(10),(20)에 출력되는 영상신호를 합성한 후 이로부터 적,녹,청색용 신호(R),(G),(B)를 복원해내는 합성영상신호 출력부(30)와, 상기 제1영상신호 처리부(10)에서 출력되는 수평구동신호(Ho)와 수직구동신호(Vo)를 공급받아 씨피티(CPT)에 수평,수직편향신호를 출력하는 수평,수직구동신호 출력부(40)로 구성한 것을 특징으로 하는 텔레비젼수상기의 픽쳐 바이 픽쳐 장치.The first video signal processor 10 which decodes the composite video signal VIDE01 to half level and stores it in the line memory, and the second video signal which decodes the composite video signal VIDE02 to half the level and stores it in three field memories. Reads the video signal stored in the line memory during the half section of the horizontal active video section A and the video signal stored in the field memory for the remaining half section by using the processing unit 20 and the horizontal and vertical blanking signals. It synthesizes the video signal output to the memory read control unit 26 and the first and second image processing units 10 and 20, and thereafter, red, green, and blue signals (R), (G), ( B) to restore the composite video signal output unit 30 and the horizontal drive signal Ho and the vertical drive signal Vo output from the first video signal processor 10 to the CPT. The horizontal and vertical drive signal output unit 40 outputs a horizontal and vertical deflection signal. A picture-by-picture device for a television receiver.
KR1019940033712A 1994-12-12 1994-12-12 Picture-by-picture device of television receiver KR100332745B1 (en)

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KR1019940033712A KR100332745B1 (en) 1994-12-12 1994-12-12 Picture-by-picture device of television receiver

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KR1019940033712A KR100332745B1 (en) 1994-12-12 1994-12-12 Picture-by-picture device of television receiver

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KR100332745B1 true KR100332745B1 (en) 2002-11-22

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