KR100331276B1 - Circuit lay-out of DRAM - Google Patents

Abstract

The present invention relates to a circuit arrangement of a DRAM, and includes a bit line sense amplifier located between cell array blocks, a Y decoder located at the bottom of the bit line sense amplifiers and cell array blocks, and a side of the cell array blocks, respectively. A plurality of memory banks composed of X decoders are arranged in a predetermined direction, bit lines are positioned in the predetermined direction through the memory banks, and an input / output sense amplifier block is positioned at one end of the bit lines. According to the present invention, by stacking a plurality of memory banks in a predetermined direction and using a bit line and an input / output sense amplifier block in common, when the general SDRAM is applied to an embedded DRAM, the input / output interface can be facilitated and the chip area can be reduced.

Description

Circuit lay-out of DRAM

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to circuit arrangement of a semiconductor random access memory (DRAM), and more particularly to a circuit arrangement of an embedded DRAM for mounting in a semiconductor MML device.

In general, semiconductor memory is used in the form of main memory located inside a computer, embedded memory in a microprocessor, and cache memory. In addition, semiconductor memories can be roughly divided into RAMs and ROMs according to cell types, and there is S (Synchronous) DRAM that can operate at high speed as one type of RAM. In order to mount such an SDRAM into an embedded memory, a circuit arrangement should be designed considering the chip area and the input / output interface.

Figure 1 shows a circuit arrangement of a conventional general SDRAM. As shown in Fig. 1, a general SDRAM includes a plurality of memory banks (10), (12), (14), (16), and memory banks (10) and (12). A bank selector 18 is provided for selecting, 14, 16.

The memory bank 10 senses and amplifies data stored in a cell array block 112 in which memory cells are arranged in an array form, and data stored in a memory cell of the cell array block 112. A bit line sense amplifier block 111 to be output through the Y, a Y decoder block 113 for selecting a column address of the cell array block 112, and a row of the cell array block 112 X decoder block 115 for selecting an address and an input / output sense amplifier for sensing and amplifying the data carried on the bit line IO and outputting the data to the outside or storing the data supplied from the cell in the cell array block 112. Block 114.

The memory banks 12, 14, and 16 are configured in the same manner as the memory bank 10 described above.

In a general SDRAM configured as described above, when an address of a desired memory is supplied from an address buffer (not shown), the bank selector 18 selects one of the memory banks 10, 12, 14, and 16. The bank select signals bo0 to bo3 are generated for selection. By the bank selection signals bo0 to bo3, for example, when the memory bank 10 is selected, the X decoder block 115 and the Y decoder block 113 operate. Accordingly, a word line (not shown) and a bit line IO of the cell array block 112 are selected, and data of the corresponding memory cell is output or stored in the memory cell according to the selection.

However, when the general SDRAM arranged as described above is applied to the MML as it is, the data line (not shown) connected to the input / output sense amplifier block 114 is located at the center of the cell array, and thus the input / output interface with the peripheral circuit is not easy. In addition, the input / output sense amplifier block 113 is required for each of the memory banks 10, 12, 14, and 16, which is not advantageous in terms of chip area.

2 is a block diagram showing another example of a circuit arrangement of a general SDRAM. In the SDRAM shown in FIG. 2, as in FIG. 1, four memory banks 20, 24, 26, and 30, and a bank selector 22 for selecting the memory banks 20 and 24 are selected. And a bank selector 28 for selecting the memory banks 26 and 30.

As shown in FIG. 1, the memory bank 20 includes a cell array block 212, a bit line sense amplifier block 211, a Y decoder block 213, an X decoder block 215, and an input / output sense amplifier block ( 214). The remaining memory banks 24, 26, and 30 are configured in the same manner as the memory bank 20.

In the general SDRAM configured as described above, the memory banks 20, 24, 26, and 30 are disposed in the horizontal direction, and the input / output sense amplifier blocks are disposed at the bottom thereof, respectively. The bank selector 22 selects one of the memory banks 20 and 24 using the bank select signals bo0 and bo1, and the bank selector 22 selects the bank select signals bo2 and ( bo3) is used to select one of the memory banks 26 and 30.

Therefore, according to the SDRAM arranged as shown in FIG. 2, the input / output interface with the peripheral circuit can be easily achieved, but the input / output sense amplifier block is required for each of the memory banks 20, 24, 26, and 30. This also has disadvantages in terms of chip area.

Accordingly, the present invention has been made to solve such a problem, and by stacking a plurality of memory banks in a predetermined direction and using a bit line and an input / output sense amplifier block in common, an input / output interface when a general SDRAM is applied to an embedded DRAM It is an object of the present invention to provide a circuit arrangement of the DRAM which can facilitate the operation and reduce the chip area.

1 is a block diagram showing a circuit arrangement of a typical SDRAM.

2 is a block diagram showing another example of a circuit arrangement of a general SDRAM.

3 is a block diagram illustrating a circuit arrangement of an embedded SDRAM according to an embodiment of the present invention.

4 is a block diagram showing a circuit arrangement of an embedded SDRAM according to another embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

40, 42, 50, 52: Memory bank 44, 54: I / O sense amplifier blocks

46, 56: Bank selector 411, 512: Bit line sense amplifier block 412, 513: Cell array block 413, 514: Y decoder block

414,515: X decoder

The present invention for achieving the above object is located in the bit line sense amplifiers located between the cell array blocks, the bit line sense amplifiers and the side of the cell array blocks and the Y decoder located at the bottom of the cell array blocks, respectively. A plurality of memory banks composed of X decoders are disposed in a predetermined direction, bit lines are positioned in the predetermined direction through the memory banks, and an input / output sense amplifier block is positioned at one end of the bit lines.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram illustrating a circuit arrangement of an embedded SDRAM according to an embodiment of the present invention. According to an embodiment of the present invention shown in Figure 3, a plurality of memory banks 40, 42 are arranged in a stacked form sequentially in a predetermined direction, for example, a horizontal direction. The plurality of memory banks 40 and 42 use the bit line IO and the input / output sense amplifier block 44 in common, and are selected by the bank selector 46, and the input / output sense amplifier block 44 is selected. Is connected to a data line (not shown) for data input and output with the outside. Here, although only two memory banks 40 and 42 are shown, the number of bank selection signals bo0 to bo3 output from the bank selector 46 is arranged.

The memory bank 40 detects and amplifies data stored in a cell array block 412 in which memory cells are arranged in an array, and stored in a memory cell of the cell array block 412. Of the bit line sense amplifier block 411 outputted through the bit line IO, the Y decoder block 413 for selecting the column address of the cell array block 412, and the cell array block 412 X decoder block 414 for selecting the low address.

The memory bank 42 is configured in the same manner as the memory bank 40.

The input / output sense amplifier block 44 writes an input / output sense amplifier circuit for sensing and amplifying data loaded on the bit line IO, and writes the data loaded on the data line to the bit line sense amplifier block 411. And a light driving circuit.

According to the exemplary embodiment of the present invention, the plurality of memory banks 40 and 42 may use the bit line IO and the input / output sense amplifier block 44 in common, in terms of chip area. More advantageously, since one input / output sense amplifier block 44 is located at the lower ends of the memory banks 40 and 42, it is advantageous in terms of an interface for inputting and outputting data.

At this time, since only the X decoder and the Y decoder of the corresponding memory bank are operated by the bank selection signals bo0 to bo3, a collision by data from another memory bank does not occur in the commonly used bit line IO. .

4 is a block diagram showing a circuit arrangement of an embedded SDRAM according to another embodiment of the present invention. In another embodiment of the present invention, like the embodiment of FIG. 3, the plurality of memory banks 50 and 52 are sequentially stacked in a predetermined direction, for example, in a horizontal direction, and the plurality of memories are stacked. The banks 50 and 52 are arranged to use the bit line IO and the input / output sense amplifier block 54 in common.

The memory bank 50 includes a cell array block 513, a bit line sense amplifier block 512, a Y decoder block 514, and an X decoder block 515 as shown in FIG. An input / output precharge block 511 is further provided to precharge data on the line IO. The memory bank 52 is configured in the same manner as the memory bank 50.

In the above-described circuit arrangement as shown in FIG. 3, when the number of banks increases or the area occupied by the unit bank in the vertical direction is large, the length of the bit line IO is increased. Therefore, the precharge time of the bit line IO is increased during the data read / write operation. In consideration of this point, in another embodiment of the present invention, the precharge time can be reduced by inserting a precharge circuit in the middle of the bit line IO. In this case, even if the input / output precharge block 511 is arranged for each of the memory banks 50 and 52, the chip area can be reduced compared to the arrangement of the input / output sense amplifier blocks for each memory bank as in the prior art. That is, the precharge circuit constituting the input / output precharge block 511 is composed of only a few transistors, whereas the input / output sense amplifier circuit constituting the input / output sense amplifier block mainly uses a differential sense amplifier. Even if the input / output precharge block 511 is disposed in each of the memory banks 50 and 52, it is advantageous in terms of chip area than before.

As described above, the present invention stacks a plurality of memory banks in a predetermined direction and uses a bit line and an input / output sense amplifier block in common, thereby facilitating an input / output interface and a chip area when a general SDRAM is applied to an embedded DRAM. Can be reduced.

Claims (4)

A plurality of memory banks comprising a bit line sense amplifiers located between cell array blocks, a bit line sense amplifiers, a Y decoder located at the bottom of the cell array blocks, and an X decoder located on the side of the cell array blocks. And a bit line is disposed in the predetermined direction through the memory banks, and an input / output sense amplifier block is positioned at one end of the bit lines. The method of claim 1, wherein the X decoder and the Y decoder is A circuit arrangement of a DRAM, characterized in that for selectively operating for each memory bank by the signals applied from a bank selector. The method of claim 1, wherein the input and output sense amplifier block is An input / output sense amplifier circuit for sensing and amplifying data transferred from the bit line sense amplifier block to the bit line; And And a write driver circuit for writing data loaded on a data line to the bit line sense amplifier block. The method of claim 1, wherein the memory banks are And an input / output precharge block for precharging data to a bit line.