KR100311500B1 - Skipable boundary scan cell - Google Patents

Abstract

The present invention relates to a skippable boundary scan cell which skips unnecessary boundary scan cells and reduces the test time by reducing the number of shift cycles in a non-boundary scan cell test using a boundary scan cell. A first multiplexer that inputs system data and test data according to a mode, selects one of them, and outputs one of them; A second flip-flop connected in series with the flop and branched between the first flip-flop and the second flip-flop having the update signal as a clock signal. The third flip-flop to receive and output the output signal of the first flip-flop in the normal mode And a second multiplexer for selecting and outputting any one of system data and an output of the second flip-flop, a first switching element controlled by an output signal of the third flip-flop and selectively outputting the output of the first flip-flop; And a second switching element controlled by the output signal of the third flip-flop and outputting the output of the first multiplexer as test data in the test mode.

Description

Skipable boundary scan cell {SKIPABLE BOUNDARY SCAN CELL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to testing a non-boundary scan chip on a system board by using a chip on which boundary scan cells are implemented. A skippable boundary scan cell that can reduce shifting cycles by skipping boundary cells.

Hereinafter, a conventional boundary scan cell will be described with reference to the accompanying drawings.

1 is a block diagram of a boundary scan cell according to the prior art.

As shown in FIG. 1, two multiplexers 11 and 14 and two flip-flops 12 and 13 are included.

That is, a first multiplexer 11 for inputting and outputting system data and test data, and a first flip-flop that receives data from the first multiplexer 11 and outputs it as test data or transfers it to an input of a second flip-flop. (12), a second flip-flop (13) which receives the output of the first flip-flop (12) and delivers it to a second multiplexer, inputs the output of the second flip-flop (13) and system data And a second multiplexer 14 for outputting system data.

The first multiplexer 11 inputs system data and test data, selects one of them, and transfers the selected data to the first flip-flop 12.

The second multiplexer 14 inputs the output of the second flip-flop 13 and system data, selects one of them, and outputs the selected data.

Such a conventional boundary cell directly outputs system data through the second multiplexer 14 in a normal mode.

However, in the test mode, first, the test pattern is shifted through the process of test data input-first multiplexer-first flip-flop-date data output, and the shifted test pattern is second flip-flop. Output to system through 13 is used for test.

In this case, as shown in FIG. 2, if there is no boundary scan cell on another chip connected to the system data output pin, the boundary scan cell serves as a control point of the non-boundary scan chip. .

In addition, the test result of the non-boundary scan chip is used as an input of another boundary scan chip so that the boundary scan cell serves as an observing point of the non-boundary scan chip.

For reference, FIG. 2 illustrates a testing process of a non-boundary scan chip.

However, the above conventional boundary scan cells have the following problems.

In order to test a non-boundary scan chip, a vector to be tested must be shifted through the boundary scan chip. Unnecessary cells may exist during the test of the boundary scan chips.

However, according to the related art, as the unnecessary cell is also shifted, the total vector size and the number of shift cycles are increased, thereby increasing the time required for the test.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and provides a skippable boundary scan cell that can significantly reduce the number of shift cycles by skipping unnecessary cells, thereby shortening the test time. Its purpose is to.

1 is a block diagram of a boundary scan cell according to the prior art

Figure 2 is a state diagram showing a test process according to the prior art

3 is a block diagram of a skippable boundary scan cell of the present invention

4 is a state diagram showing a test process according to the present invention

Explanation of symbols for main parts of the drawings

21,25: first and second multiplexer

22,23,24: 1st, 2nd, 3rd flip-flop

The skippable boundary scan cell of the present invention for achieving the above object comprises a first multiplexer for inputting system data and test data and selecting one of the system data and the test data according to the shift mode or the load mode, and the first multiplexer in the normal mode. A first flip-flop that is outputted by receiving the output signal of the multiplexer, and is skipped in a test mode, a second flip-flop connected in series with the first flip-flop, and having an update signal as a clock signal, and the first flip-flop A third flip-flop branched between the second flip-flops and receiving a clock signal as a result of NAND operation of a skip control signal and a load clock signal, and receiving and outputting a signal output from the first flip-flop in normal mode; A second mode in which one of the system data and the output of the second flip-flop is selected and output in the normal mode A multiplexer, a first switching element controlled by the output signal of the third flip-flop and selectively outputting the output of the first flip-flop, and controlled by the output signal of the third flip-flop and in the test mode And a second switching element for outputting the output of the first multiplexer as test data.

Hereinafter, a skippable boundary scan cell of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram of a skippable boundary scan cell of the present invention.

As shown in FIG. 3, the first and second multiplexers 21 and 25, the first and second flip flops 22, 23, and 24, and the first and second switching elements T1, T2).

That is, a first multiplexer 21 that inputs system data and test data and selectively outputs any one of them, a first flip-flop 22 that receives and outputs an output of the first multiplexer 21, and the first multiplexer 21. A second flip-flop 23 connected in series with the flip-flop 22, a third flip-flop 24 branched between the first flip-flop 22 and the second flip-flop 23, and the second flip-flop 24. A second multiplexer 25 that receives the output of the second flip-flop 23 and the system data and selects one of them, and is controlled by the output of the third flip-flop 24 to control the first flip-flop ( A first switching element 26 for outputting the output of 22 as test data and a signal applied to an output terminal of the first switching element T1 and controlled by the output of the third flip-flop 24. And a second switching element T2 that feeds back the flip-flop 22.

The clock signal of the third flip-flop 24 is input with a result value according to a NAND operation between a load clock signal and a skip control signal.

The first and second switching elements T1 and T2 are formed of transistors, the first switching element T1 is formed of PMOS transistors, and the second switching element T2 is formed of NMOS transistors. .

Such a skippable boundary scan cell of the present invention operates in the normal mode as in the prior art, but in the test mode, the first and second switching elements may be used according to the output value of the third flip-flop 24. The first flip-flop 22 may be skipped through the on / off of T1 and T2.

The skip control signal is an output of a 1-bit flip-flop added to the TAP controller, as shown in FIG. 4, initialized upon instruction input, and cleared when exiting Exit 1-DR.

On the other hand, the third flip-flop 24 has an initial value of '0'.

Such an operation of the skippable boundary scan cell of the present invention will be described in detail with reference to FIGS. 3 and 4.

As shown in FIG. 4, when a test vector is directly inputted from A to C (see FIG. 3) when inputting a test vector, it is possible to obtain an effect of skipping hatched cells in FIG. 2.

To do this, first, the skip controller register is initialized when an instruction is input. When the skip controller register is initialized to '1', it enables skipping of boundary scan cells of the current chip, and if it is initialized to '0', skipping is impossible.

Once initialized, the initialized value is maintained until a DR (Destination Register) scan to use the setting of the third flip-flop 24.

The third flip-flop 24 is set through a DR scan.

In the shift-DR state, data necessary for setting the third flip-flop 24 of each cell is shifted through a scan chain. At this time, the load clock signal is kept low to prevent the third flip-flop 24 from being set to incorrect data.

After the data of the third flip-flop 24 of all the cells is shifted, the TAP controller transitions to the Exit 1-DR state, and in synchronization with this, a load clock signal is generated to set the third flip-flop 24 to a desired value. Update

At this time, if the value of the third flip-flop 24 is '0', the same function as the conventional cell, and if the value of the third flip-flop 24 is '1', a path of A-T2-C is formed. The first flip-flop 22 is skipped when the test vector is shifted.

Thereafter, when the update of the third flip-flop 24 is completed, the TAP controller transitions from the shift-DR state to the pause-DR state. At this time, the skip control signal transitions to '0' and the subsequent test vector. The third flip-flop 24 is prevented from being updated due to unnecessary data during scan shift.

The TAP controller transitions to the shift-DR state again via Exit 2-DR, and then starts the shift process of the vectors (test input of the non-boundary scan chip) necessary for the actual test.

The following process is the same as the general boundary scan test process.

As described above, by skipping unnecessary boundary scan cells when testing a non-boundary scan chip using boundary scan cells, the time required for the entire test can be shortened by minimizing the shift cycle and the vector size of the test pattern. It is possible to reduce the cost accordingly.

Claims (2)

A first multiplexer which inputs system data and test data according to the shift mode or the load mode, selects one of them, and outputs the selected one; A first flip-flop that is output in response to the output signal of the first multiplexer in the normal mode, and skipped in the test mode, A second flip flop connected in series with the first flip flop and using an update signal as a clock signal; It is branched between the first flip-flop and the second flip-flop and receives a clock signal from a NAND operation of a skip control signal and a load clock signal, and receives and outputs a signal output from the first flip-flop in normal mode. The third flip-flop, A second multiplexer for selecting and outputting any one of the system data and the output of the second flip-flop in the normal mode; A first switching element controlled by the output signal of the third flip-flop and selectively outputting the output of the first flip-flop; And a second switching element controlled by an output signal of the third flip-flop and configured to output the output of the first multiplexer as test data in a test mode. 2. The skippable boundary scan cell of claim 1, wherein the first switching element is a PMOS transistor and the second switching element is an NMOS transistor.