KR100301294B1 - Apparatus for processing data by a byte in optical transmission system - Google Patents

Abstract

The present invention is to process data in the unit of byte in the optical transmission system, the present invention converts the input data and the clock of the unit of the unit of byte and the amount of data in the state that the loss of data is prevented by using the buffer An increase / decrease data loss prevention unit; The data loss prevention unit is composed of a stuffing management unit that outputs data and a clock according to a desired format by performing stuffing management while storing the data having increased speed in a buffer, and performing data processing by byte unit to process by bit unit. It can reduce the heat generated, prevent data slip and can process data at high speed.

Description

Apparatus for processing data by a byte in optical transmission system}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer processing apparatus of an optical transmission system, and more particularly, to perform data processing in units of bytes, thereby reducing heat generated when processing in units of bits, preventing data slip, and making it suitable for processing data at high speed. A byte unit data processing apparatus of a system.

In order for a DS3 / E3 signal, typically a Pleisynchronous Digital Hierarchy (PDH) signal, to be converted to an AU3 / TU3 signal, which is a Synchronous Digital Hierarchy (SDH) signal, the first in first out First-in, first-out) is inevitable. The FIFO is also used as a translation medium for signals with different clocks, also called elastic buffers.

1 is a block diagram of a bit unit buffer processing apparatus of a conventional optical transmission system.

As shown therein, a free run counter 1 for counting an input clock of 45 MHz; A read counter 2 for counting an input clock of 51 MHz; A filling determination unit (3) which reads a write address from the free run counter (1) and reads a read address from the read counter (2) to determine whether the maximum value of the counter is filled; An AU3 / TU3 format generation unit 4 for receiving a 51 MHz clock to generate an AU3 / TU3 format, and a logical sum element 5 for ORing the outputs of the filling determination unit 3 and the AU3 / TU3 format generation unit 4. Wow; The buffer 6 is configured to read DS3 / E3 data bit by bit according to an input 45 Mhz clock and read data using a 51 Mhz clock according to the read enable signal of the logical sum element.

The configuration of such a conventional apparatus will be described again as follows.

First, in the conventional buffer technology, signal processing in units of bits is the center.

Thus, the process of writing data to the buffer 6 is as follows. That is, it stores the incoming DS3 / E3 signal in the buffer (6) at 45Mhz. At this time, the position of the data entered into the buffer 6 should be known using the 128 free run counter 1. Thus, every one clock, the free run counter 1 increments the count value by one and writes one bit into the buffer 6. When the clock reaches 128, the free run counter 1 counts again from the beginning to increase the count value by one, and the buffer 6 continuously writes the DS3 / E3 data by one bit, and the free run counter 1 Transmits the write address signal to the filling determination unit 3.

The process of reading from the buffer 6 is as follows. That is, the read counter 2 is made in accordance with the AU3 / TU3 frame structure. The buffer 6 reads out the data corresponding to the count value (lead address) according to the read counter 2 produced. The overhead (poh) is added to the read value to generate an AU3 / TU3 signal.

In addition, the process of controlling the buffer 6 is as follows. That is, the filling determination unit 3 receives the address of the data written to the buffer 6 in the free run counter 1 and the address read from the buffer 6 in the read counter 2. When the difference between the two addresses is larger than 64, which is the middle point of the buffer, one more bit of the read count 2 is read to prevent the buffer level from increasing. (The buffer level is always going up.)

Referring to the operation of the conventional device configured as described above in detail.

First, in order to write to the buffer 6, the 128 addresses operating at a 45 MHz clock store data in the buffer according to the value of the free-run counter 1. This buffer is used when the frequency of the input clock and the output clock is different, and the size of data passing through the buffer 6 is reduced. The 128-stage buffer 6 is a medium for storing data. When one data is written to the buffer, the write address is increased by 1, and when the data is read one by one, the read address is increased by one. Therefore, by adjusting the read speed, you can map AU3 / TU3 frames without losing data.

When the read enable signal input from the OR circuit 5 is high for reading from the buffer 6, the previous address is extracted from the data in the buffer 6 while increasing the read address of the buffer by one. The resulting data is not only one clock in size, but also in multiple clocks, and does not match the AU3 / TU3 frame structure. However, since it is set to the 51MHz clock, it is easy to attach poh or pointer. Attaching a poh or pointer produces a complete AU3 / TU3 signal.

In addition, in order to control the buffer 6, the addresses of the buffer 6 are latched once per subframe based on the AU3 signal. So if the result is 64 or higher, make the stuff enable signal value '1' or '0'. When the value of the stuff enable signal is '1', it means that one bit of data is read from the buffer 6 more than usual, so that the overflow of the buffer 6 can be prevented. Combining this stuff enable signal with the original read enable signal can read 621 or 622 bits of data into approximately AU3 subframes.

However, such a conventional device has a problem in that a lot of heat is generated because the operation in the bit unit.

In addition, at a high speed of 51 MHz, the time interval for processing a signal is very small, and thus, the timing interval is reduced so that a data slip may occur.

Accordingly, the present invention has been proposed to solve the conventional problems as described above, and an object of the present invention is to perform data processing in units of bytes to reduce heat generated during processing in units of bits, to prevent data slip, and to achieve high speed. The present invention provides a byte-based data processing apparatus of an optical transmission system capable of processing data.

1 is a block diagram of a bit unit buffer processing apparatus of a conventional optical transmission system,

2 is a block diagram of a byte-based data processing apparatus of the optical transmission system according to the present invention;

3 is a detailed configuration diagram of the first control generation unit in FIG. 2;

FIG. 4 is a detailed configuration diagram of the second control generator in FIG. 2.

Explanation of symbols on the main parts of the drawings

10: data loss prevention unit 11: clock conversion unit

12: first control generator 13: first buffer

20: stuffing management unit 21: second control generation unit

22: second buffer

In order to achieve the above object, the byte unit data processing apparatus of the optical transmission system according to the present invention,

A data loss prevention unit converting the input bit unit data and the clock unit into byte units and increasing / decreasing the speed of data in a state where data loss is prevented using a buffer; The technical configuration is characterized in that the data loss prevention unit is made of a stuffing management unit for outputting the data and the clock in accordance with the desired format by performing the stuffing management while storing the data of the increased speed in the buffer.

Hereinafter, an embodiment according to the technical concept of the byte unit data processing apparatus of the present invention as described above is as follows.

2 is a block diagram of a byte-based data processing apparatus of the optical transmission system according to the present invention.

As shown therein, a data loss prevention unit 10 converts the input data and the clock in byte units and increases / decreases the speed of data in a state where data loss is prevented by using a buffer; The data loss prevention unit 10 includes a stuffing management unit 20 for outputting data and a clock according to a desired format by performing stuffing management while storing data having an increased speed in a buffer.

The data loss prevention unit 10 includes a clock converter 11 for converting an input clock and data in a unit of bits into units of bytes; A first control generation unit 12 for comparing the write address and the read address of the first buffer 13 to determine the level of the buffer and maintaining a constant interval between the write address and the read address; A first buffer 13 receives the data and the clock of the clock converter 11 and outputs the data and the clock at an increased speed according to the control signal of the first control generator 12.

The stuffing manager 20 may generate a control signal by comparing a write address and a read address of the second buffer 22 and perform stuffing to output data and a clock according to a desired format. 21); The data loss prevention unit 10 receives a data, a clock, and a control signal under the control of the second control generator 21, and is configured as a second buffer 22 for outputting data and a clock in a desired format.

FIG. 3 is a detailed configuration diagram of the first control generation unit in FIG. 2.

As shown in the figure, a counter 31 receives a clock and counts a necessary interval so that data can be read without data loss; Enable generation means (32) for generating an enable signal to the counter (31); The write address and the read address of the clock are read from the first buffer 13 according to the latch signal output from the enable generating means 32. The positive and negative goings of the clock are positive and negative. Latch means 33 for latching when; Value extracting means (34) for obtaining a value of a write read address and a write read address buffer from the value latched by the latch means (33); Stuffing signal generating means (35) for receiving the value obtained by the value extracting means (34) to generate and output a stuffing enable signal to the counter (31); Compensation means (36) for receiving the output of the stuffing signal generating means (35) and the output of the enable generating means (32) to compensate for the phases of the control signal and the data output; Calculation means (37) for receiving the read enable signal of the enable generating means (32) and calculating a read address and the number of bits to be included in one byte according to a control signal; Address determination means 38 for receiving a result output from the calculation means 37 and determining an address for each of 8 bits so as to output a signal for mapping the data of the bit unit stored in the first buffer 13 in order of the byte unit. It is composed of

FIG. 4 is a detailed configuration diagram of the second control generator in FIG. 2.

As shown therein, a count 41 for receiving a clock and outputting a count value at regular intervals; Enable generating means (42) for generating an enable signal in accordance with the count value output from said count (41); Write calculation means (43) for receiving the output of the compensation means (36) in the first control generator (12) and calculating the write address and the number of bytes to be included in one byte according to the control signal; Write address determination means (44) for determining the address of each of the eight bits by the signal received from the write calculation means (43); Mapping determination means (45) for outputting a signal for mapping the values of the second buffer (22) in order according to the output of the write address determination means (44); Read calculation means (46) for receiving an output of the enable generating means (42) and calculating a read address and the number of bytes to be included in one byte according to a control signal; Read address determination means (47) for determining the address of each of the eight bits by the signal received from the read calculation means (46); Latch means (48) for latching the write-read address output from the write and read calculation means (43) (46) when the clock is positively gotten; Value extracting means (49) for obtaining a write-read address from the value latched by said latching means (48); Read enable signal generation means (50) for receiving a value obtained by said value extracting means (49) to generate a read enable control signal; A chase means (51) for receiving a read enable control signal from the read enable signal generating means (50) and generating a stuff enable and chase enable signal; The output of the chase means 51 is input, and the second buffer 22 receives the result of mapping the data in order according to the value of the address bus. It is composed of an output means 52 for making and outputting.

The operation of the byte-based data processing apparatus of the optical transmission system according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First, the data loss prevention unit 10 converts an incoming 45 MHz signal and clock into a 5 MHz data and clock. Here, 45 MHz of data is hit by a 45 MHz clock and processed in a buffer. Firstly, a lot of heat is generated, and secondly, the data is lost due to a fast clock, and thirdly, a lot of power is consumed. Therefore, the bit-wise processing implies such various risks, so that the clock converter 11 changes the data in the 5-MHz byte of the 45-MHz signal for the byte-based data processing.

The data thus converted is unconditionally put into the first buffer 13 at a clock of 5 MHz. Since all of the DS3 / E3 signals entering the first buffer 13 are data (not reserved bits or stuff bits), if any byte is lost, the data is broken. The first buffer 13 determines the number of readings in accordance with the control signal input from the outside. The external control signal referred to here is a signal produced by the first buffer 13 itself. The first buffer 13 checks the level of the buffer every 8 times at 5 MHz. When the buffer level is 32 or more, the first buffer 13 generates a signal to read one more bit when reading from the buffer. The combination of reading this signal and the read enable signal can be 8 bits, 1 bit, and 0 bits in one 6MHz clock.

The first control generator 12 compares the read address with the write address to find the level of the buffer, and generates a control signal in a direction narrowing when the difference between the write address and the read address increases. If there is a large difference in the level of the buffer found, there is a possibility of data loss. Therefore, even when the read enable signal is low, data is read one bit so that the difference in the buffer level is maintained at 32.

The following explains why only one bit should be read. In this case, the buffer used may store data of 64 bits, that is, 64 bits. On the other hand, if you write to the buffer with a 5MHz clock, the write address is increased by 8, and if you read with a 6MHz clock, it is decreased by 8. However, repeating reads and writes will cause more data to be released from the buffer during the same time (the 6MHz clock is faster), resulting in errors being read before the data is written to the buffer. The conclusion is that if you want to convert the incoming data to 6MHz without loss, you have to read the data while the 6MHz is at rest. The problem is how to adjust the reading speed, and the calculations conclude that when a 45 MHz signal comes in 64 bits, the 51 MHz signal must read at about 10.163 bit intervals in order to read without losing 64 bits. If we think of this as the case of 5MHz and 6MHz, 6MHz uses 10 counters (31) to generate 10 lead enable signals during 8 writes at 5MHz, one of which is unconditionally low and the other clock is at the buffer level. Depending on the 5-bit or 6-bit read. This keeps the number of data going out at 6MHz nearly constant during the interval at which the 5MHz signal comes in.

In addition, the control signal used to read the data from the buffer, the 6MHz clock and the data is sent to the second buffer 22. Since the purpose of the data loss prevention unit 10 is to convert the data matched to 5MHz to 6MHz, some of the data of 6MHz there is also a byte is not all data. Of course, only a few bits of a byte are data. In order to inform the stuffing management unit 20, the control signals used when the data loss prevention unit 10 reads the data should also be sent to the second buffer 22 of the stuffing management unit 20 together with the data.

Meanwhile, the stuffing manager 20 inserts data into the second buffer 20 with the clock, data, and control signals received from the first buffer 13. In order to put the on-data like the control signal into the buffer like this, a 90 counter 41 is required. In order to know the read or write address of the buffer, a block for counting an address is required. In the normal case, the data is input in bytes, so the count value is increased by eight. However, the signals coming in together with the control signal indicate the fact that all eight bits in a byte are not data, so a counter is needed to indicate the address increment at this time. The first buffer 13 may store 64 bits of data, whereas the second buffer 22 may store 128 bits of data.

It also creates enable and control signals for the AU3 / TU3 frame structure. Create a lead enable signal to match the AU / TU frame structure. There are 5 control signals, Rbit, Sbit, Cbit, POH, and read enable. Among them, 8-bit data is sent out of the buffer at 6MHz one clock unconditionally in the position of the lead enable signal, and 1 bit of data is sometimes out at the 6MHz one clock depending on the level of the buffer in the Sbit position, and sometimes it is not. The data comes out.

The control signal is generated by comparing the read address with the write address, and decide whether to fill the data in the Sbit of the AU / TU frame according to the difference. When reading data with a clock of 6MHz, data is sent in accordance with the control signal described above. If the read enable signal is high, the MSB (Most Significant Bit, most significant bit) is added to the previous read address unconditionally by adding 8 to the previous read address. ). In the remaining positions, there is no change in the read address, and in the Sbit position, when a stuff signal occurs, the LSB (Least Significant Bit) is filled with one bit, the read address is increased by one, and if the stuff is zero, it is maintained.

The chase here reads more or less data than the 8-bit (7-bit) format up to a certain range when the level of the buffer is too high or low, allowing the buffer to quickly approach the center (64 when using 128-bit buffers). If within a certain range (eg 54 to 74), the Chase function does not work and only adjusts the buffer level with Stuff.

The 6MHz clock also reads the data at the address generated by the control signal in the buffer. Accordingly, the output of the stuffing manager 20 has a frame of AU / TU. These signals retime the 6MHz clock.

As described above, the present invention can reduce the heat generated during the processing by the unit of bit by processing the data in the unit of byte, prevent data slip and process the data at high speed.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the byte-based data processing apparatus of the optical transmission system according to the present invention can reduce a lot of heat generated when the 51MHz processing by controlling the buffer and the processing speed of 6MHz, the byte unit, when processing at 51MHz The slip of data that can occur can be prevented, and the data can be processed at high speed by processing the bit unit by the byte unit.

Claims (5)

In the byte unit data processing apparatus of the optical transmission system, A data loss prevention unit converting the input bit unit data and the clock unit into byte units and increasing / decreasing the speed of data in a state where data loss is prevented using a buffer; And a stuffing management unit configured to output data and a clock according to a desired format by performing stuffing management while storing data having an increased speed in the buffer in the data loss prevention unit. The method of claim 1, wherein the data loss prevention unit, A clock converting unit converting the input bit unit clock and data in byte unit; A first control generation unit comparing the write address and the read address of the first buffer to determine the level of the buffer and maintaining a constant interval between the write address and the read address; And a first buffer configured to receive data and a clock of the clock converter in response to a control signal of the first control generator, and to output data and a clock at an increased speed. The method of claim 2, wherein the first control generator, A counter that receives a clock and counts a necessary interval so that data can be read without data loss; Enable generation means for generating an enable signal with the counter; Latch means for reading a write address and a read address from the first buffer and latching the write address and the read address in a positive go and a negative go of a clock according to a latch signal output from the enable generation means; Value extracting means for obtaining a value of a write read address and a write read address buffer from the value latched by the latch means; Stuffing signal generating means for receiving a value obtained by the value extracting means and generating and outputting a stuffing enable signal to the counter; Compensation means for receiving the output of the stuffing signal generating means and the output of the enable generating means and compensating the phases of the control signal and the data output; Calculating means for receiving a read enable signal of the enable generating means and calculating a read address and the number of bits to be included in one byte according to a control signal; An optical transmission system comprising an address determination means for receiving a result output from the calculation means and determining an address for each of 8 bits and outputting a signal for mapping the data of the bit unit stored in the first buffer in order of the byte unit Byte data processing unit. According to claim 1, The stuffing management unit, A second control generator configured to generate a control signal by comparing the write address and the read address of the second buffer, and to perform stuffing to output data and a clock according to a desired format; And a second buffer configured to receive a data, a clock, and a control signal from the data loss prevention unit, and output a data and a clock in a desired format under the control of the second control generator. . The method of claim 4, wherein the second control generating unit, A count for receiving a clock and outputting a count value at a predetermined interval; Enable generation means for generating an enable signal in accordance with the count value output from the count; Write calculation means for receiving an output of the compensation means in the first control generation part and calculating a write address and the number of bytes to be included in one byte according to a control signal; Write address determination means for determining an address of each of the eight bits with the signal received from the write calculation means; Mapping determination means for outputting a signal to map values of the second buffer in order according to the output of the write address determination means; Read calculation means for receiving an output of the enable generation means and calculating a read address and the number of bytes to be included in one byte according to a control signal; Read address determination means for determining the address of each of the 8 bits with the signal received from the read calculation means; Latch means for latching a write-read address outputted from the write and read calculation means when the clock is positively gotten; Value extracting means for obtaining a write-read address from the value latched by the latching means; Read enable signal generation means for receiving a value obtained by the value extracting means and generating a read enable control signal; A chase means for receiving a lead enable control signal from the lead enable signal generation means and generating a stuff enable and chase enable signal; The output means for receiving the output of the chase means and the result of mapping the data in order in accordance with the value of the address bus in the second buffer in order to fill the appropriate value in the overhead seat to create and output the data of the desired format A byte unit data processing apparatus of an optical transmission system, characterized in that configured.