KR100300216B1 - Method and apparatus for transmitting data isochronously at a rate less than the isochronous data rate - Google Patents

Abstract

The first station is connectable to the second station to transmit a predetermined fixed amount of data to the second station for a predetermined period of time to achieve a predetermined fixed data rate. The predetermined time period is made up of a plurality of component time periods. The actual amount of data smaller than a predetermined fixed amount of data transfers actual data during a portion of the component time period from the first station to the second station in a predetermined time period and transmits " null " data for the remainder of the component time period And transmitted. That is, during a predetermined period, the actual data is transmitted with a real efficiency smaller than a predetermined fixed data transmission rate. The blank data may be interspersed with the actual data and the determination of how to scatter the blank data into the actual data may be in accordance with an interpolation algorithm such as the Brezgen's algorithm.

Description

TECHNICAL FIELD [0001] The present invention relates to a method and apparatus for isochronously transmitting data at a rate lower than an isochronous data rate,

Recommendation H.221 of the International Telegraph and Telephone Advisory Committee (CCITT) provides recommendations on the format of line transmission of non-telephone signals. In particular, H.221 recommends a standard frame structure for one or more "B-channel" transmissions for audiovisual services on the entire transmission channel. The B channel or " Bearer Channel " is 64 kilobits per second which carries consumer information such as voice calls, circuit switched data, or packet switched data. The B channel is constant and therefore has a predictable bandwidth.

The H.221 Recommendation divides the entire transport channel into frames, each frame containing 80 octets of octet. The bits at a particular bit position in the octet are collectively considered to be sub-channels of 8 kilobits per second. The lower transmission rates of the subchannels are suitable for image, data and telemetry purposes. The 8th subchannel called the service channel (ie, the octet bits at bit position 8; H.221 numbers octet bits 1 through 8) allow the receiver to synchronize with a 64 kilobits / sec serial stream (&Quot; FAS ") of 8 bits to allow the receiver to determine the capacity and structure of the information transmitted on the channel, and an 8 bit bit rate allocation signal (" BAS "). Recommendation H.221 is incorporated by reference to provide additional background information regarding the present invention as disclosed herein.

The communication information may be transmitted in the H.221 frame structure format via a local area network (" LAN ") or a wide area network (" WAN "). Figure 1 illustrates a system in which computing node 42a is connected to another computing node (e.g., node 42b) that is similar via WAN for audio, video, and data exchange. Computing node 42a is connected to isochronous hub 40 by isochronous Ethernet serial physical layer link 47. Optionally, compute node 42 may be connected to a private branch exchange (" PBX "). The hub / PBX 40 is connected to the WAN, and the backbone connection provides a connection from the hub / PBX 40 to the other hub / PBXs.

The present inventors have recognized the desirability of isochronous transmission of information between subsystems in the computing node 42. Therefore, fixed waiting time and bandwidth, which are characteristics of isochronous communication, can be utilized.

The present invention relates to a method and apparatus for isochronously transmitting data, and more particularly, to a method and apparatus for isochronously transmitting data at an actual efficiency lower than an actual isochronous data rate.

Figure 1 shows in block form a system in which one computing node is isochronously connected to an isochronous hub and / or PBX, to another computing node via that hub, and to a WAN.

2 illustrates in block form one embodiment of a computing node that is isochronously transmitting signals between subsystems of a node using the method and apparatus of the present invention.

3 shows an example of the intra-node transport channel format.

4 is a block diagram of the data interface of the computing node of FIG.

5 schematically illustrates an outbound B-channel interface circuit of the computing node of FIG. 2;

Figure 6 schematically illustrates the inbound B-channel interface circuit of the computing node of Figure 2;

FIG. 7 schematically shows the CPU interface circuit of the computing node of FIG. 2. FIG.

Figure 8 is a graphical representation of the timing of the control signals used to synchronize data communication between the components of the computing node of Figure 2;

The first station is connectable to the second station to transmit a predetermined fixed amount of data to the second station for a predetermined time period to achieve a predetermined fixed data transmission rate. The predetermined time period is made up of a plurality of component time periods. The actual amount of data, which is less than the predetermined fixed amount of data, transfers actual data during a portion of the component time period within a predetermined time period and " null " data from the first station to the second station As shown in FIG. Thus, over a predetermined period of time, the actual data is transmitted at a real efficiency lower than a predetermined fixed data transmission rate. The blank data may be transmitted interspersed with the actual data, and the decision on how to intersperse the null data with the actual data may be in accordance with an interpolation algorithm such as the algorithm of Bresenham.

The features and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings which illustrate an exemplary embodiment in which the principles of the invention are employed.

2 shows an embodiment of a computing node 42 'in block form. The user of the node 42 may be, for example, one of the conference phones. Five subsystems (or components) within computing node 42 handle interactive communication. The five subsystems

1) the translator 45,

2) Data interface unit 46:

3) Audio interface unit 47:

4) an image interface unit 49, and

5) An application software section 44 which executes in a window environment on the CPU,

to be.

The translators 45 described below provide an interface from the isochronous physical layer 45 to other subsystems in the node. The data interface unit 46 transmits data (for example, data corresponding to mouse movement or data from a file) to the application software unit 44 and transmits data (for example, For example, data corresponding to mouse movement or data from a file). The audio interface unit 47 transmits audio data (for example, audio data for driving a speaker or audio data received from a microphone) to the application software unit 44, Provides an interface to receive data. The image interface section 48 provides an interface for transferring image data (for example, from the camera and to the display) to and from the application software section 44.

An intra-node transport channel for inter-subsystem communication of node 42 'is divided into time division multiplexing (" TDM ") frames for information transmission between elements of node 42. FIG. 3 shows six TDM frames 12a-12f, which illustrate examples of such intra-node transport channel format 10. Each TDM frame is divided into bytes (i.e., " B channels "). Typically, each TDM frame is divided into a large number of B channels (e.g., 96). To simplify the description, the TDM frames of the intra-node transport channel format 10 are shown divided into six B channels each. For example, the TDM frame 12a is shown divided into B channels 14a through 14f.

Using the intra-node transport channel format as shown in FIG. 3, certain information types (e.g., audio) are transmitted into a "logical stream" which is one or more B channels in a predetermined storage location within a TDM frame. For example, referring to FIG. 3, a first logical stream, LOGICAL STREAM 1, is stored in storage locations 2 and 3 (i.e., B channels in TDM frame 12a) within TDM frames 14a through 14f. 14b and 14c and their corresponding TDM frames 12b through 12f). The second logical stream, LOGICAL STREAM 2, is shown occupying logical location 5 within TDM frames 14a-14f. Logical streams occupy integer B channels.

Referring again to Figure 2, the translator 45 performs two functions, link translation and compilation / distribution. It is indicated by the link translation that the translator 45 relays the isochronous Ethernet serial physical link 47 to the physical links 51, 52 and 53 in the same node. The translator 45 receives and decodes the information configured in H. 221 format and distributes the data framed in that TDM to the various " interface " components. Conversely, the translator 45 compiles the information received from the "interface" subsystem 46, 48, 49 and encodes it into the H.221 frame structure.

The data interface unit 46 is shown in block form in FIG. The data interface unit 46 provides an interface between the translator 45 and the ISA bus 49 to which the CPU 44 (not shown in FIG. 4) is connected. The data interface portion 46 includes separate "interface" circuits (inbound B channel interface circuitry 116, outbound B channel interface circuitry 118 and CPU interface circuitry 120), "arbitration" circuitry 122, and RAM (114). All three interface circuits operate synchronously to the periodic clock signal (for simplicity, not showing the clock signal in FIG. 4). The original inbound data stream formatted in the intra-node TDM frame transport format is received from the translator and written into the inbound buffer 114a in the RAM 114. [

From the inward butter 114a, the CPU 44 can read any logical stream required by the application program via the CPU interface unit 120. [ Likewise, the CPU 44 is coupled to the outbound buffer 114b of the RAM 114 via the CPU interface circuitry 120 and to the outbound buffer 114b of the RAM 114 for any event that needs to be transferred to the isochronous physical layer 47 for ultimate transmission over the WAN. One or more logical streams can be written.

Intermediate circuit 122 mediates access to RAM 114 between inbound B channel interlace circuit 116, outbound B channel interface circuit 118, and CPU interface circuit 120, as described below.

Each of the interface circuits controls the storage location in the RAM 114, which it accesses independently of the other interface circuits. In particular, in each of the inbound and outbound B channel interface circuits 118 and 116, there are provided inbound buffer address registers, a " starting " address register, an " ending " And a register. The start and end address register pairs define the inbound 114a and outbound 114b buffer boundaries in the RAM 114. The inbound 114a and outbound 114b buffers need not be defined to be the same size, but each must be large enough to hold at least one TDM frame. The CPU 44 initializes the start and end address registers, for example, to start an application program. In a particular embodiment, the address register is mapped to the I / O space of the CPU 44 and initialized by the CPU 44 over the ISA bus by executing I / O instructions. Typically, the start and end address registers (and thus the size of the inbound 114a and outbound 114b buffers) are not changed by the application after being initialized.

On the other hand, the current address register is dynamic and defines the current active storage location in the RAM 114. [ For example, whenever the B channel of the inbound data stream is written to the inbound buffer 114a of the RAM 114, the value of the inbound current address register is updated to the next available inbound buffer 114a storage location. Likewise, each time the B channel of the outbound data stream is read from the outbound buffer 114b of the RAM 114, the value of the outbound current address register is updated to the next outbound buffer 114b storage location to be read. It goes without saying that a single address range of the RAM 114 may be used for both the inward 114a and the outward 114b buffers when the operation of the inbound interface circuit and the outbound interface circuit is appropriately adjusted.

A set of address registers are provided in the address generator of the CPU interface circuit 120. Since the CPU interface circuit reads from the inward buffer 114a of the RAM 114 and writes to the outbound buffer 114b of the RAM 114, the values of the CPU interface circuit 120 start and end address registers are set to the CPU 44 ) Is accessed every time before accessing the RAM 114. Similarly, the value of the current address register of the CPU interface circuit 120 is reset.

The arbitration circuit 122 will be described in detail. During one period of the clock signal, only one complete read or ride operation may be performed in RAM 114. [ Thus, all accesses to the RAM 114 are made through the arbitration circuit 122. For example, to write to RAM 114, inbound B channel interface circuit 116 provides data to be written to arbitration circuit 122 via a " data " bus. The address at which the data is to be written is provided from the current address register to the arbitration circuit 122 via the " address " bus. Finally, a " write request " line to arbitration circuit 122 is required. The arbitration circuit 122 provides data and addresses to the RAM 114 and requests a " write strobe " to the RAM to cause the data to be written to the requested address. The arbitration circuit 122 acknowledges the successful write to the inbound B channel interface circuit 116 via the " ack " line. The current address register is then modified to have the value of the next available memory location to be written to the inbound buffer 114a in the RAM 114. [

Similarly, to read data from the RAM 114, the outbound B-channel interface circuit 118 provides the address from which the data is to be read from the current address register to the arbitration circuit 122 via the " address & Requests the arbitration circuit 122 to " request a read " The arbitration circuit 122 provides an address to the RAM 114 and requests a " lead strobe " to the RAM to cause the data to be read from the requested address. Quot; ack " line to the outbound B channel interface 118 and indicates that the data being read is on the " data " bus.

The CPU interface circuit 120 using the start address, end address and current address register writes data to the outbound buffer 114b of the RAM 114 and from the inbound buffer 114a of the RAM 114 in the same manner Data is accessed.

When more than one RAM 114 access is attempted at the same time, the arbitration circuit 122 provides the interface circuit with the highest priority access to the RAM 114. Intermediate circuit 122 rotates the priority of access every clock period (e.g., from inbound B channel interface circuit 116 to outbound B channel interface circuit 118, to ISA bus 49, Channel B interface circuit 116. It is therefore apparent that, independent of the possible access latency, simultaneous memory access attempts to the interface circuit occur.

5 schematically illustrates the outbound B-channel interface circuit 118. In Fig. A number of control signals are used to synchronize the operation of the outbound B channel interface circuit 118. Hereinafter, the timing of these control signals will be described with reference to Fig. 8 which shows the timing of control signals in a graph. The outward address generator 130 has a group of address registers and controls access to the outbound buffers in the RAM 114 by the outbound B channel interface circuit 118. The outward address generator 130 receives the transmit enable signal Trn _- Enable from the translator 45. In response to the Trn _- Enable occurrence, the output address generator 130 provides the address of the storage location of the outbound buffer 114b (via the arbitration circuit 122) in the RAM 114 that initiates the TDM frame read. The bytes of the TDM frame that are read in parallel from the RAM 114 are converted to a serial data stream by the parallel / The bits of the serial data stream are transmitted to the translator 45 in response to Trn _- Enable and in synchronization with the master clock (see FIG. 8). By checking the number of Trn _- Enable pulses received for each received Trn _- Synch pulse, the outward synchronization check logic 135 checks whether the correct number of bytes are transmitted for each outgoing TDM frame. Otherwise, the outward synchronization check logic 135 adjusts the current address pointer in an attempt to resynchronize the outbound B channel transmission (the timing of the Trn _- Enable and Trn _- Sync signals depends on the Rec _- Enable and Rec _- Sync signals Of course not necessarily related to the timing of < RTI ID = 0.0 >

The TDM reference counter circuit 134 receives, from the translator 45, a transfer synchronization signal Trn _- Synch indicating the start of TDM frame transmission by the translator 45. The TDM reference counter circuit 134 provides a time reference to the network front end circuit 100. In particular, the TDM reference counter 134 increments the value of the TDM reference counter register each time it receives a Trn _- Synch from the translator 45. In addition to being used to time delay the TDM in the inbound and outbound data streams, the TDM reference counter circuit 134 may also be used to generate a TDM synchronous interrupt to the CPU 44. [ Typically, a TDM reference counter is used to schedule CPU device driver interrupt activation for communication between the CPU and the arbitration circuit 122 via the CPU interface circuit 120. To allow the CPU device driver to schedule the next serving point, the device driver determines the amount of time (delta time) to the next serving point, adds this time to the current value of the TDM reference counter register, and adds the sum to the TDM interrupt register Lt; / RTI > When the value of the TDM reference counter register reaches the value of the TDM interrupt register, the TDM reference counter circuit 134 generates an interrupt signal to the CPU.

Finally, the TDM reference counter circuit 134 provides the master enable function, as controlled by the master enable signal provided by the CPU 44, as an I / O map signal over the ISA bus. When enabled by the master enable signal and upon the occurrence of the next Trn _- Synch pulse, the TDM reference counter 134 provides an inbound enable signal to the inbound B channel interface circuit 116 and an outbound B channel interface circuit 118 ) To enable the operation of these circuits.

6 schematically illustrates an inbound B-channel interface circuit 116. The in- The serial / parallel converter 142 receives the TDM frame serially from the translator 45 and receives the receive enable signal Rec _- Enable synchronous with the master clock from the translator 45 (see FIG. 8). The serial-to-parallel converter 142 converts the serial data flow into a parallel data word.

The inbound address generator 140 includes a group of address registers for controlling access to the inbound buffer 114a in the RAM 114 by the inbound B channel interface circuit 116. [ The inward address generator also receives a receive enable signal from the translator 45. [ The receive enable signal signals the inbound address generator 140 to provide the address of the storage location of the inbound buffer 114a in the RAM 114 that writes the parallel data word (via arbitration circuit 1222). By checking the number of received Rcv _- Enable pulses for each received Rec _- Synch pulse, the in _- sync check logic 143 checks whether the correct number of bytes have been received for each inbound TDM frame. Otherwise, the inbound synchronization check logic 143 adjusts the current address pointer in an attempt to resynchronize the inbound B channel reception.

FIG. 7 schematically shows a CPU interface circuit 120. FIG. The outbound FIFO 150 and the inbound FIFO 152 are each two bytes deep. Address generator 154 includes a group of address registers for controlling access to inbound 114a and outbound 114b buffers in RAM 114. [ The " offset to next TOM frame " is set to be equal to the number of B channels from the end of the logical stream portion in one TDM frame to the beginning of the logical stream portion in the next TDM frame.

After setting the start and end address register values at the address generator 154, the CPU 44 maintains the initial (first) B channel of the logical stream to be written to write a particular logical stream from the RAM 114 The current address register is set to the address of the storage location in the outbound buffer 114b, and the CPU 44 sets the "number of B channels in logical stream" register to the size of the logical stream (the number of B channels).

The number of B channels transmitted from the CPU 44 to the outbound buffer 114b through the outbound FIFO 150 of the CPU interface circuit 120 is equal to the total number in the "total bytes to consider" register. The CPU 44 initializes this register and maintains the logical stream size multiplied by the number of TDM frames to be processed. For example, to write a logical stream that occupies 6 B channels per TDM frame over a 160 TDM frame, the CPU 44 initializes the " total bytes to consider " The CPU writes the data to the outbound FIFO 150 and the address generator 154 generates the appropriate control signal to write the B channel to the RAM 114 via the arbitration circuit 122. Flow control is provided through the ISA Bus Ready line. Since no polling is required, string I / O or other high-speed transmission techniques can be used.

For the read operation, the CPU 44 similarly sets addresses, offsets, the number of B channels, and bytes to be considered by the CPU interface circuit 120. The CPU interface circuit 120 starts a TDM frame read in response to the read operation indicated by the CPU 44. [ When the read operation is instructed, if the first B channel is not available from the TDM frame, the flow control is provided via the ISA Bus Ready line. For writing to RAM 114, string I / O or other high speed transmission techniques may be used.

Partial logic flow

As mentioned above, the H.221 recommendation defines how the entire transport channel may be divided into frames, each frame containing 80 8-bit octets. The subchannel has a 1/8 capacity of the B channel, and across the network, the partial B channel capacity is passed on to the subchannels of the H.221-format frame. However, as described in the Background section, it is desirable to isochronously connect the components of the node. That is, over these isochronous connections, the fractional capacity of the actual data bytes is passed to the intra-node transport format as the entire byte stream, with the "blank bytes" inserted to "fill" the capacity of the channel. For example, a 1/8 capacity channel has 7 blank bytes per physical data byte. To indicate which byte is blank, each byte associates it with the 9th "blank flag" bit. An inter-node parallel link (an inbound B channel interface 116 to an arbitration circuit 122), an outbound B channel interface 118 to an arbitration circuit 122, a CPU interface circuit to arbitration circuit 122, 0.0 > RAM < / RTI > 114) is 9 bits wide.

Referring to Figures 6 and 8, the blank bytes are transferred from the translator 45 to the inbound B channel interface circuit 116 with the help of the Rec _- Null signal. In particular, when a Rec _- Null signal is generated as the S / P converter 142 receives a data byte (as indicated by Rec _- Enable being generated), the S / Quot; blank byte " flag of the data byte as it is written into the inbound buffer 114a in the < / RTI > In this case, the 8-bit data portion of the received data byte is " do not care ". Otherwise, if the Rec _- Null signal is not generated as the S / P converter 142 receives the data byte (as indicated by the Rec _- Enable being generated), the S / Quot; blank byte " flag of the data byte as it is written into the inbound buffer 114a in the memory 114. [ In this case, the 8-bit data portion of the received data byte is the actual data byte.

5 and 8, the blank bytes are transferred from the outbound B-channel interface circuit 118 to the translator 45 with the help of the Rec _- Null signal.

In particular, when the ninth " empty byte " flag of the byte to be transmitted from the outbound buffer 114b is set, the parallel-to-serial converter 132 generates a Trn _- Null signal . The data bytes transmitted serially to the translator 45 are " Don Care ". If Relatively rather, that the ninth "blank bytes" flag is not set, the parallel / serial converter is a parallel / serial converter 132, the data bytes _- Trn as to transmit the (Trn that is generated as a vibration removal table indicated by the Enable) _- Do not generate a null. In this case, the data bytes sent serially to the translator are the actual data bytes.

Referring back to FIG. 7, the inward blank processing circuit 156 in the CPU interface circuit 120 discards the inward blank bytes that are read from the inbound buffer 114a, and the blank bytes are never sent to the CPU 44. [ Likewise, the CPU interface circuit 120 inserts a blank byte into the outbound FIFO 150 so that a blank byte (as indicated by the ninth " blank " flag bit set) is sent to the outbound buffer 114b and written. That is, while the inbound B-channel data rate is a function of the B-channel source, the CPU 44 directly controls the actual data rate of outgoing and effective data.

For example, when the logical stream of the partial B channel is written from the CPU 44 to the RAM 114 via the CPU interface circuit 120 and the arbitration circuit 122, the CPU 44 writes the complete B channel , And some of the B channel bytes are designated as " blank ". For example, the CPU may designate a particular byte as blank by outputting bytes from the CPU 44 at a specific I / O storage location different from the storage location where the non-blank bytes are output. This causes the blank flag bit associated with that byte to be set. The CPU interface circuit also sets the ninth bit blank flag to be sent to the RAM 114 and the written byte is set to the blank (" not care ") data value . Optionally, when the actual byte is transferred to the RAM 114 and then written, the CPU interface circuit 120 erases the ninth bit blank flag and the bytes written to the RAM 144 are actually (i. E., Non-empty) . When the logical stream of the partial B channel is transferred from the CPU 44 to the RAM 144 via the CPU interface circuit 120 and the arbitration circuit 122, the value of the " total bytes to be considered " B channel, and the value of the " total bytes valid " register is the total number of non-blank bytes. As described above, the value of the " total bytes to be considered " register is written by the CPU 44 before the CPU transfer operation. In particular, the written value can be calculated by multiplying the number of B channels in the logical stream by the number of TDM frames to transmit. The value of the " total byte valid " register is set by the CPU interface circuit 120 during the CPU transfer operation.

During a read operation, the CPU also writes the value to the " Total Bytes " register, which is the total capacity of the B channel in the logical stream to be transmitted. However, the " inward blank processing " circuit of the CPU interface circuit 120 discards the blank bytes before delivering them to the inbound FIFO. After transmission, the value of the " total bytes valid " register indicates the total number of non-blank bytes transmitted. The CPU 44 then discards the final " total bytes to consider " minus " total bytes valid " that this led to from the CPU interface circuit 120.

If the CPU 44 continues to read after all valid bytes have been transferred, and even after the total number of bytes to be considered has been used, the CPU interface will transfer the undefined data to the CPU, but the ISA bus will not hang. Similarly, if the CPU 44 continues writing after the total number of bytes to be considered is used, the extra data is discarded, but the ISA bus does not hang.

To set the fractional outward rate, it first needs to be determined what the total capacity of the logical stream in the H.221 format frame (this simplifies the process of adding capacity to use the common denominator). The following three examples illustrate an algorithm for determining the total capacity of three different logical streams in an H.221 format frame:

1. Two B-channel arcs with FAS / BAS on both channels with 16 kB / s audio. Total image capacity is

((2 * (4/40)) + ((5 + 7) * (5/40))) = 68/40 or 1.7B channels.

2. Six B-channel arcs with FAS / BAS on all channels and 56 kbit / s audio. The service channel in the initial B channel is used for the image. Total image capacity is

((6 * (4/40)) + (5 * 7 * (5/40))) = 199/40 or 4.975 B channel

3. Low speed data (LSD) of HO call and service channel with 56 kB / s audio. The total data channel capacity is 4/40 or 0.1 B channels.

Once the extrinsic rate is known, it can be determined which byte is designated as " blank ". An algorithm is now provided that may be used to determine which byte of the logical stream is designated as blank. This algorithm uses a set of "C" code register variables. Determining which bytes should be blank is basically an interpolation problem. For example, in computer graphics, it is used to determine which pixel on the display will emit light to display a smooth line. The Bregenz algorithm used to solve this smoothed line problem is also used by the CPU to determine which of the transmitted bytes is designated as blank. In order to minimize the buffering and latency required in the translator 45, it is important to " smooth " the insertion of blank bytes into the logical stream. The Bregenz algorithm is particularly useful in this application since there is no rounding error. Since the translator 45 compilation must be an exact multiple of the B channel, rounding errors can not be tolerated.

In the three examples, the speed is of course first expressed as a ratio, i.e., 68/40, 199/40, and 4/40. To execute the algorithm, the speed ratio is designated as " X / Y " and the outbound blank register is set up as follows.

1. Determine the total number of B channels required. B ChanNum = X / Y. IF ((B ChanNum * Y) < X) B ChanNum ⁺⁺ .

2. Make Y> = X. Y = B ChanNam * Y.

3. Brethrenham setup: a) Error = 2 * X, b) Minor = 2 * X-2 * Y, C) Major = 2 * X. Major is always positive and minors are 0 or negative.

When X / Y is an integer, the operation returns to the case of all B channels because "minor" is 0 and the data value is always written.

For each outbound buffer write, do the following:

if error> 0

{

Output the data value.

Error = Error + Minor.

}

else

{

Print the value and specify it as a blank.

Error = Error + Major

}

It is needless to say that various modifications to the embodiments of the present invention described above may be adopted in the practice of the present invention. The following claims define the scope of the invention and cover methods and apparatus within the scope of these claims and their equivalents.

Claims (10)

Wherein the first station is connectable to the second station to transmit a predetermined fixed amount of data to the second station for a predetermined period of time to achieve a predetermined fixed data rate and the predetermined time period consists of a plurality of component time periods, 1. A method for transmitting an amount of actual data less than a predetermined fixed amount of data from a first station to a second station in a time period, a. Transmitting actual data during a portion of the component time period, and b. Null " data during the remainder of the component time period, such that during a predetermined period of time, the actual data is transmitted with a real efficiency less than a predetermined fixed data rate. 2. The method of claim 1, further comprising determining first the total number of time periods for which blank data should be transmitted so that all actual data is transmitted and a predetermined fixed data rate is achieved. 3. The method of claim 2, wherein component time periods in which blank data is transmitted are scattered in component time periods in which actual data is transmitted. 4. The method of claim 3, wherein the determination of the method of interspersing component time periods of empty data transmission in time periods of actual data transmission is in accordance with an interpolation algorithm. 5. The method according to claim 4, wherein the interpolation algorithm is an algorithm of Brezgen. Wherein the first station is connectable to the second station to transmit a predetermined fixed amount of data to the second station for a predetermined time period to achieve a predetermined fixed data rate, the predetermined time period being comprised of a plurality of component time periods, An apparatus for transmitting an actual data amount smaller than a predetermined fixed data amount from a first station to a second station in a predetermined time period, a. Means for transmitting actual data during a portion of a component time period, and b. Means for transmitting " null " data during the remainder of the component time period, Wherein, during a predetermined time period, the actual data is transmitted at a real efficiency smaller than a predetermined fixed data transmission rate. 7. The apparatus of claim 6, further comprising means for determining first the total number of time periods in which the blank data should be transmitted so that all actual data is transmitted and a predetermined fixed data rate is achieved. 8. The apparatus of claim 7, wherein component time periods in which blank data is transmitted are scattered in component time periods in which actual data is transmitted. 9. The apparatus of claim 8, wherein the determination of the method of interspersing component time periods of empty data transmission in time periods of actual data transmission is in accordance with an interpolation algorithm. 10. The apparatus of claim 9, wherein the interpolation algorithm is an algorithm of Brezgen.