KR100297992B1 - Moving picture decoding method and apparatus, and moving picture reproducing apparatus - Google Patents

Abstract

An object of the present invention is to reduce the circuit scale and simplify the control operation.

According to the present invention, the display parameter synchronization holding circuit 20 outputs the register group 21 to which the display parameter DP separated in the variable length decoding circuit is supplied to the data input terminal, and the display parameter DP and the register group 21. Selector 24 for selecting and outputting either one of the registers, the register group 22 to which the output of the selector 24 is supplied to the data input terminal, and the output of the register group 22 to the data input terminal and responding to VSYNC. A register group 23 holding input data and a control circuit 25 are provided, and the control circuit 25 is provided to the selector 24 when the image coding type (PCT) is an I or P image. The output of the register group 21 is selected, and the sustain signals SH2 and SH1 to the register groups 22 and 21 are activated in turn, and if the PCT indicates that it is a B image, the DP is selected for the selector 24. Select and activate SH2 .

Description

Moving picture decoding method and apparatus, and moving picture reproducing apparatus

The present invention relates to a video decoding method and apparatus and a video playback apparatus.

In the conventional moving picture decoding apparatus, decoding processing is performed in the order of the supplied coded data and stored in the frame memory, and the decoded image data is read out from the frame memory in the order of the original image. The read data is processed based on the display parameters and analogized to generate a video signal.

These display parameters include the following.

Three sets of frame center offsets in the picture display extension (horizontal position and vertical position)

During picture spatial scalable extension,

Spacial temporal weight code table lndex

Lower layer vertical offset

Lower layer horizontal offset

Lower layer temporal reference

Lower layer deinterlaced field select

Repeat first field

Top field first

In FIG. 5, I, B, and P represent I image, B image, and P image, respectively, and the numerical value attached to these I, B, or P has shown the decoding process procedure.

The display parameters are separated in the variable length decoding circuit, used in the image display circuit, and their contents are released after use. For example, in Fig. 5, when the decoding processing of I1, B2, B3 and B4 is performed in sequence, the display parameters are separated in the variable length decoding circuit for each image, and are maintained in the register groups 1 to 4, respectively. These contents are released each time the data processing in the image display circuit is finished in units of images, and the contents are rewritable. The hatching section in Fig. 5 shows a period in which it is released. Subsequently, when the decoding processes of B5, B6, and B7 are performed in sequence, the display parameters are separated in the variable length decoding circuit for each image, and are maintained in the released register groups 2, 3, 1, respectively.

In the conventional moving picture decoding apparatus, four sets of registers were required to hold the display parameters, which caused a increase in the circuit scale. In addition, in the maintenance and reading of display parameters, since one set of four register crowds must be appropriately selected, the control is complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a moving picture decoding method and apparatus and a moving picture reproducing apparatus capable of reducing the circuit scale and simplifying the control operation in view of such a problem.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a schematic configuration of a moving picture decoding apparatus according to one embodiment of the present invention.

FIG. 2 is a diagram showing an example of the configuration of a display parameter synchronization maintaining circuit in FIG. 1; FIG.

FIG. 3A is a diagram showing a configuration example of the control circuit in FIG. 2, and FIG. 3B is a time chart showing the operation of the circuit in FIG.

4 is an operation explanatory diagram of the circuit of FIG. 2;

5 is a diagram illustrating a conventional display parameter synchronization maintaining operation.

<Explanation of symbols for main parts of drawing>

11: memory control circuit

12: complete control circuit

13: memory

15 variable length decoding circuit

19: image display circuit

20: display parameter synchronization maintaining circuit

21: rearrangement register group

22: display register group

23: display synchronization register group

24: selector

25 control circuit

251: discrimination circuit

252: delay circuit

253: OR gate

VSYNC: Vertical Sync Signal

SEL: selection control signal

SH1, SH2: hold signal

ST: Sync signal

PCT: Picture Coding Type

DP: display parameter

The method according to claim 1, wherein the display parameter and the image coding type are separated from the coded data, the coded data is decoded, the separated display parameter is stored, and the stored display parameters are read out in the order of the display image. A moving picture decoding apparatus which processes decoded data based on the display parameter,

First, second and third register groups,

When the picture coding type indicates that the picture coding type is a reference picture, the contents of the first register group are held in the second register group, and the separated display parameters are held in the first register group. A control circuit for holding the separated display parameter in the second register group when indicating that the separated picture coding type is a non-reference picture,

In synchronization with the display synchronizing signal, the contents of the second register group are held in the third register group as display parameters in the display image order.

According to the moving picture decoding apparatus, since three sets of register groups may be provided, the circuit scale can be reduced compared with the case of providing four sets as in the prior art. Furthermore, since the holding control for the first register group or the second register group may be performed based on the picture coding type, the control is simplified. In addition, it is sufficient to keep the output of the second register group in the third register group in synchronization with the display synchronization signal, and process the decoded data based on the output of the third register group, and select one set from a plurality of sets of register groups. There is no effect, so that the data read control from the register group is simplified.

The method according to claim 2, wherein the display parameter and the image coding type are separated from the coded data, the coded data is decoded, the separated display parameter is stored, and the stored display parameters are read out in the order of the display image. A moving picture decoding apparatus which processes decoded data based on the display parameter,

A first group of registers supplied with the separated display parameters to a data input terminal and holding input data in response to a first holding signal;

Selection means for selecting and outputting one of the separated display parameters and the output of the first register group in accordance with a selection control signal;

A second register group which is supplied with an output of said selecting means to a data input terminal and holds input data in response to a second holding signal;

A third register group supplied with an output of the second register group to a data input terminal and holding input data in response to a display synchronization signal;

If it is indicated that the picture coding type is a reference picture, the selection means outputs the selection control signal for selecting an output of the first register group, activates the second sustain signal, and outputs the first When the holding signal is activated and output, and the picture coding type indicates that the picture coding type is a non-reference picture, the selection control signal for selecting by the selection means the separated display parameter is output and the second holding signal is output. And a control circuit which outputs as being active.

In the moving picture decoding apparatus according to claim 3, the control circuit according to claim 2 further comprises: a discriminating circuit for determining whether the picture coding type indicates the reference picture or the non-reference picture;

And a control signal generation circuit for generating the selection control signal, the first sustain signal, and the second sustain signal based on a result of the discrimination of the discrimination circuit.

The video decoding apparatus of claim 4, wherein the discrimination circuit outputs a first pulse when the picture coding type indicates that the picture coding type is the reference picture, and the picture coding type indicates the non-reference picture. If it is indicated that the second pulse is output,

The control signal generation circuit outputs the first pulse as the selection control signal, outputs the delayed first pulse as the first sustain signal, and corresponds to the logical sum of the first pulse and the second pulse. A signal is output as the second sustain signal.

In the moving picture decoding apparatus of claim 5, the display synchronization signal is a vertical synchronization signal.

The moving picture reproducing apparatus of claim 6 includes the moving picture decoding device according to claim 1.

The method according to claim 7, wherein the display parameter and the image coding type are separated from the coded data, the coded data is decoded, the separated display parameter is stored, and the stored display parameters are read out in the order of the display image. A moving picture decoding method for processing data decoded based on the display parameter,

Having a first, second and third register group,

If the picture coding type is a reference picture, the contents of the first register group are held in the second register group, and the separated display parameters are held in the first register group,

If the picture coding type indicates that the picture coding type is a non-reference picture, the separated display parameter is held in the second register group,

In synchronization with the display synchronizing signal, the contents of the second register group are held in the third register group as display parameters in the display image order.

EMBODIMENT OF THE INVENTION Hereinafter, one Embodiment of this invention is described based on drawing.

1 shows a schematic configuration of a moving picture decoding apparatus 10.

The video bit stream VBS encoded by the MPEG (2) method is supplied to the memory control circuit 11 of the moving picture decoding apparatus 10. In the moving picture decoding apparatus 10, a video bit stream VBS is temporarily stored at high speed in the encoded data area 131 of the memory 13 by the memory control circuit 11 based on the instructions of the entire control circuit 12. The data in this area 131 is read out at a slower speed than when stored, and is supplied to the variable length decoding circuit 15 as coded image data DAT0 via the memory bus 14. The DAT0 is converted into quantized DCT coefficients by the variable length decoding circuit 15, and then converted into DCT coefficients by the inverse quantization circuit 16, and then converted into image data DAT1 by the inverse DCT circuit 17. do.

The control data included in the DAT0 is separated from the variable length decoding circuit 15, and a part thereof is supplied to the entire control circuit 12, which includes an image coding type (PCT).

If the DAT1 is an I picture (internally coded picture), it simply passes through the motion compensation circuit 18 including the predictive decoding circuit, and decodes the image data DAT2 via the memory bus 14 and the memory control circuit 11. As a result, it is stored in the decoded data storage area 132 of the memory 13. When the DAT1 is a P picture (previous prediction coded picture) or B picture (bidirectional predictive coded picture), the memory control circuit 11 decodes a reference decoded picture from the decoded data storage area 132 of the memory 13. Data is read and supplied to the motion compensation circuit 18 as reference decoded image data DAT3, a predictive image is generated from the DAT3, and DAT1 is added to the decoded image data DAT2 to generate a memory bus. It is stored in the area 132 via the 14 and the memory control circuit 11.

The data in the area 132 is read by the memory control circuit 11 in order of the image before encoding, and is supplied to the image display circuit 19 as display decoded image data DAT4 for display via the memory bus 14, Format conversion or the like is performed based on the display parameters from the display parameter synchronization holding circuit 20, and then analogized to generate a video signal VS.

The display parameter synchronization holding circuit 20 is supplied with a display parameter and an image coding type PCT among control data separated by the variable length decoding circuit 15. In addition, a synchronization signal ST indicating the short circuit for each image is generated by the variable length decoding circuit 15 and supplied to the display parameter synchronization holding circuit 20.

The display parameter synchronization holding circuit 20 holds the display parameters in accordance with the image coding type PCT as described later, and synchronizes the image display circuit 19 in synchronization with the vertical synchronization signal VSYNC from all the control circuits 12. The display parameter corresponding to the image processed in the circuit is supplied to the image display circuit 19.

2 shows an example of the configuration of the display parameter synchronization maintaining circuit 20.

The circuit 20 includes a rearrangement register group 21, a display register group 22, and a display synchronous register group 23 having the same configuration with n registers. Parallel display parameters DP are supplied to the data input terminal of the register group 21. One of the output of the data held in the registers 211 to 21n of the register group 21 and the display parameter DP is selected by the selector 24, and the data input terminal of the registers 221 to 22n of the register group 22 is selected. Are supplied at the same time. The output of the data held in the registers 221 to 22n is simultaneously supplied to the data input terminal of the registers 231 to 23n of the register group 23. The output of the data held in the registers 231 to 23n is simultaneously supplied to the image display circuit 19.

The control circuit 25 generates the selection control signal SEL and the sustain signals SH1 and SH2 based on the picture coding type PCT and the synchronization signal ST, respectively, and select control input terminals and registers of the selector 24, respectively. The clock input terminal CK of the groups 21 and 22 is supplied. The vertical synchronization signal VSYNC is supplied to the clock input terminal CK of the register group 23.

The control circuit 25 determines the type of the picture coding type PCT in synchronization with the synchronization signal ST. When the control circuit 25 determines that the PCT indicates that it is an I picture or a P picture (reference picture), the control circuit 25 selects the output of the register group 21 with respect to the selector 24 to thereby select the registers 211 to 21n. The outputs are simultaneously supplied to the registers 221 to 22n respectively, and then the sustain signal SH2 is activated to hold the output of the register group 21 in the register group 22, and then the output of the register group 21 is held. The sustain signal SH1 is activated to hold the display parameter DP in the registers 211 to 21n of the register group 21. This process is performed at the time points t1, t6, and t12 in FIG. FIG. 4 is an operation explanatory diagram of the circuit of FIG. 2 and corresponds to FIG. 5.

When the control circuit 25 determines that the PCT is a B image (non-reference image), the control circuit 25 selects the display parameter DP with respect to the selector 24 to supply the DP to the registers 221 to 22n. The sustain signal SH2 is then activated to hold the DP in the register group 22. This process is performed at the time points t2, t4, t8, t10, t1 4 and t16 in FIG.

The contents of the register group 23 are updated at time points t3, t5, t7, t9, t11, t13, t15 and t17 in FIG.

Fig. 3A shows a configuration example of the control circuit 25 in Fig. 2, and Fig. 3B is a time chart showing the operation of this circuit. DAT2 in FIG. 3B is a part thereof in FIG. 4.

The discrimination circuit 251 determines whether the PCT indicates the reference image at the timing of rising of the synchronization signal ST, and maintains the selection control signal SEL at a high level for a certain period of time when determining that the PCT indicates the reference image. . While the SEL is at the high level, the output of the register group 21 is selected by the selector 24, while the display parameter DP is selected by the selector 24 while the SEL is at the low level. The SEL passes through the delay circuit 252 to become the holding signal SH1.

The discrimination circuit 251 maintains the signal SB at a high level for a certain period when it is determined that the PCT indicates the non-referenced image at the timing of rising of the synchronization signal ST. SB and SEL are supplied to the OR gate 253, and the sustain signal SH2 is output from the OR gate 253.

The above operation is performed by such a control circuit 25.

According to this embodiment, since three sets of register groups may be provided in the display parameter synchronizing holding circuit 20, the magnitude | size of the display parameter synchronizing holding circuit 20 reduces compared with the case of providing four sets as conventionally. Further, since the selector 24 may be selectively controlled based on the picture coding type PCT and the sustain signal SH1 or SH2 is activated, data retention control in the register group is simplified. In addition, the output of the register group 22 may be held in the register group 23 at the timing of the vertical synchronization signal VSYNC, and the output of the register group 23 may be supplied to the image display circuit 19. Since the data supplied to (19) need not be selected from a plurality of register groups, data read control from the register groups is simplified.

In addition, various modifications are included in this invention besides.

For example, the display parameter DP may be serial data in bit units or word units. In the case of word-level serial data, the display parameters DP are sequentially held in the registers 211 to 21n or 221 to 22n by the address signal from the variable length decoding circuit 15. Serial data in bit units or word units may be transferred from the registers 221 to 22n to the registers 231 to 23n.

As the display synchronization signal, instead of the vertical synchronization signal VSYNC, a new synchronization signal within the blanking period may be generated and used.

Claims (7)

The display parameter and the image coding type are separated from the coded data, the coded data is decoded, the separated display parameter is stored, the stored display parameters are read out in the order of the display image, and based on the read display parameters. In the video decoding apparatus for processing the decoded data, First, second and third register groups, When the picture coding type indicates that the picture coding type is a reference picture, the contents of the first register group are held in the second register group, and the separated display parameters are held in the first register group. A control circuit for holding the separated display parameter in the second register group when indicating that the separated picture coding type is a non-reference picture, And a content of said second register group is held in said third register group as display parameters of said display image sequence in synchronization with a display synchronizing signal. The display parameter and the image coding type are separated from the coded data, the coded data is decoded, the separated display parameter is stored, the stored display parameters are read out in the order of the display image, and based on the read display parameters. In the video decoding apparatus for processing the decoded data, A first group of registers supplied with the separated display parameters to a data input terminal and holding input data in response to a first holding signal; Selection means for selecting and outputting one of the separated display parameters and the output of the first register group in accordance with a selection control signal; A second register group which is supplied with an output of said selecting means to a data input terminal and holds input data in response to a second holding signal; A third register group supplied with an output of the second register group to a data input terminal and holding input data in response to a display synchronization signal; When the picture coding type indicates that the picture coding type is a reference picture, the selection means outputs the selection control signal for selecting the output of the first register group, activates the second sustain signal, and outputs the first control signal. When the holding signal is activated and outputted, indicating that the picture coding type is a non-reference picture, the selecting control signal for selecting by the selection means the separated display parameter is output and the second holding signal is output. A moving picture decoding apparatus comprising: a control circuit which is output as being active. The method of claim 2, wherein the control circuit, A discriminating circuit for discriminating whether the picture coding type indicates the reference picture or the non-reference picture; And a control signal generation circuit for generating the selection control signal, the first sustain signal, and the second sustain signal based on a determination result of the discrimination circuit. The method of claim 3, wherein the discriminating circuit outputs a first pulse when the picture coding type is the reference picture, and outputs a second pulse when the picture coding type is the non-reference picture. Output, The control signal generation circuit outputs the first pulse as the selection control signal, outputs the delayed first pulse as the first sustain signal, and corresponds to a logical sum of the first pulse and the second pulse. And a video signal to be output as the second sustain signal. The video decoding apparatus according to claim 1, wherein the display synchronization signal is a vertical synchronization signal. A moving picture decoding device comprising the moving picture decoding device according to claim 1. The display parameter and the image coding type are separated from the coded data, the coded data is decoded, the separated display parameter is stored, the stored display parameters are read out in the order of the display image, and based on the read display parameters. In the video decoding method for processing the decoded data, Having a first, second and third register group, If the picture coding type is a reference picture, the contents of the first register group are held in the second register group, and the separated display parameters are held in the first register group, If the picture coding type indicates that the picture coding type is a non-reference picture, the separated display parameter is held in the second register group, And a content of the second register group is held in the third register group as a display parameter of the display image sequence in synchronization with a display synchronization signal.