KR100295703B1 - Semiconductor device testing apparatus and semiconductor device testing system having a plurality of semiconductor device testing apparatus - Google Patents

Abstract

Provided is a semiconductor device test system capable of efficiently operating a plurality of semiconductor device test apparatuses. A host computer 2 for managing and controlling a plurality of semiconductor device test apparatuses 1A, 1B, and 1C, and a classifying device 3 are provided, and a device such as a number and a test result assigned to the tested semiconductor device. The storage information storage means 4 which stores the storage information is provided in the host computer 2. In the handler section 11 of each test apparatus, the test apparatus is not classified or classified into only two categories, and is transferred from the test tray to the general-purpose tray, and the storing information of each apparatus is transferred to the storing information storage means. Remember to. After all the tests are completed, the storing information of each device stored in the storing information storage means is sent to the classifying apparatus, and the classifying apparatus is sorted by the classifying apparatus.

Description

A semiconductor device test system having a semiconductor device test device and a plurality of semiconductor device test devices TECHNICAL FIELD

A semiconductor device test apparatus (generally called an IC tester) that applies a predetermined pattern of test signals to a semiconductor device to be tested (generally called a DUT) and measures its electrical characteristics, returns the semiconductor device to a test section. In which the semiconductor device is brought into electrical contact with the test head of the test apparatus, and the tested semiconductor device is taken out of the test section after the test, and the tested semiconductor device is classified into good or defective according to the test result. Are commonly called handlers). In this specification, the test apparatus in which this kind of handler is mounted is called a semiconductor device test apparatus. In addition, below, the IC which is a typical example of a semiconductor device is demonstrated as an example in order to simplify description.

As the IC improves the density and increases the number of terminals, it is difficult to test an IC with a large number of terminals with an IC tester equipped with a naturally-falling handler that slides the IC by its own weight on an inclined transport path. have. For this reason, in recent years, the IC test apparatus is equipped with a handler called a horizontal conveying method which can suck an IC with a vacuum suction head and convey the IC absorbed by the X-Y conveying means to an arbitrary place.

As an IC test apparatus equipped with a horizontal transfer type handler, the following two types are conventionally assisted in practical use.

(1) A tray on which a plurality of ICs are placed in a planar shape is placed at a predetermined position of an IC test apparatus, and a predetermined number of ICs are sucked from the tray on which the ICs are mounted by a vacuum adsorption head, and the adsorbed ICs are XY conveying means. A test is carried out by sequentially returning from the preheating part to the testing part using the tester, and the test IC is returned to the tray while being classified as good or defective using the XY conveying means.

(2) It is used by the user to carry the IC outside the IC tester or to store it in a predetermined place. Place a plurality of ICs in a flat shape on the general purpose tray (Castmart Ray), that is, place the ICs placed thereon in the loader section of the IC test apparatus, and at this loader part, high / low temperature from the general purpose tray. Send the IC to the test tray which withstands the test, and return the test tray to the test section through the thermostat.The test section performs the test by electrically contacting the IC with the test head with the IC mounted on the test tray. After completion of the test tray, the test tray is taken out to the unloader unit through the heat removal tank, and the unloader unit transfers the tested IC to the general-purpose tray while classifying the tested IC from the test tray as good or bad.

The IC testing apparatus equipped with the handler of the former type (1) is slow in processing speed and time-consuming because the number of ICs that can be tested at a time is limited to about two to four. As a result, it is not suitable for high speed processing. Since the IC test apparatus equipped with the latter type (2) handler can be brought into contact with the test head of the test apparatus while the IC is mounted on the test tray, the test apparatus can be connected to 16, 32 or 64 at a time. Multiple ICs can be tested. Therefore, IC test apparatuses equipped with handlers of the latter type (2) are now mainstream.

First, with reference to FIG. 4 and FIG. 5, the outline structure of the conventional IC test apparatus equipped with the handler of the latter form (2) is demonstrated. The illustrated IC test apparatus includes a chamber unit 100 for testing an IC such as, for example, a semiconductor memory carried in a test tray TST, and an IC (test IC) and a test IC for testing from these. The IC storing part 200 which classifies and stores, and the loader part which transfers and puts the IC under test which the user put into the general-purpose tray (Kastmart Ray) (KST) to the test tray (TST) which withstands high / low temperature, and places it An unloader for transferring the test 300 from the test tray TST to the general purpose tray KST after the test in the chamber 300 and the chamber unit 100 is completed and the test IC is placed and returned to the test tray TST. The part 400 is provided. In general, the unloader unit 400 is configured to classify the tested ICs into categories based on the data of the test results and to mount them in the corresponding general purpose trays.

The chamber part 100 is a thermostat 101 which gives the target high temperature or low temperature stress to the IC under test loaded in the test tray TST, and in the state in which the temperature stress was applied to this thermostat 101. And a test chamber 102 for carrying out an electrical test of the IC, and a heat removing tank 103 for removing the temperature stress applied from the thermostat 101 from the IC where the test in the test chamber 102 is completed. have. The test chamber 102 includes a test head 104 of the IC test apparatus therein, and the test head 104 is connected to the test head 104 electrically in contact with the test head 104. At the same time as supplying the electrical signal, it receives the response signal from the IC under test and sends it to the test apparatus.

The test tray (TST) is a thermostatic chamber (101) of the loader section 300 → the chamber section (100) → the test chamber (102) of the chamber section (100) → the heat removal tank (103) of the chamber section (100). 400 is circularly moved with the loader 300. The thermostat 101 and the heat removal tank 103 are higher than the test chamber 102 and, therefore, have a portion protruding upward. Between these thermostats 101 and the upper part which protrudes above the heat removal tank 103, the board | substrate 105 is handed over as shown in FIG. 5, and the test tray conveyance means 108 on this board | substrate 105 is carried out. The test tray TST is conveyed from the heat removal tank 103 side toward the constant temperature tank 101 by the test tray conveying means 108.

When the high temperature stress is applied to the IC under test by the thermostat 101, the heat removal tank 103 cools by blowing, returns to room temperature, and carries it out to the unloader part 400. FIG. In the case where a low temperature stress of, for example, about -30 ° C is applied to the IC under test in the thermostat 101, the unloader part is heated by heating with a warm air or a heater, and then returned to a temperature at which no dew condensation occurs. To 400).

The test tray TST in which the IC under test is loaded in the loader 300 is transferred from the loader 300 to the thermostat 101 of the chamber 100. The thermostat 101 is equipped with a vertical transfer means, which is configured to support a plurality of test trays TST (for example, nine sheets) in a stacked state. In the example of illustration, the test tray from the loader part 300 is supported at the top, and the test tray at the bottom is carried out to the test chamber 102. The IC under test is either hot or cold while the top test tray is sequentially moved to the bottom by the vertical downward movement of the vertical conveying means, and while waiting for the test chamber 102 to be empty. Given a predetermined temperature stress. In the test chamber 102, a test head 104 is disposed at the center thereof, and a test tray TST, which is carried out one by one from the thermostat 101, is transported above the test head 104 to be described later. A predetermined number of ICs under test in the IC under test are electrically connected to an IC socket (not shown) attached to the test head 104. When the test of all the tested ICs on one test tray through the test head 104 is finished, the test tray TST is returned to the heat removing tank 103 to remove the temperature stress of the tested IC, thereby reducing the temperature of the IC. It returns to room temperature and discharges to the unloader part 400.

The heat removal tank 103 also has a vertical transport means similar to the thermostat 101, and is configured to support a plurality of test trays TST in a stacked state by the vertical transport means. It is. In the example of illustration, the test tray from the test chamber 102 is supported at the bottom, and the test tray at the top is discharged to the unloader unit 400. While the test tray at the bottom is sequentially moved to the top by the vertical upward movement of the vertical conveying means, the test IC is removed to return to the external temperature (room temperature).

Tested ICs on the test trays TST discharged to the unloader unit 400 are classified for each category of test results from the test trays, and are transmitted and stored in the corresponding universal trays KST. The test tray TST emptied from the unloader unit 400 is conveyed to the loader unit 300, where the IC under test is transmitted and placed again in the general purpose tray KST. Hereinafter, the same operation is repeated.

As the IC transfer means for transferring the IC from the general purpose tray KST to the test tray TST in the loader 300, as shown in FIG. 5, on the upper part of the loader 300 of the substrate 105, It is hypothesized between two parallel rails 301 which are hypothesized so as to extend in the front-rear direction of the test apparatus (this direction is set to the Y-direction), and these two rails 301 are installed in the Y-direction. According to the movable arm 302 whose both ends are supported by these two rails 301 and the extending direction of this movable arm 302 so that a movement is possible, the left-right direction of a test apparatus (this direction shall be X direction) The XY conveyance means 304 comprised by the movable head 303 supported by the movable arm 302 to be movable by (circle)) can be used. According to the above configuration, the movable head 303 can reciprocate in the Y direction between the test tray TST and the general purpose tray KST, and can also move in the X direction along the movable arm 302.

The IC suction pad is mounted on the lower surface of the movable head 303 so as to be movable upward and downward. The IC suction pad is mounted on the universal tray KST by the XY direction movement of the movable head 303 and the downward movement of the suction pad. The suction pad contacts the IC, and the IC is sucked and held by the vacuum suction action, and the IC is returned from the general purpose tray KST to the test tray TST. For example, about eight suction pads are attached to the movable head 303, and eight ICs are configured to be transported from the general purpose tray KST to the test tray TST at one time.

Further, between the stop position of the general-purpose tray KST and the stop position of the test tray TST, an IC position correcting means 305 (Fig. 5) called a pulley screw is provided. The position correcting means 305 has a relatively deep recess, and once the IC is sucked by the suction pad and conveyed to the test tray TST is dropped. The periphery of the recess is surrounded by an inclined surface, which defines the dropping position of the IC. After precisely defining the positions of the eight ICs by the position correcting means 305, the ICs having these positions defined are adsorbed again by the suction pads and returned to the test tray TST. The reason for providing the position correction means 305 is that in the universal tray KST, the recess holding the IC is formed relatively larger than the shape of the IC, and therefore, the position of the IC stored in the universal tray KST. There is a big deviation in this situation, and if the IC absorbed by the adsorption pad in this state is directly returned to the test tray TST, there is an IC that cannot be dropped directly into the IC storage recess formed in the test tray TST. For this reason, the position correction means 305 is provided, and the position correction means 305 is made to match the arrangement precision of an IC with the arrangement precision of the IC storage recessed part formed in the test tray TST.

The unloader 400 is provided with two sets of transport means 404 having the same structure as the XY transport means 304 set in the loader 300, and the unloader part 400 by these XY transport means 404. In the test tray (TST) exported to the test IC is replaced with a universal tray (KST). Each XY conveyance means 404 is constructed between two parallel rails 401 hypothesized so as to extend in the front-back direction (Y direction) of a test apparatus, and these two rails 401, The movable arm 402 whose both ends are supported by these two rails 401, and the movable arm movably in the left-right direction (X direction) according to the extending direction of this movable arm 402 are movable. It is comprised by the movable head 403 supported by 402.

6 shows a structure of an example of the test tray TST. The test tray TST is formed in a rectangular frame 12 with a plurality of bridges 13 in parallel and at equal intervals, and on both sides of these bridges 13 and the frame 12 facing the bridge 13. A plurality of attachment pieces 14 are formed on the sides 12a and 12b at equal intervals, respectively. The attachment pieces 14 on both sides of each bridge 13 are formed so that one attachment piece 14 is located in the middle of the attachment piece 14 on the opposite side. Similarly, the sides 12a, The attachment piece 14 of 12b) is formed so that it may be located in the middle of the attachment piece 14 of the bridge 13 which opposes. In the space between these opposed bridges 13 and the space between the bridge 13 and the opposite sides 12a and 12b, a plurality of IC carriers 16 are stored in a juxtaposed state, respectively. Each IC carrier 16 is housed in a carrier housing portion 15, which is a rectangular section containing two obliquely opposed attachment pieces 14, which are displaced in these spaces, in each of the diagonal directions. Therefore, in the example of illustration, since 16 attachment pieces 14 are formed in one side of each bridge 13, 16 carrier storage parts 15 are formed in each said space, and 16 IC carriers 16 are attached. It is. In the example of illustration, since there are four spaces, the IC carrier 16 can attach 16 * 4 pieces, 64 pieces in total to one test tray TST. Each IC carrier 16 is attached to two attachment pieces 14 by fasteners 17.

The outer shape of the IC carrier 16 is the same shape and same dimension, and the IC accommodating part 19 which accommodates an IC element is formed in the center part. The shape (shape) and dimensions of the IC accommodating portion 19 are determined in accordance with the shape and dimensions of the IC element to be accommodated. The IC accommodating part 19 is called a rectangular recess in this example. The outer shape of the IC accommodating portion 19 is selected to be loosely fitted in the space between the opposing pieces of the carrier accommodating portion 15, and is disposed on the attachment piece 14 at both ends of the IC accommodating portion 19. The protrusions are respectively installed. Both of these protrusions are formed with a mounting hole 21 into which the fastener 17 is inserted and a hole 22 into which the positioning pin is inserted.

A pair of latches 23 are attached to the IC carrier 16 as shown in FIG. 7, for example, to prevent misalignment or ejection of the IC elements stored in the IC carrier 16. These latches 23 are integrally formed so as to protrude upward from the bottom surface of the IC accommodating portion 19, and due to the elasticity of the resin material constituting the IC carrier 16, these latches 23 are their tip portions. Opposing nails are elastically biased in the closing direction. Accordingly, the latch release mechanism 25 disposed on both sides of the IC adsorption pad 24 for adsorbing the IC element when the IC element is accommodated in the IC accommodation portion 19 or taken out from the IC accommodation portion 19. By widening the space | interval of the front-end | tip part of two latches 23 by this, IC acceptance or extraction is performed. When the latch release mechanism 25 is detached from the latch 23, the latch 23 is returned to its original state by its elastic force, and the received IC is kept in the nail-proof state at the distal end of the latch 23. .

The IC carrier 16 holds the IC element in a state where the pin 18 of the IC element is exposed on the lower surface side as shown in FIG. The test head 104 has an IC socket, and a contact 26 of the IC socket protrudes upward from the upper surface of the test head 104. The exposed pin 18 of the IC element is pressed against the contact 26 of the IC socket, that is, pushed to electrically connect the IC element to the IC socket of the test head. For this reason, a pressure contactor (pusher) 20 is installed on the upper portion of the test head 104 to press down the IC element, and the pressure contactor 20 is placed above the IC element housed in each IC carrier 16. It is comprised so that it may press and press from and will come into contact with the test head 104. FIG.

The number of IC elements connected to the test head 104 at one time depends on the number of IC sockets attached to the test head 104. For example, in the case where the IC elements are arranged in four rows by 16 columns as shown in Fig. 9, it is possible to test all the IC elements (elements indicated by diagonal lines) arranged in four columns of each row at a time of 4? 4. Sixteen IC sockets are attached to the test head 104. As a result, the first test is performed on 16 IC elements arranged in columns 1, 5, 9, and 13 of each row, and the second test is performed by moving the test tray TST by one column of IC elements. Sixteen IC elements arranged in rows 2, 6, 10, and 14 are performed, and the test of all the IC elements placed in one test tray is completed by performing the following four tests in the same manner. The result of the test is determined by the serial number (serial number in one lot) assigned to each IC, the identification number assigned to the test tray (TST), and the number assigned to the IC accommodating part of the test tray (TST). The memory is stored in the corresponding address of the memory. Here, when 32 IC sockets can be attached to the test head 104, all 64 IC elements arranged in 4 rows and 16 columns can be tested only by performing two tests. In the test chamber 102, there is also a handler in which the IC under test is transferred from the test tray to the socket of the test head 104 for testing, and after completion of the test, the IC is transferred from the socket to the test tray and returned.

The IC storing unit 200 includes an IC stocker 201 for receiving a universal tray (KST) storing an IC under test, and a universal tray (KST) containing test ICs classified for each category according to the test results. A tested IC stocker 202 is installed to accommodate the above. These IC stocker 201 and the tested IC stocker 202 are comprised so that a universal tray can be accommodated in a laminated state. The universal tray (KST) storing the IC under test stored in the stacked state in the IC stocker 201 is transferred from the upper tray to the loader unit 300 sequentially, and the universal tray KST in the loader unit 300 is stored. The IC under test is stacked on the test tray TST stopped by the loader 300 from the stack.

The IC stocker 201 and the tested IC stocker 202 preferably have the same shape and structure, and as shown in FIG. 10, a tray support having an upper surface open and an opening at the bottom surface thereof is shown. A frame 203 and an elevator 204 disposed below the tray support frame 203 and capable of lifting up and down inside the tray support frame 203 through an opening in the bottom surface of the tray support frame 203. Doing. In the tray support frame 203, a plurality of universal trays (KST) are stacked and stored and supported, and the stacked universal trays (KST) intrude from the bottom of the tray support frame (203). It moves up and down by.

In the example shown in FIG. 4 and FIG. 5, eight stockers STK-1, STK-2, ..., STK-8 are prepared as the tested IC stocker 202, and according to a test result, it can be divided into eight categories. It is configured to be classified and stored. This is because in addition to distinguishing the tested IC from good and defective, the operating speed can be classified into high speed, medium speed, low speed, or retesting required even in bad quality. . Even if there are eight types of categories that can be classified, only four general purpose trays KST can be arranged in the unloader 400 in the example of the illustration. For this reason, when a test IC element classified into a category other than the category assigned to the general purpose tray KST disposed in the unloader unit 400 is generated, one universal tray (KST) from the unloader unit 400 is generated. ) Is returned to the IC storing unit 200, and instead of this, a general purpose tray (KST) which should store an IC element of a newly generated category is transferred from the IC storing unit 200 to the unloader unit 400, and The order of storing IC elements is taken.

As shown in FIG. 5, the IC stocker 201 and the tested IC stocker 202 are disposed on the upper portion of the IC stocker 201 and the tested IC stocker 202 between the substrate 105 and the substrate 105. The tray conveying means 205 which is movable over the whole range of the arrangement direction (left-right direction of a test apparatus) of the is provided. This tray conveying means 205 is provided with the holding | gripping tool holding the general purpose tray KST in the lower surface. The tray conveying means 205 is moved to the upper part of the IC stocker 201 under test, driving the elevator 204 in that state, and raising the universal tray KST stacked in the stocker 201. The uppermost tray of the rising universal tray KST is gripped by the holding hole of the tray conveying means 205. When the uppermost universal tray KST containing the IC under test is delivered to the tray conveying means 205, the elevator 204 descends and returns to its original position. The tray conveying means 205 moves in the horizontal direction and stops at the position of the loader 300. In this position, the tray conveying means 205 removes the universal tray from the gripper and lowers the universal tray KST to a tray support (not shown) positioned slightly downward. The tray conveying means 205 having lowered the universal tray KST on the tray support moves to a position other than the loader 300. In this state, the elevator 204 ascends from the bottom of the tray support on which the universal tray KST is placed, and raises the tray support upward. Therefore, the universal tray KST on which the IC under test is mounted also rises upward, and remains in a state where the universal tray KST is exposed to the window 106 formed on the substrate 105.

The same window 106 is formed in the board | substrate 105 of the upper part of the unloader part 400, and the empty general-purpose tray is maintained by exposing these windows 106 from the state. Each window 106 has dimensions that two universal trays expose in this example, and thus four empty universal trays are exposed from the two windows 106 of the unloader unit 400. In the general purpose trays KST of these windows, the tested ICs are classified and stored according to the category assigned to each general purpose tray. As in the case of the loader 300, each universal tray is mounted on a tray support, and each tray support is lifted up and down by the elevator 204. When one universal tray becomes full, the universal tray KST is lowered from the position of the window 106 by the elevator 204 to the tray storage position of the category assigned to the one by the tray conveying means 205. It is stored. 4 and 5 indicate an empty tray stocker accommodating the empty universal tray KST. From this empty tray stocker 206, the empty general purpose tray is conveyed and held at the position of each window 106 of the unloader unit 400 by the tray conveying means 205 and the elevator 204 to store the tested IC. Will contribute.

As described above, in an IC test apparatus equipped with a handler of the type (2) in which ICs are stacked in a test tray, conveyed to a test section (chamber section), and tested, a large number of ICs can be tested at one time. As a result, the time required for the test can be shortened. On the other hand, since the unloader unit 400 can only classify and transfer about eight ICs at a time from the test tray to the general purpose tray, the transfer operation of the tested IC takes time. Nevertheless, since the work is performed while classifying, this sorting work takes time. For this reason, although two X-Y conveying apparatuses are provided in the unloader part 400, the inconvenience which the time required for classification becomes longer than the time required for a test still arises.

In the IC test apparatus equipped with the handler of the above-mentioned type (2), the XY conveying means 404 is used when the unloader 400 transmits the test IC from the test tray TST to the general purpose tray KST. Stores in the storage device the transfer of the tested IC to the general-purpose tray at the address assigned to each IC carrier 16 on the test tray TST, and transfers it to the test tray TST based on this memory. The transfer operation is performed so that the IC forgotten is not left, but in rare cases, the IC forgotten to transfer remains on the test tray.

If the IC is left in the unloader unit 400, the test tray TST is conveyed to the loader unit 300 as it is, so that the loader unit 300 repeatedly mounts the IC under test on the remaining tested IC. It is thrown away. In this case, since the IC under test which is overlapped in two stages protrudes from the surface of the test tray, when the next test tray is piled up inside the thermostat 101, the IC under test which protrudes upwards is When the next test tray is inserted, it causes the inconvenience of being pushed down or falling off.

When an accident such as the IC falling from the test tray TST inside the thermostat 101 occurs, the IC dropped to a transport apparatus installed in the lower part of the thermostat 101 interferes and becomes impossible to carry. There is a risk of an accident. In addition, when the stacked test ICs are tested without overflowing and dropping out to the unloader 400, the upper ICs are classified according to the test results of the lower tested ICs. There is also the inconvenience of being done.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device testing apparatus suitable for testing semiconductor devices, in particular, semiconductor integrated circuit devices (hereinafter, referred to as ICs) which are representative examples thereof. More specifically, the present invention conveys a semiconductor device for testing, and the test section electrically contacts the semiconductor device to a test head (a portion of a test apparatus that supplies and receives various electrical signals for testing). A semiconductor device testing apparatus of a type in which a test is carried out, and after the test, the semiconductor device is taken out from the test section, and the semiconductor device (hereinafter referred to as the "tested semiconductor device") whose test is finished according to the test result is classified into good or bad. And a semiconductor device test system including a plurality of such semiconductor device test apparatuses.

Fig. 1 is a block diagram for explaining the overall configuration of a first embodiment of an IC test system according to the present invention.

FIG. 2 is a schematic perspective view showing an example of a container that can contain and transport a plurality of general purpose trays that can be used in the IC test system shown in FIG. 1 as one set.

Fig. 3 is a block diagram for explaining the overall configuration of the second embodiment of the IC test system according to the present invention.

4 is a schematic plan view showing a chamber part in a perspective view of an example of a conventional IC test apparatus.

5 is a schematic perspective view of the IC test apparatus shown in FIG. 4.

6 is an exploded perspective view for explaining the structure of an example of a test tray used in an IC test apparatus.

FIG. 7 is a schematic perspective view for explaining a storage state of the IC in the test tray shown in FIG. 6.

FIG. 8 is an enlarged cross-sectional view for explaining an electrical connection state between an IC under test and a test head mounted in the test tray shown in FIG.

9 is a plan view for explaining the procedure of testing the IC under test mounted on the test tray.

Fig. 10 is a perspective view for explaining the structure of the stocker for storing the general purpose tray used in the IC test apparatus.

Fig. 11 is a schematic perspective view for explaining the configuration of main parts of an embodiment of an IC test apparatus according to the present invention.

12 is a schematic cross-sectional view of FIG.

FIG. 13 is an enlarged perspective view of a part of the IC test apparatus shown in FIG. 11 taken out.

Disclosure of the Invention

It is a first object of the present invention to provide an IC test system capable of performing highway transfer work of a tested IC from a test tray in an unloader section to a general purpose tray.

A second object of the present invention is to provide a plurality of IC test apparatuses, and to test a plurality of ICs sequentially using different IC test apparatuses for different conditions. It is to provide an IC test system in which a plurality of tests are carried out in the shortest possible time, and at the same time, the sorting work performed according to these test results can be performed in a short time.

A third object of the present invention is to provide an IC test apparatus capable of preventing an accident in which a tested IC is left over a test tray.

A fourth object of the present invention is to provide an IC test apparatus capable of detecting an overflow of an IC from a test tray equipped with an IC.

According to the first aspect of the present invention, in the loader section, the IC under test is stacked from the general purpose tray to the test tray, and the test tray equipped with the IC under test is transported from the thermostat to the test section, and the test section is mounted on the test tray. An IC test system provided with an IC test apparatus for testing a used IC, and carrying out a test tray to an unloader unit after completion of the test, and transferring the test IC to the general-purpose tray from the unloader unit. In addition to providing a sorting device for performing the sorting operation of the tested IC, a storing information storage means is installed in the host computer or the IC testing device that controls the IC testing device, and the serial number attached to each IC and the general purpose tray. The universal t number to the address of the storing information storage means determined by the identification number attached to the number and the number attached to each IC storage section of the general purpose tray. The test results of the test ICs stored in the respective IC accommodating units and the storing information such as the socket number contacted by the test unit are stored, and the sorting operation of the test ICs is performed by the classifying device based on the storing information. An IC test system is provided which allows the operation.

According to the IC test system according to the first aspect, all the tested ICs can be sorted by using the storing information stored in the storing information storage means by the classifying device. Therefore, since the unloader unit only needs to transfer the IC from the test tray to the general purpose tray without sorting, the ICs can be stacked at high speed. In particular, since there are many classifications, even if the general purpose tray of the corresponding category is not arranged in the unloader section, there is no need to convey the general purpose tray of the category to the unloader section, thereby increasing the processing speed.

According to the second aspect of the present invention, in the loader section, the IC under test is stacked from the general purpose tray to the test tray, and the test tray equipped with the IC under test is returned from the thermostat to the test section, and the test section is transferred to the test tray. In the IC test apparatus, a plurality of IC test apparatuses for testing the mounted IC, and carrying out the test tray to the unloader section and transferring the tested IC to the general-purpose tray after the test is completed, In an IC test system for performing a plurality of tests with different test conditions, a host computer for providing a sorting exclusive device for sorting a test IC mounted on the general-purpose tray and controlling the name IC test apparatus. Alternatively, a storage information storage means is provided in the IC test apparatus, and the serial number attached to each IC, the identification number attached to each universal tray, and the general purpose. At the address of the storage information storage means determined by the number attached to each IC storage unit of the ray, the test result of the tested IC contained in each IC storage unit of the general-purpose tray, the socket number, etc. contacted by the test unit. Information is stored, and the name IC test apparatus classifies the tested IC into only two types of good and defective items, and stores the information of the tested IC by the classifying device based on the stored information stored in the storing information storage means. An IC test system is provided to allow the rest of the classification work.

According to the IC test system according to the second aspect, since the sorting work in the unloader section is limited to two homes, the transfer work to the general-purpose tray is faster than the case where the unloader section is classified into all categories. Is done. At the same time, the IC once determined to be defective is not supplied to the test under the following test conditions, so that the IC which is determined to be defective is not tested again and the test time is shortened. Therefore, there is an advantage that the IC can be tested at high speed. In addition, the information stored in the storage information storage means was used to classify the tested ICs into detailed classifications using the classifier, so that even if a general purpose tray of a corresponding category is not arranged in the unloader section, It is not necessary to convey the tray to the unloader portion, and thus the processing speed can be increased.

According to the third aspect of the present invention, in the loader section, the IC under test is stacked from the general-purpose tray to the test tray, and the test section is transferred to the test section, the IC section is tested in the test section, and the test section is taken out to the unloader section after the test is completed. In the IC test apparatus, the test IC is transferred from the unloaded part to the unloader part, and a new test IC is loaded into the empty test tray from the unloader part to test the IC continuously. An IC test apparatus is provided between the part and the loader part, which is provided with an IC detection sensor for detecting whether an IC exists in a test tray error during a movement, and can detect a state in which an IC is left in the test tray error. .

According to the fourth aspect of the present invention, in the loader section, the IC under test is changed from the general-purpose tray to the test tray, stacked and returned to the test section, whereby the IC section is tested in the test section, and the test section is taken out to the unloader section. In an IC test apparatus for moving a test IC from a test tray to a general purpose tray, sending an empty test tray from an unloader section to a loader section, and stacking new test ICs on the empty test tray in the loader section to test the IC continuously. There is provided an IC test apparatus provided with an IC detection sensor for detecting whether an empty IC accommodating portion is present in a test tray in the middle of a conveyance path of a test tray conveyed from a test section toward an unloader section.

Further, according to the fifth aspect of the present invention, in the loader section, the IC under test is stacked in the test tray from the general-purpose tray, stacked and returned to the test section, the IC section is tested in the test section, and the test section is taken out to the unloader section after completion of the test. In an IC test apparatus for moving a test IC from a test tray to a general purpose tray, sending an empty test tray from an unloader section to a loader section, and stacking new test ICs on the empty test tray in the loader section to test the IC continuously. An IC test apparatus having a function of monitoring whether or not the IC accommodating portion of the test tray is empty in the middle of the conveyance path of the test tray conveyed from the loader portion to the test portion is provided.

According to the IC test apparatus according to the third aspect, even if an IC is left over the test tray moving from the unloader to the loader, the presence of the IC can be detected by the IC detection sensor. When the loader portion is reached, the remaining IC in the loader portion can be removed from the test tray. As a result, the IC is not stacked in two stages, and accidents such as the IC at the top falling downward in the thermostat can be prevented from occurring. Thus, an IC test apparatus with high stability can be provided.

According to the IC test apparatus according to the fourth aspect, even if the IC of the test fill overflows and disappears from the test tray in the test section, the IC is transferred while the test tray is conveyed from the test section to the unloader section. The position of the IC housing of the lost test tray can be detected. Therefore, the unloader unit can stop the sorting operation on the detected IC storage unit, and can shorten the time required for the sorting operation.

Furthermore, according to the IC test apparatus according to the fifth aspect, even if the IC is dropped from the test tray while the test tray is being conveyed from the loader to the test unit, the test tray is transferred to the test unit until it is returned. The IC storage portion of the empty test tray can be detected. Therefore, since the test section can stop the test operation on the empty IC storage section of the test tray, it is not necessary to spend useless time, and the test time can be shortened.

Best Mode for Carrying Out the Invention

1 shows a first embodiment of an IC test system according to the present invention. This IC test system is equipped with three IC test apparatuses 1A, 1B, and 1C. Each of the IC test apparatuses 1A, 1B, and 1C has the same configuration, and the electrical part of the IC test apparatus that applies a test signal of a predetermined pattern to the IC under test and measures its electrical characteristics, that is, the IC tester part (10) (main part of the lower part of FIG. 5) and the handler part 11 (main part of the upper part of FIG. 5) are comprised. The IC tester unit 10 of each IC test apparatus is placed under the control of the host computer 2 and is controlled by the host computer 2. The classifier 3 for sorting the ICs of the test pieces is also performed. Is installed. In general, two handler sections 11 are incorporated into one IC tester section 10 and are often operated as one IC test apparatus. Although not shown in the drawing, two handler parts 11 are assembled in each IC test apparatus.

The handler part 11 of each IC test apparatus 1A, 1B, and 1C is a chamber for testing the IC which is mounted on the test tray and conveyed in the same manner as the conventional IC test apparatus described above with reference to FIGS. 4 to 10. An IC storage section for classifying and storing the section, the IC under test and the IC under test, a loader section for transferring the IC under test, which the user has previously placed in the general-purpose tray, to a test tray that can withstand high and low temperatures, and The unloader part which transfers and correctly puts the IC of the test which was carried and carried in the test tray and conveyed by the test tray from the test tray to the general purpose tray is provided. The chamber section includes a thermostat that imparts a high temperature or low temperature stress to the IC under test loaded on the test tray, and an IC in which the temperature stress is applied in the thermostat. The test chamber which electrically contacts a test head and performs a test, and the heat removal tank which removes the temperature stress provided by the thermostat in the IC which the test in the test chamber completed.

In this embodiment, each of the IC test apparatuses 1A, 1B, and 1C tests the IC under the same test conditions, and sorts the IC of the test piece from the test tray at the unloader portion of each handler portion 11 at all. After the test is completed and all the tests are completed, the test IC is transported to the classifier 3, and the classifier for classifying the test IC is collectively performed. It is to be done.

For this reason, in this embodiment, the storing information storage means 4 is provided in the host computer 2. The storing information storage means 4 stores all the test results of the IC. These test results include the serial number assigned to each IC, the identification number assigned to each universal tray, and the universal tray each time the unloader section of each handler section 11 transfers the tested IC from the test tray to the universal tray. The address of the storage information storage means 4 to be stored is determined based on the number or the like assigned to each IC storage unit, and stored in the address. As test results, the conditions of the test, the classification of operating speeds such as high speeds, medium speeds, and low speeds in good parts, the necessity and unnecessary necessity of retesting in bad parts, and the socket number of the test head contacted during the test are stored. The stored information is transferred to the host computer 2 via the IC tester unit 10 by communication means 5 such as a GPIB communication port or an RS232C communication port between computers, for example, and the storage information storage means. It is memorized in (4).

The storage information storage means 4 can be configured as a memory. The storage information stored in the storage information storage means 4 is stored in a storage medium such as a floppy disk for each IC test apparatus 1A, 1B, and 1C, for example, and provided to the classification dedicated device 3, or the communication means 5 ) Can be transmitted to the classifier 3.

A general-purpose tray equipped with a test IC which is transmitted without being classified by the unloader section of each handler section 11, for example, as shown in Fig. 2, accommodates a plurality of universal trays KST therein in a horizontal position. It may be housed in a box-shaped container 27 provided with a shelf that can be stored and transported to a sorting-only machine 3, or a tray conveying device may be installed between each handler section 11 and the sorting-only machine 3, respectively. It is also possible to carry it to the sorting device 3 by these tray transfer devices. The container 27 is provided with the opening-closing cover 28 for allowing the general purpose tray KST in and out. In the sorting-only machine 3, the IC is taken out from the general purpose tray KST carried in the sorting-only machine 3 by the IC adsorption pad provided in the sorting-only machine 3, and stored in the address corresponding to the take-out position. According to the information, classification of the tested IC is performed.

3 shows a second embodiment of the IC test system according to the present invention. The IC test system of this second embodiment also includes three IC test apparatuses 1A, 1B, and 1C similarly to the test system of the first embodiment. Each of the IC test apparatuses 1A, 1B, and 1C has the same configuration, and the IC tester section 10, which is an electrical part of the IC test apparatus that applies a test signal of a predetermined pattern to the IC under test and measures its electrical characteristics. ) And the handler section 11. The IC tester unit 10 of each IC test apparatus is placed under the management of the host computer 2 and controlled by the host computer 2. In addition, a sorting exclusive machine 3 for sorting a test IC is provided. Also in this embodiment, two handler portions 11 are inserted into each IC test apparatus.

The handler part 11 of each IC test apparatus 1A, 1B, and 1C is a chamber for testing the IC which is mounted on the test tray and conveyed in the same manner as the conventional IC test apparatus described above with reference to FIGS. 4 to 10. An IC storage section for classifying and storing the section, the IC under test and the IC under test, a loader section for transferring the IC under test, which the user has previously placed in the general-purpose tray, to a test tray that can withstand high and low temperatures, and The unloader part which transfers and correctly puts the IC of the test which was carried and carried in the test tray and conveyed by the test tray from the test tray to the general purpose tray is provided. The chamber section includes a thermostat that imparts a high temperature or low temperature stress to the IC under test loaded on the test tray, and an IC in which the temperature stress is applied in the thermostat. The test chamber which electrically contacts a test head and performs a test, and the heat removal tank which removes the temperature stress provided by the thermostat in the IC which the test in the test chamber completed.

In this second embodiment, each IC test apparatus 1A, 1B, and 1C tests the IC under different test conditions. As the conditions of the test, for example, different temperatures or different operating voltages are given to the IC under test. In addition, the storage information storage means 4 is provided in the host computer 2.

First, all the ICs under test are tested in the IC tester 1A. The IC under test is mounted on the general-purpose tray and transported to the handler section 11 of the IC test apparatus 1A. A multi-purpose tray is stacked and stored in a plurality of containers 27 for transport as shown in FIG. 2 described above, for example, and in the handler part 11, the opening and closing cover 28 of the container 27 is opened and the handler part 11 is disposed. ) Is mounted. The general purpose tray KST is carried out one by one from the container 27 and sent to the loader part. The IC mounted in the universal tray KST in this loader section is transmitted to the test tray, and the test tray is sent to the test chamber through the thermostat, and the test head section of the IC tester section 10 disposed in the test chamber. The IC is in electrical contact and the electrical characteristics of the IC are tested. When all the tests of the IC mounted on the test tray are completed, the test tray is taken out from the test chamber, and the temperature stress is removed from the heat removing tank and discharged to the unloader unit.

Tested ICs above the test tray are transferred to the universal tray (KST) in this unloader section. In this manner, in the second embodiment, at least two empty universal trays KST are prepared, and the tested ICs are classified only as good or defective. When the general-purpose tray KST is filled with good and defective goods, the full-purpose tray KST is returned to the container 27 by the conveying means. At this time, in the container 27, the general purpose tray KST which mounted the defective goods from the lower end side is stored, for example, and the general purpose tray KST which accommodated the good goods is stored from the upper end side. In this way, the general-purpose tray which stores the good goods and the defective goods in the container 27 is distinguished.

When the test by the IC test apparatus 1A is completed, the container 27 containing the general purpose tray KST equipped with the tested IC is moved to the next IC test apparatus 1B as described above.

In the IC test apparatus 1B, tests with different conditions are executed, but only the general-purpose tray equipped with the good-tested IC of good quality is taken out from the container 27 and sent to the loader part, and only the IC determined as good quality is tested. When a defective product occurs in the second test in the IC test apparatus 1B, a general purpose tray (with a gap in the IC storage part) on which the defective product is stored in the container 27 is conveyed to the unloader part. Then, the tested IC determined as defective in the IC test apparatus 1B is transferred from the test tray to this general purpose tray. When there is no space in the IC storage portion of the general-purpose tray on which the defective product is placed in the container 27, the empty general-purpose tray is conveyed from the container 27 or from the beam tracer to the unloader part.

In the IC test apparatus 1B, when all the tested ICs judged as good quality by the IC test apparatus 1A have been tested, and the general purpose tray on which the good and defective items are stored is stored in the container 27, the container 27 is next Is transferred to the IC tester (1C). In this IC test apparatus 1C, tests with different conditions are carried out, but similar to the IC test apparatus 1B in the previous stage, only the general-purpose tray equipped with a good-test IC is taken out of the container 27, and the loader section Only the ICs sent to the product and judged to be good are tested. However, the IC test apparatus 1C of this final stage transmits the test results to the host computer 2 for each IC of each general purpose tray, and stores them in the storage information storage means 4 installed in the host computer 2. .

When a defective product occurs in the third test in the IC test apparatus 1C, a general purpose tray (with a gap in the IC storage part) on which the defective product is stored in the container 27 is conveyed to the unloader part. Then, the tested IC determined as defective in the IC test apparatus 1C is transferred from the test tray to this general purpose tray. When there is no space in the IC storage section of the general-purpose tray on which the defective product in the container 27 is loaded, the empty general-purpose tray is conveyed from the container 27 or from the tray stocker to the unloader section.

When all the ICs judged as good products are tested by the last two tests in the last IC test apparatus 1C, the container 27 is moved from the IC test apparatus 1C of the last stage to the classifier 3. In the sorting-only machine 3, the tested ICs in the container 27 are sorted according to the storing information sent from the host computer 2. In this case, since the storage information sent from the host computer 2 is only information related to the tested ICs sent from the IC test apparatus 1C at the final stage, it is judged as defective in the first and second tests. The test results of the tested ICs are not stored in the storage information storage means 4 of the host computer 2. Therefore, when it is desired to further classify the tested ICs judged as defective in the first and second tests, the sorting operation takes some time, but it is determined that the defective ICs are judged as defective in the IC test apparatuses 1A and 1B. The test result of the tested IC is transmitted to the host computer 2, stored in the storage information storage means 4, and after all tests are completed, the defective product in the container 27 in accordance with the storage information from the host computer 2. The tested ICs may also be classified by the class exclusive device 3.

In the first and second embodiments shown in Figs. 1 and 3, the case where three IC test apparatuses, 1A, 1B and 1C, are provided is illustrated, but the number of IC test apparatuses is not limited. Further, even the combination of the IC tester 1C and the classifier 3 can improve the processing speed of the handler portion 11. Therefore, even the combination of the IC tester 1C and the classifier 3 can achieve the above object of the present invention. Further, the IC test system of the second embodiment is effective even if applied to an IC test apparatus equipped with a handler of the type (1) described in the prior art.

Next, Fig. 11 shows an embodiment of an IC test apparatus according to the present invention. This IC test apparatus is equipped with a handler of the type (2) described above, and is an IC tester part which is an electrical part of an IC test apparatus which applies a test signal of a predetermined pattern to an IC under test and measures its electrical characteristics (Fig. It is comprised by the main part of 5 main lower part, and a handler part (mainly upper mechanism part of FIG. 5). The handler unit classifies and stores the chamber unit for testing the IC mounted on the test tray and conveyed in the same manner as the conventional IC test apparatus described above with reference to FIGS. 4 to 10, and the IC under test or the IC under test. The IC storage unit, the IC to be placed in the general purpose tray in advance, are transferred to a test tray that withstands high / low temperatures, the loader unit is correctly placed, and the test in the chamber unit is completed. An unloader section is provided for transferring the tested IC from the test tray to the general-purpose tray and placing it correctly. In addition, the chamber section is configured to provide a thermostat for imparting a high or low temperature stress to the IC under test loaded on the test tray, and an IC in which the temperature stress is applied to the IC to the test head of the IC tester. It consists of a test chamber which makes a test by making a contact, and a heat removal tank which removes the temperature stress provided by the thermostat in the IC which the test in the test chamber completed.

Fig. 11 is for explaining the configuration of the main part of this embodiment, and the test tray TST _l stopped at the unloader part 400 of the handler part and the test tray TST ₂ stopped at the loader part 300. ) And an IC detection sensor 500 provided between the unloader unit 400 and the loader unit 300. The IC detection sensor 500 performs an operation of detecting whether an IC is left in each IC carrier 16 (see Fig. 6) attached to the test tray TST, that is, whether an IC is left.

In this embodiment, the light transmitting type IC detection sensor 500 formed by the light source 501 and the light receiver 502 is disposed between the unloader 400 and the loader 300 between the test tray TST. The case where it is comprised so that it may face in the direction and orthogonally crosses a moving direction, and it detects whether IC is left on the test tray TST is shown.

The IC detection sensor 500 is provided corresponding to the number of rows (number of columns) of the IC carrier 16 mounted in the test tray TST. As a result, when the number of arrangement of the IC carriers 16 mounted in the direction perpendicular to the movement direction (the vertical direction) of the test tray TST is four, the number of four IC detection sensors 500 is shown. ) May be provided at an array pitch in the vertical direction of the IC carrier 16. In the example of illustration, although the light source 501 is arrange | positioned above the test tray and the light receiver 502 is arrange | positioned under the test tray, you may arrange | position in reverse to this.

A through hole 16A is formed in the bottom plate of each IC carrier 16 as shown in FIG. 12, and light passing through the through hole 16A is detected by the light receiver 502. In addition to the through hole 16A, the bottom plate of each IC carrier 16 has an opening through which light from the light source 501 passes (an opening exposed by an IC pin, etc.), so that only the light passing through the through hole 16A is detected. must do it. For this reason, as shown in an enlarged manner in Fig. 13, in this embodiment, each IC carrier arranged in the advancing direction of the test tray on one side of the side parallel to the advancing direction of the rectangular frame 12 constituting the test tray TST. At the position corresponding to the through hole 16A of the bottom plate of 16, the reflective mark 503A is attached. The reflection mark 503A is selected such that the length of the traveling direction is equal to or slightly larger than the diameter of the through hole 16A of the bottom plate of each IC carrier 16 arranged in the traveling direction of the test tray. Since the rectangular frame 12 of the test tray is made of a non-light reflecting member in this embodiment, the portion where the reflective mark 503A does not exist becomes the non-reflective mark 503B. Therefore, the reflective optical sensor 504 is disposed above the test tray, and the light projected from the optical sensor 504 and reflected by the reflective mark 503A is detected. While the light sensor 504 detects light reflected from the reflection mark 503A, the IC detection sensor 500 detects light passing through only the through hole 16A by detecting whether the light is detected and the IC. It is configured to detect the presence of.

In the above-described embodiment, an example of detecting whether an IC is left in the test tray abnormality conveyed from the unloader unit 400 to the loader unit 300 has been described, but the IC detection sensor 500 may be, for example, a loader unit ( It is also installed in the middle part of the path from the test head 104 to the test head 104 and the middle part of the path from the test head 104 to the unloader part 400 so that the test tray TST is loaded into the loader part 300. IC is dropped from the test tray TST while being conveyed from the test head 104 to the test head 104, and an empty IC housing portion exists and the IC is overflowed from the test tray TST during the test in the test head 104 so as to be empty. It is also possible to configure to detect that the IC housing portion exists.

Although the IC detection sensor 500 can increase the reliability of the IC test apparatus even if it is installed at any one of the above positions, the IC detection sensor 500 is provided between the unloader 400 and the loader and the test head. Both positions between the 104 and the unloader 400, or between the unloader 400 and the loader 300 and between the loader 300 and the test head 104 In this case, the reliability of the IC test apparatus can be further improved. Of course, if the IC detection sensor 500 is installed in all the above-described positions, the reliability of the IC test apparatus is the highest.

The arrangement relationship between the reflective mark 503A and the anti-reflective mark 503B is reversed from the state shown in Fig. 13, and the IC detection sensor 500 is carried out while the reflective optical sensor 504 does not detect the reflected light. The light passing through only the through hole 16A may be detected by detecting whether the light is detected, and the presence or absence of the IC may be detected.

In addition, the IC detection sensor 500 may be configured not only by the optical sensor of the transmission type but also by a proximity switch for detecting metal (metal in the IC), a camera having a pattern recognition function, or the like.

As described above, according to the IC test system of the first embodiment of the present invention, the handler portion 11 does not need to perform the classification operation. Furthermore, according to the IC test system of the second embodiment of the present invention, the handler part In (11), it is only necessary to perform the classification operation of only two categories by good or bad goods or other classification methods, so that the time required for the IC test for each IC test apparatus can be considerably shortened and processed. Can be speeded up. In addition, since each handler part 11 only needs to perform the classification | movement operation of two categories also in 2nd Embodiment, a structure can be simplified. Therefore, the cost of the handler section 11 can be reduced. In addition, since the IC under test contains the number of the socket contacted by the test section in the data stored in the storage information storage means, when the defect has concentrated in the IC in contact with the specific socket, the socket becomes defective. If you can, guess. Therefore, there is also an advantage that the failure of the socket in the test section can be detected. In addition, the classifier 3 can be manufactured at low cost because it is only necessary to classify. Therefore, there is an advantage that an IC test system which is inexpensive as a whole can be constructed.

In addition, according to the IC test apparatus of the first embodiment of the present invention, since the configuration for detecting that the IC is left in the test tray TST to be emptied is added, in the loader 300, on the left IC In this way, malfunctions such as newly stacked ICs can be prevented from occurring. Therefore, it is possible to prevent the occurrence of an accident such as that the IC overflows inside the thermostat 101 and breaks down the transport apparatus below. In addition, the stacked ICs are tested without being dropped off and carried out to the unloader unit 400, thereby preventing incorrect classification such as the upper IC being classified according to the test result of the lower IC. have.

Moreover, according to the IC test apparatus of the second embodiment of the present invention, even if the IC has overflowed from the test tray during the test in the test section or while the test tray is returned from the test section to the unloader section 400, In addition, the overflowed event can be detected. Therefore, a malfunction of virtually classifying ICs can be prevented from the IC storage section of a test tray or more in which no IC is present, according to the test result stored in the storage device. The sorting operation with respect to the IC housing portion can be stopped, thereby reducing the time required for the sorting operation.

In addition, according to the IC test apparatus of the third embodiment of the present invention, the IC is dropped while the test tray is transferred from the loader unit 300 to the test unit, or the test unit is tested on the test tray. It is not possible to load the IC, and even if there is an empty IC storage part in the test tray TST carried in the test part, such as when the IC is not loaded, the empty IC storage part can be detected. The test can be stopped for the empty IC housing. As a result, since the useless test is not performed, the test time can be shortened and a highly reliable IC test apparatus can be provided.

In addition, although the IC has been described as an example of the semiconductor device, the present invention can be applied to a test apparatus for testing a semiconductor device other than the IC, and needless to say, the same effect can be obtained.

Claims (7)

A semiconductor device test apparatus having a test apparatus section and a handler section, and a storage information storage means, wherein the loader section of the handler section transfers and mounts a plurality of semiconductor devices under test from a general purpose tray to a test tray, and mounts the test tray as a handler. The semiconductor device mounted on the test tray is electrically contacted with the test head of the test apparatus arranged in the test unit, and the operation of the semiconductor device is tested. The test tray is taken out from the test section to the unloader section of the handler section. In this unloader section, the tested semiconductor device of the test tray is stacked on a general-purpose tray, and the universal tray equipped with the tested semiconductor device is taken out from the handler section. Configured to Conductor device according to the test apparatus, In the unloader section, the tested semiconductor devices are stacked in the semiconductor device storage section of the general-purpose tray without sorting them, and the general-purpose trays are taken out from the handler, and the number assigned to each semiconductor device at the time of the stacking, Address information of each semiconductor device including at least the address information of each semiconductor device storage unit of the general-purpose tray, the test result of the semiconductor device, and the socket number used for the test in the test unit. Each time the stored tested semiconductor device is stored in the storage information storage means, the tested semiconductor device mounted on the general-purpose tray taken out from the test apparatus using this stored information is not classified. To be classified according to the results. By the semiconductor device testing apparatus according to claim. A semiconductor device test apparatus having a test apparatus section and a handler section, and a storage information storage means, conveying the semiconductor device under test to the test section of the handler section, and placing the semiconductor device in a test head of the test apparatus section disposed in the test section. The electrical contact is tested for operation of the semiconductor device, and after completion of the test, the tested semiconductor device is taken out from the test part to the unloader part of the handler part, and the test semiconductor device is stacked on the general purpose tray in the unloader part, A semiconductor device testing apparatus configured to take out a general-purpose tray carrying a tested semiconductor device from a handler, In the unloader section, only the operation of classifying the tested semiconductor device into two kinds of good and bad products is carried out, and the tested semiconductor devices are transferred to the general purpose trays of the corresponding divisions, respectively, and taken out from the test apparatus. In each of the above-mentioned general purpose trays, the storing information of each semiconductor device stored in the semiconductor device storage section is stored in the storing information storage means, and stored in the storing information storage means corresponding to each of the general purpose trays. A semiconductor device testing apparatus characterized in that the tested semiconductor device accommodated in each of the general purpose trays can be classified in more detail according to the test result using the information. A plurality of semiconductor device test apparatuses including a test device section and a handler section are provided, and each semiconductor device test apparatus includes a semiconductor device under test mounted in a test tray and returned to the test section of the handler section, and the test apparatus section disposed in the test section. Test the operation of the semiconductor device by electrically contacting the semiconductor device with a test head of the test head, and after completion of the test, a test tray equipped with the tested semiconductor device is taken out of the test section to the unloader section of the handler section. The semiconductor device testing apparatus is configured to classify the tested semiconductor device into two categories, good and bad, according to the test results thereof, and to transfer and store the semiconductor device in the semiconductor device storage unit of the general-purpose tray of the corresponding category from the test tray. In A semiconductor device characterized in that the test conditions of the plurality of semiconductor device test apparatuses are set to be different from each other, and a general-purpose tray equipped with only good quality and determined semiconductor devices in each of the test apparatuses is supplied to the next semiconductor device test apparatus. Test equipment. 4. The semiconductor device testing apparatus according to claim 3, wherein each of the semiconductor device testing apparatuses includes storage information storage means, and the storage information storage means includes a test result of each semiconductor device stored in the semiconductor device storage portion of the general-purpose tray. Storing the storage information of each semiconductor device including at least the assigned number and the socket number used in the test section, and after all the tests have been completed, using the storage information stored in the respective storage information storage means, And a test semiconductor device mounted on a general-purpose tray taken out from the test apparatus so as to be classified in more detail according to the test result. A semiconductor device test system provided with a plurality of semiconductor device test apparatuses according to claim 1, wherein the storage information storage means is provided in common in each test apparatus, and the plurality of semiconductor device test apparatuses have the same test conditions. The semiconductor device under test is supplied in parallel to each of the plurality of semiconductor device test apparatuses, the storage information of each test apparatus is stored in the storage information storage means, and the tested semiconductor devices are mounted without being classified. A universal tray is taken out from these test apparatuses, and the storage information of the semiconductor device mounted in the tray is taken out from the storage information storage means corresponding to each general purpose tray. According to the storage information, the processing including the fine classification can be further received. A semiconductor device test system, characterized in that is configured to. A semiconductor device test system comprising a plurality of semiconductor device test apparatuses as set forth in claim 2, wherein said storage information storage means is provided in common in each test apparatus, and said plurality of semiconductor device test apparatuses set different test conditions. The semiconductor device which is set to have, and supplies only the general-purpose tray corresponding to the good product in each said test apparatus to the next semiconductor device test apparatus, and is mounted in the general-purpose tray corresponding to the good product from the last test apparatus, and is taken out A semiconductor device test system, characterized in that it is configured to further receive a process including fine classification by using the storage information stored in the information storage means. The semiconductor device testing apparatus according to claim 3, wherein each of the semiconductor device test apparatuses has storage information storage means, and each of the storage information storage means stores the storage information of each semiconductor device obtained from the test apparatus in each of the general purpose trays. After all the tests by a large test apparatus are finished, the tested semiconductor device mounted on the general purpose tray corresponding to the good product from the last test apparatus can be classified in more detail according to the storage information of the plurality of test apparatuses. The semiconductor device test apparatus characterized by the above-mentioned.

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