KR100295113B1 - Field emission display and its spacer manufacturing method - Google Patents

Abstract

The present invention relates to a field emission display having a spacer which serves to maintain a constant gap between the upper and lower plates, and a method of manufacturing the spacer.

The FED of the present invention is characterized in that it comprises a spacer structure having a predetermined height and a hole formed in a predetermined unit between the negative electrode plate and the positive electrode plate disposed to face each other.

According to the present invention, by fabricating an integrated spacer structure using photosensitive glass, it is possible to solve the misalignment problem of existing individual spacers and to minimize the cracking of the substrate glass by dispersing the high stress applied to the individual spacers throughout the spacer structure. It becomes possible.

Description

Field Emission Display and Fabrication Methods Of Its Spacer

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a field emission display, and more particularly, to a field emission display having a spacer which serves to maintain a constant gap between the upper and lower plates, and a method of manufacturing the same.

Today, with the development of multimedia, the interest and importance of the display (Dispaly) play an important role is increasing. In response to this, various flat panel displays, such as liquid crystal displays (LCDs) and plasma display panels (PDPs), have been developed and put into practical use. However, they have not yet achieved a satisfactory display in terms of viewing angle, high-speed response, high brightness, high definition, power consumption, and thinness. Currently, except for problems such as thinness, weight, and power consumption, cathode ray tube (CRT) This is close to the ideal display.

In recent years, field emission displays (hereinafter referred to as FEDs), which are attracting attention as next-generation displays, use phosphor emission by electron beams similarly to cathode ray tubes (CRTs). Accordingly, the FED is likely to be implemented as a flat panel display having low power consumption without distortion of the image while maintaining excellent characteristics of the cathode ray tube (CRT).

In general, the FED is a triode, like a conventional vacuum tube, but concentrates a high electric field on a sharp cathode, that is, an emitter, without using a hot cathode. The cold cathode which emits is used. The electrons emitted from the emitter are accelerated by the voltage applied between the anode and the cathode and collide with the phosphor film formed on the anode to emit the phosphor. In other words, it is the same principle as the cathode ray tube (CRT) in that the phosphor emits light by electron collision.

1 and 2 are a cross-sectional view and a perspective view showing the basic structure of the FED, the FED shown in Figures 1 and 2 is a vacuum between the positive electrode plate 28 and the negative electrode plate 20, the positive electrode plate 28 and the negative electrode plate 20 A spacer 30 is provided to keep the space 32.

In the FED shown in FIGS. 1 and 2, the negative electrode plate 20 is disposed on the lower glass 10, the negative electrode 12 and the emitter 14 stacked thereon, and the negative electrode 12 around the emitter 14. A laminated insulating layer 16 and a gate electrode 18 are provided. The anode plate 28 includes an upper glass 22, an anode 24 and a phosphor 26 stacked below. In addition, the vacuum space 32 provided by the spacer 30 between the positive electrode plate 28 and the negative electrode plate 20 maintains a high vacuum state. In the FED of this structure, the tip-shaped emitters 14 emit electrons 34 into the vacuum 32 by a high electric field formed by a voltage applied to the cathode 12 and the gate electrode 18. Thus, the electrons 34 emitted from the emitter 14 are accelerated by the voltage applied between the cathode 12 and the anode 24, and red (R) and rust (G) applied to the surface of the anode 24. ), The visible light is emitted by colliding with the blue (B) phosphor 26 to emit light. Thus, the FED shown in FIGS. 1 and 2 has a driving voltage of about 400 to 1000 V across the anode 24 and a low voltage type FED in which the distance between the cathode plate 28 and the anode plate 20 is set to about 200 to 500 μm. to be.

Referring to Figure 3, a cross-sectional view of a high voltage type FED is shown.

In the high voltage type FED shown in FIG. 3, unlike the low voltage type FED shown in FIGS. 1 and 2, the phosphor 26 is first applied to the upper glass 22, and the anode 24 is formed on the phosphor 26. . This structure is the same as the electrode structure of the fluorescent surface of the current cathode ray tube (CRT). In addition, since the high voltage type FED applies a high voltage of 3 to 10 kV to the anode 24 in order to use the high voltage phosphor 26, the distance between the positive electrode plate 28 and the negative electrode plate 20 should be set larger than that of the low voltage type FED. . For example, the gap between the positive electrode plate 28 and the negative electrode plate 20 should be maintained at least 1 mm. In this case, the role of the spacer 30 supporting the positive electrode plate 28 and the negative electrode plate 20 becomes more important. For this purpose, the spacer 30 must have a larger ratio of width to height and a mechanical strength to withstand stress must also be increased. In addition, in the high voltage type FED, the structure of the lower glass 10, the cathode 12, the emitter 14, the insulating layer 16, and the gate electrode 18 in the negative electrode plate 20 is the same as that of the low voltage type FED, but the positive electrode plate 28 ) And a focusing electrode 36 is further provided to prevent the spread of the electron beam due to the increase in the distance between the cathode plate 20 and the cathode plate 20. The focusing electrode 36 is formed on the gate electrode 18 and has been proposed in a variety of forms, such as the case of forming the emitter unit and the case of the subpixel unit as shown in FIG. 3.

One of the important components of the FED spacer 30 is a glass substrate (so that the space between the panel consisting of thin glass substrates 10 and 22 maintains a high vacuum state ranging from 10 ^-6 to 10 ^-7 Torr). 10, 22) should be able to be supported so as not to bend or break. In addition, the spacer 30 should have a strong mechanical strength so that even if the screen is wide, the glass substrates 10 and 22 may be supported even without thickening. In addition, a width smaller than the space between the pixel and the pixel should be maintained so that the presence of the spacer 30 does not block the path of the electron beam, and even if the emitted electron beam collides with the spacer 30 in a portion close to the anode plate 28. Material designs that do not accumulate space charge must also be considered.

In addition, the height of the spacer 30 is set to be similar to the pixel pitch. As shown in FIGS. 1 and 2, in the case of a low voltage type FED using low voltage phosphors, the height of the spacer 30 is about 200 to 400 μm, which is relatively easy to manufacture. In the case of the high voltage type FED using the focusing electrode 36 as shown in FIG. 1, the ratio of the width-to-height ratio must be further increased because the distance between the cathode 12 and the anode 24 exceeds 1000 μm. This will follow. Looking at the material aspect, the material of the spacer 30 currently used mainly is glass, ceramic, insulating metal, etc. In the case of high voltage FED, in addition to the above three essential conditions, additional conditions that must withstand high pressure are required. Done. In addition, an insulation coating process is additionally required to prevent charges from accumulating in the periphery of the spacer 30, and there are difficult conditions to withstand high pressure breakdown.

As such, the spacer of the FED should be selected to satisfy the above requirements simultaneously. The most widely used method so far in form is a post type spacer 30 as shown in FIGS. 4 and 5. )to be.

4 and 5 are a perspective view and a cross-sectional view for explaining a method for manufacturing a FED with a spacer 30 of a low voltage type FED.

In FIGS. 4 and 5, the spacer 30 is manufactured to be thin and long in the form of a post using glass or a ceramic compound. The spacer 30 manufactured as described above is installed in the groove 42 of a line shape provided between the black matrix 40 formed to secure the contrast in the positive electrode plate 28. 4 and 5, the anode plate 28 includes an anode 24 formed on the upper glass 22, red (R), green (G) and blue (B) phosphors 26 formed on the anode 24, and The chromium (Cr) layer 38 formed between the phosphors 26 and the black matrix 40 formed on the chromium layer 38 so as to surround the phosphor 26 are comprised. The spacer 30 is arranged in the groove 34 provided between the black matrix 40 in units of pixels, and then the alignment is performed by aligning the positive electrode 28 and the negative electrode 26 shown in FIGS. 1 and 2. Done.

However, since the post-shaped spacer 30 is not sufficiently mechanical in strength, a shake phenomenon occurs in each of the spacers 30 as shown in FIG. 5, and thus the alignment is not accurately aligned. In addition, since the post-type spacers 30 are to be disposed separately, there is a disadvantage in that the mass production yield is low because of the large number of processes.

In addition, the spacer 30 applied to the high voltage type FED has to have an aspect ratio of the width-to-height higher than that of the low-voltage type, and it is difficult to secure mechanical strength with the glass post, and the ratio of the width-to-height ratio is high. ) Is not easy to implement.

To this end, US Patent Nos. 5,532,548 and 5,424,605 disclose a method of vertically standing a plate by processing a ceramic plate (Ceramic Plate) as shown in Figs.

6 and 7 show a plate type spacer 44 installed in a high voltage FED.

In the high voltage type FED shown in FIGS. 6 and 7, the positive electrode plate 28 includes red, green, and blue phosphors 26 formed on the upper glass 22, a chromium layer 38 formed between the phosphors 26, and a phosphor. The black matrix 40 formed on the chromium layer 38 so as to surround the 26 and the anode 22 coated on the phosphor 26 and the black matrix 40 are constituted. After the plate-type spacers 44 are installed in the grooves provided between the black matrices 40 of the positive electrode plate 28 having such a structure, the positive electrode plate 28 and the negative electrode plate 20 shown in FIG. 3 are aligned and bonded. .

By the way, this plate-type spacer 44, as shown in Fig. 7, also occurs in each of the shake does not occur correctly occurs.

As described above, the spacers 30 and 44 described above all have a non-integrated structure, so that the vulnerability of self-supporting can be pointed out, and the negative electrode plate 20 and the positive electrode plate (in packaging) can be pointed out. 28) There is a problem that is likely to cause inaccurate alignment in between. Furthermore, as the FED becomes larger and larger, the above-mentioned problems are more serious, and thus there is a problem that it is very disadvantageous in terms of production and mass production.

Accordingly, an object of the present invention is to provide a FED and a method for manufacturing the spacer thereof, which can prevent misalignment by integrally manufacturing the spacer using photosensitive glass.

Another object of the present invention is to fabricate the spacers integrally using photosensitive glass, thereby dispersing the high stress applied to the spacers over the entire width of the spacer wall to minimize the cracking of the glass substrate. To provide.

1 is a cross-sectional view showing the basic structure of a conventional low voltage type field emission display.

2 is a perspective view showing the basic structure of a conventional low voltage type field emission display.

3 is a cross-sectional view showing the basic structure of a conventional high voltage type field emission display.

4 is a view showing a spacer for a conventional low voltage type field emission display.

FIG. 5 is a view illustrating a shaking phenomenon of the spacer illustrated in FIG. 4. FIG.

Figure 6 is a view showing a spacer for a conventional high voltage type field emission display.

FIG. 7 is a view illustrating a shaking phenomenon of the spacer illustrated in FIG. 6.

8A to 8F are views showing step by step a spacer manufacturing method for a field emission display according to an embodiment of the present invention.

9 is a perspective view showing a field emission display applied to the spacer according to an embodiment of the present invention.

<Brief description of symbols for the main parts of the drawings>

10: lower glass 12: cathode

14 emitter 16 insulating layer

18 gate electrode 20 negative electrode plate

22: upper glass 24: anode

26 phosphor 28 anode plate

30, 44: spacer 32: vacuum space

34: electron beam 36: focusing electrode

38: chromium layer 40: black matrix

42: groove 46: photosensitive glass

48: first mask pattern 50: ultraviolet

52, 62: crystallization portion 54: primary spacer structure

56 pixel hole 58 opening

60: second mask pattern 64: connection groove

66: secondary spacer structure 68: getter

In order to achieve the above objects, the FED according to the present invention is characterized in that it comprises a spacer structure having a predetermined height and integrally formed between the negative electrode plate and the positive electrode plate disposed to face each other and provided with holes in a predetermined unit.

According to the present invention, there is provided a method of manufacturing a FED spacer using a first mask pattern and a photolithography process on a photosensitive glass substrate, and a second mask pattern and a photolithography process on a photosensitive glass substrate having a hole. It characterized in that it comprises the step of providing a connection groove for connecting the holes spatially.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 8A to 9.

8A through 8F are diagrams illustrating a method of manufacturing a spacer for an FED according to an embodiment of the present invention in stages.

Referring to FIG. 8A, there is shown a photosensitive glass 46 and a mask pattern 48 disposed thereon. First, after preparing the photosensitive glass 46 for forming the spacer structure, a mask pattern 48 made of chromium (Cr) material having an opening having a desired shape is disposed on the photosensitive glass 46. Next, the photosensitive glass 46 is exposed to the ultraviolet ray 50 through the mask pattern 48. In general, the wavelength of the ultraviolet ray 50 is about 280nm to 340nm, and the thickness of the photosensitive glass 46 which can be exposed to the commercial ultraviolet ray 50 can be applied to most FED spacers because the thickness of the photosensitive glass 46 is currently about 2mm. have.

The photosensitive glass 46 is then heat treated to cause the portion 52 exposed to the ultraviolet light 50 to crystallize, as shown in FIG. 8B. In other words, after the above-described ultraviolet exposure process is completed, the mask pattern 48 is removed and the photosensitive glass 46 is heat-treated at 400 ° C to 500 ° C for crystallization of the surface of the photosensitive glass 46 irradiated with the ultraviolet light 50. . Accordingly, in the photosensitive glass 46, agglomeration of silver (Ag) atoms formed in the exposed portion 52 upon exposure to ultraviolet rays is formed, and the high-temperature crystals having a diameter of 1 to 10 μm are formed on the portion 52 where the atomic nucleus is located. Will be formed.

Subsequently, the crystallized portion 52 is etched to form a primary spacer structure 54 in which holes in pixels (hereinafter referred to as pixel holes) 56 are provided as shown in FIG. 8C. The pixel holes 56 in this primary spacer structure 54 are formed by fully etching the crystallized portion 52 shown in FIG. 8B with HF 10% solution at room temperature.

In general, the FED is important to maintain the vacuum inside the panel because the inside of the panel has a characteristic of operating normally only at a high vacuum of at least 10 ^-6 Torr. Here, the vacuum degree of 10 ^-6 Torr is a criterion for indicating the average vacuum degree in the macroscopic panel, and the vacuum degree around one sub-pixel, which is actually formed by a large number of emitters, becomes a more important vacuum element. Therefore, as shown in FIG. 8C, when the primary spacer structure 54, which is a film in all directions, is used as a spacer, an initial vacuum cannot be maintained and a passage connected to the entire panel must be provided. The vacuum degree can be maintained by the discharge action of the getter to be installed near the edge. To this end, it is necessary to further form a passage (hereinafter referred to as a connecting groove) for spatially connecting the pixel holes 56 in the primary spacer structure 54.

Referring to FIG. 8D, a second mask pattern 60 for forming connection grooves is disposed on the primary spacer structure 54. The second mask pattern 60 is for forming a connection groove for spatially connecting the pixel holes 56 provided in the primary spacer structure 54. The opening 58 formed in the second mask pattern 60 is formed. The spacer structure 54 is aligned with the middle portion of the wall to be disposed on the spacer structure 54. Subsequently, the ultraviolet rays 50 are irradiated to the lower spacer structure 54 through the openings 58 of the second mask pattern 60.

Subsequently, after removing the second mask pattern 60, as shown in FIG. 8E, the primary spacer structure 54 is heat-treated to crystallize the portion 62 irradiated with ultraviolet rays.

The crystallized portion 62 is etched to complete the secondary spacer structure 66 having the connection grooves 64 for spatially connecting the pixel holes 56 pixel by pixel as shown in FIG. 8F. The connecting groove 64 is formed by etching the photosensitive glass, that is, about 50% of the thickness of the spacer structure 54 by calculating a condition that the photosensitive glass is not completely etched through the etching ratio determined during the above-described primary etching. do.

In the first and second etching processes for forming the pixel hole 56 and the connection groove 64, the pixel hole 56 may be formed in a unit size or a width including a plurality of sub-pixels. In other words, the width of the pixel hole 56 is the contact area between the secondary spacer structure 66 and the glass substrate according to the calculation of the stress distribution between the spacer structure 66 and the upper and lower glass substrates, that is, the secondary spacer structure ( 66) Since the width of the wall (w) can be set to the minimum size that can withstand the stress, the larger the size, the more advantageous the residual gas discharge in terms of the stress-bearing condition.

And, as shown in FIG. 9, the final spacer structure 66 is disposed between the anode plate 28 and the cathode plate 20 prepared in advance by a separate process to be bonded after undergoing an alignment process to complete the FED panel. . In this case, the getter 68 which absorbs the gas component remaining in the inner space and maintains a high vacuum state is disposed in a direction perpendicular to the connection grooves 64 in the negative electrode plate 20.

As described above, according to the FED according to the present invention and the method for manufacturing the spacer, by fabricating an integrated spacer structure using photosensitive glass, while solving the problem of misalignment of the existing individual spacers and at the same time the high stress applied to the individual spacers By dispersing throughout the structure, cracking of the substrate glass can be minimized. In addition, according to the FED and the spacer manufacturing method according to the present invention by producing an integral spacer structure, the time required to align all the spacers and to significantly reduce the time required for bonding the upper plate and the lower plate when manufacturing the panel mass production process The effect is to increase the yield significantly.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (6)

An electric field emission display comprising a spacer structure having a predetermined height between the cathode plates and the anode plates disposed to face each other and integrally formed with holes in predetermined units. The method of claim 1, The focusing structure is a field emission display, characterized in that the material is photosensitive glass. The method of claim 1, The negative plate is A cathode formed on the first substrate, An emitter formed on the cathode to emit electrons; A gate electrode controlling an electron emission amount of the emitter unit; And an insulating film for insulating the gate electrode and the emitter portion. The method of claim 3, wherein The negative plate is And a focusing electrode for focusing the electron beam emitted from the emitter. The method of claim 1, The positive plate is A second substrate disposed to face the first substrate, An anode for accelerating the electron beam emitted from the emitter, And a phosphor for emitting visible light by the collision of the electron beam. Preparing holes in the photosensitive glass substrate by using a first mask pattern and a photolithography process; And forming a connection groove in the photosensitive glass substrate provided with the hole using a second mask pattern and a photolithography process to spatially connect the holes.