KR100293362B1 - Reception and interface device of multiple tdm channels and method for the same - Google Patents

Abstract

PURPOSE: A reception and interface device of multiple TDM(Time Division Multiplexing) channels and a method for the same are provided to store reception data of each channel for multiple channels into each FIFO and process received data by using a serial communication controller. CONSTITUTION: A signal generation control portion(10) transmits recording signals(/ffwr0 to /ffwr31) to 32 FIFOs(11) through a data bus of 8 bits when receiving a data signal, a clock signal, and a frame synchronization signal through a TDM bus(13). The FIFOs(11) store the received recoding signals(/ffwr0 to /ffwr31) according to each channel of the TDM bus and transmits data to a serial communication controller(12) through the data bus of 8 bits. The FIFOs(11) generates signals(level0 to level31) for indicating a storing state of data and outputs the generated signals(level0 to level31) to the serial communication controller(12).

Description

Apparatus and method for simultaneous reception of multiple T D M channels

The present invention relates to a reception (Rx) simultaneous matching device and method for a plurality of time division multiplexing (TDM) channels, and more particularly, to transmit (Tx) a plurality of channels operated by a TDM scheme. In matching, one SCC (Serial Communication Controller) stores data to be transmitted for each channel in a plurality of first-in first-out (FIFO) and then sequentially one byte at each FIFO. The present invention relates to an apparatus and a method for concurrently receiving a plurality of time division multiple access channels received on a TDM bus.

Communication between different boards or systems such as the upper processor and lower processor of the control system of the electronic switchgear performs serial communication. There are various protocols for serial communication, one of which is HDLC (High Level Data Link Control). Protocol. The data frame exchanged between two systems by this HLDC protocol consists of a flag, valid data, and a cyclic redundancy code (CRC). The flag is used to indicate the beginning and the writing of the data frame. The SCC generally uses 16 to 32 bits as part to insert into the frame to check for. In the idle state without valid data, logic 1 is continuously transmitted, and when the CPU transmits valid data to be sent to the SCC, the SCC serves to make and transmit the data frame. In addition, when receiving a data frame, it detects the flag pattern from the bitstream received from the communication line, detects the beginning and the writing of the frame, and sends only valid data to the CPU.

The TDM bus is a multiple access bus divided into 32 time slots. Each time slot corresponds to one channel, and the serial communication of the SCC can be performed using one time slot.

In the prior art, in order to implement serial communication by HLDC protocol of several channels, each time slot (ie, channel) has a status of idle, valid data, and a flag. Therefore, each channel has to be connected to an SCC.

That is, in the prior art, when matching multiple channels and SCCs operated by the TDM method, one independent SCC is matched for each channel. Therefore, in order to match a plurality of channels, there is a problem that a plurality of channels, that is, as many SCCs as channels are required.

The present invention has been made under the above-mentioned background. In the transmission of data between systems of an electronic switching system, the received (Rx) data of each channel is stored in each first-in first-out buffer (FIFO) for a plurality of channels. It is an object of the present invention to provide an apparatus and method for receiving simultaneous matching of a time division multiple access (TDM) channel capable of receiving and matching a plurality of channels by sequentially processing received data.

1 shows that each time slot of a TDM bus is stored in a receive FIFO,

2 is a block diagram for realizing simultaneous reception of multiple TDM channels according to the present invention;

FIG. 3 is a flowchart in which each time slot of a TDM bus is recorded in each FIFO by the controller of FIG.

4 is a flowchart of processing data by inspecting each FIFO in a serial communication controller (SCC).

* Explanation of symbols for main parts of the drawings

10 control unit 11 FIFO

12: SCC 13: TDM Bus

In order to achieve the above object, the reception co-matching apparatus of a plurality of TDM channels of the present invention may be applied to any communication protocol such as high level data link control (HLDC) between each system such as an upper processor and a lower processor of an electronic switching system. In the RX simultaneous matching device for transmitting and receiving data, receiving 8-bit data signal, clock signal and frame synchronization signal from another system through TDM bus having 32 time slots. A control unit for generating a signal for recording data of each time slot, 32 first-in first-out buffers (FIFOs) for storing and outputting data received by the recording signal generated by the control unit in order of input, and from each of the first-in first-out buffers A serial communication controller (SCC) that reads and processes data for each time slot is provided for simultaneous reception of TDM channels. It provides a reception simultaneous matching device of a plurality of TDM channels, characterized in that.

In this case, an 8-bit data bus is used to transfer data between the control unit and each FIFO, and an 8-bit data bus is used to transfer data between the FIFO and the SCC.

In addition, the FIFO is characterized by generating a level signal indicating that the data is stored above a certain level.

In addition, the reception co-matching apparatus of a plurality of TDM channels of the present invention transmits and receives data by an arbitrary communication protocol such as high level data link control (HLDC) between each system such as an upper processor and a lower processor of an electronic switch. In the RX simultaneous matching method, an arbitrary 8-bit data signal, a clock signal, and a frame synchronization signal are received from another system through a TDM bus having 32 time slots, and data of each time slot is recorded. Generating a signal, and transitioning to a time slot used as signaling by a frame synchronization signal in the event of a data failure; Storing and outputting the data received by the recording signal in the order of input and processing the data when the data is stored at a predetermined level by reading the output data for each time slot. Provides a simultaneous matching method of reception.

DETAILED DESCRIPTION Hereinafter, an apparatus and method for receiving simultaneous matching of multiple TDM channels will be described in detail with reference to the accompanying drawings.

1 shows that each time slot of a TDM bus is stored in a reception FIFO. As shown, the TDM bus is composed of 32 time slots, which form one data frame. Slot 0 is not used as a channel but as signaling. The start of the frame is indicated by the frame sync pulse.

The serial communication controller (SCC) sequentially checks each received FIFO, and if there is data, processes the data by the HLDC protocol and then processes the next FIFO and performs data processing.

2 is a block diagram for realizing a reception simultaneous matching method for multiple TDM channels according to the present invention.

The block diagram shown in FIG. 2 receives a random 8-bit data signal, a clock signal, and a frame synchronization signal from another system via a TDM bus having 32 time slots to generate a signal for recording data of each time slot. The signal generation control unit 10, 32 first-in first-out buffers (FIFO) 11 for storing and outputting data received by the recording signals generated by the control unit 10 in order of inputting, and data from each of the first-in first-out buffers. A serial communication controller (SCC) 12 reads and processes slot by slot.

The operation of simultaneous reception of TDM channels according to the present invention will be described with reference to FIG. 2.

When the signal generation control unit 10 receives the data signal, the clock signal and the frame pulse, that is, the frame synchronization signal through the TDM bus 13, the control unit 10 transmits an 8-bit data bus (FIFO) to the 32 FIFOs 11 at the rear end. -lN [7 ... 0]) transmits the recording signal (/ ffwr0- / ffwr31). Then, each of the 32 FIFOs 11 sequentially stores the recording signals / ffwr0- / ffwr31 for each channel of the TDM bus, and sends the FIFO 11 to the serial communication controller (SCC) 12 behind the FIFO 11. Data is transferred via an 8-bit data bus (FIFO-OUT [7 ... 0]). The controller 10 reads and processes data by a signal (/ ffrd0- / ffrd31) for reading data from the respective FIFOs 11.

The 32 FIFOs 11 generate the signal level 0-level 31 indicating that the data is stored above a certain level, and output the signal to the SCC 12. Then, the SCC 12 processes the data only when data is stored in the FIFO 11 by a level-level31 signal at a predetermined level or more. 3 is a flowchart in which the control unit records each timeslot of the TDM bus, that is, data of each channel in each FIFO, and sequentially records data in each FIFO 11 from timeslot 0 to timeslot 31. Is showing.

However, when a failure such as a data recording failure occurs, the sequential recording is interrupted by the frame synchronizing signal and the time slot 0 is shifted.

4 is a flowchart of processing data by inspecting each FIFO in a serial communication controller. The SCC 12 sequentially checks 32 FIFOs 11 and stores a predetermined amount or more of data in each FIFO 11. Only shows processing data.

According to the apparatus and method for simultaneous reception of a plurality of TDM channels according to the present invention as described above, in receiving and matching a plurality of channels operated by a TDM method, data of each channel is stored in each FIFO, and then one serial communication controller By (SCC) processing the data of each FIFO in sequence, it is possible to achieve cost reduction by receiving and matching a plurality of channels.

So far, the TDM channel reception simultaneous matching method of the present invention has been described, but the present invention is not limited thereto, and various modifications and variations are made by those skilled in the art without departing from the spirit and scope of the appended claims. Of course, it can be carried out.

Claims (3)

Receiving (Rx) simultaneous matching device of a plurality of TDM channels to send and receive data between each system of the upper processor and lower processor of the switchboard, Signal generation control unit for receiving arbitrary 8-bit data signals, clock signals, and frame synchronization signals from other systems through a TDM bus having 32 time slots and generating a signal for recording data of each time slot; 32 first-in first-out buffers (FIFO) for storing the data received by the recorded signal of the received signal in the input order and generating and outputting a level signal indicating that the data has been stored above a predetermined level, and each first-in first-out buffer And a serial communication controller (SCC) for reading and processing data from each slot by time slots for simultaneous reception of TDM channels. The plurality of TDM channels of claim 1, wherein the signal generation controller and each FIFO are transferred using an 8-bit data bus, and the FIFO and the SCC are transferred using an 8-bit data bus. Receive simultaneous matching device. In the simultaneous matching (Rx) of a plurality of TDM channels in which data is transmitted and received by an arbitrary communication protocol between the upper processor of the switchboard and the lower processor, Receive arbitrary 8-bit data signal, clock signal, and frame synchronization signal from other system through TDM bus with 32 time slots and generate signal to record data of each time slot, but frame synchronization in case of data failure Transitioning to a time slot used as signaling by a signal; Storing data received by the recording signal in an input order and generating and outputting a level signal indicating that the data has been stored above a predetermined level; And, And receiving the output data for each time slot and processing the data when a predetermined level of data is stored.

Images