KR100293256B1 - A fast lock on time mixed mode delay locked loop with low jitter - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronizing circuit having fast clock synchronizing time and small jitter. More specifically, the present invention relates to analog circuits of conventional delay locked loop (DLL), phase locked loop (PLL), and delay line (DL). It is a mixed mode DLL (Mixed Mode DLL) consisting of analog voltage controlled delay line (VCDL) and digital fixed delay line (FDL) to have all the advantages of digital circuit. To do this, the large phase difference between the internal clock and the external clock is initially reduced by only two clock cycles by the FDL, and the clock is synchronized once, and for the remaining phase difference, the delay time of the analog VCDL is changed slightly so that the clock can be changed quickly. Configured to be fully synchronized, it has faster clock sync times and more improved jitter than traditional methods. Power, yet can be employed in place that requires a high-speed clock of the interface that can be useful for chips that require high-speed data transmission.

Description

A fast lock on time mixed mode delay locked loop with low jitter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronization circuit, and in particular, has a fast clock synchronization time and a further improved small jitter characteristic so that a fast clock can be used for a chip requiring low power and high speed data transmission. A mixed mode delay locked loop has a synchronization time and a small jitter characteristic.

In general, when a system is implemented on a printed circuit board (PCB), in order to improve the performance of the overall system, designers usually implement a synchronous system by applying a clock signal to each chip in common. At this time, since all data is transmitted and received in synchronization with the clock signal, the clock must be operated quickly while transmitting and receiving data stably in order to increase the speed of the system.

However, until now, the clock has been commonly applied to all chips from a crystal oscillator, and data transmission time and various skews make it difficult to speed up the clock.

In a clock synchronization system, when an external clock enters an integrated circuit, it is generated as an internal clock to be used internally through a clock buffer and a clock driver. In this case, due to the delay between the buffer and the driver, the internal clock does not coincide with the external clock. Due to such unnecessary clock skew, it is difficult to speed up the entire system clock. Recently, an integrated circuit having a high speed interface has added a circuit for synchronizing an external clock with an internal clock.

Therefore, in order to use a high speed clock, recently, a circuit for synchronizing an external clock and an internal clock is integrated in a chip to eliminate skew in the chip, or by simultaneously transmitting clock and data using a clock synchronization circuit. Data is transmitted at high speed by eliminating skew between data.

Such clock synchronization circuits include a phase locked loop (PLL), a delay locked loop (DLL), and a delay line (Delay Line) method, which can be classified into digital and analog methods. Can be.

The analog method is a closed loop clock synchronous circuit that allows the clock to be synchronized by varying the delay time of the delay cells by control. Examples of the analog method include a PLL and a DLL, and the digital method is an open loop. A delay line etc. are mentioned as a circuit using the unit delay cell which fixed the delay time as a clock synchronization circuit.

On the other hand, the analog method such as DLL has a long time for synchronizing the clock, but because it is implemented using the analog method, it has a good jitter characteristic and is used for a very high speed interface application recently. In brief, the phase detector compares a phase difference between an external clock and an internal clock, and compares a signal corresponding to a comparison result, for example, a rising (leading) pulse signal or a falling (delay) corresponding to the leading / delay level of two clock signals. ) Generates a pulse signal. Then, this signal is converted into a voltage signal through a charge pump (CP), and a control signal for generating a variable delay time by extracting a DC component through a loop filter (LP) is generated. A voltage controlled delay line (VCDL) is generated as an internal clock by adjusting the delay time of the external clock by a control signal.This feedback operation continuously compares the external clock with the internal clock and continuously controls the corresponding phase difference. Change the signal This closed loop operation, however, lengthens the clock synchronization by hundreds of clock cycles. At this time, in order to reduce the synchronization time due to the loop characteristics, the gain of the loop is increased inversely so that the delay time can be changed quickly. This causes the internal clock to shake because of the large loop gain, even if the clock is synchronized, resulting in poor jitter.

Therefore, the conventional analog method can control the jitter finely through the loop, so it is often used where a high speed interface of 400 MHz or more is required, but the clock synchronization time is too long, and the performance of the circuit is that of the clock. Since there is a relationship between the synchronization time and the jitter, if the gain of the loop is increased to increase the synchronization time, there is a problem that the jitter may increase.

On the other hand, there are various digital methods. When a typical synchronous mirror delay (SMD) operation is performed, when a rising edge of an external clock is input, a time to digital converter (TDC) delay array is performed. Then, at the next rising edge, you can see the distance that the rising edge of the first clock travels through the TDC. When the distance is transmitted to the DTC (Digital to Time Converter), the delay time from the external clock to the internal clock is coincided with the clock period, and the clock is synchronized.

Therefore, digital systems usually have fast synchronization times of two to three clock cycles and are therefore used in present-day synchronous dynamic RAMs (SDRAMs) with low power modes. However, the digital method has a relatively big disadvantage because the phase difference between the external clock and the internal clock is dependent on the manufacturing process.

Accordingly, the present invention is to implement a clock synchronizing circuit having a faster clock synchronizing time and better jitter characteristics by employing both the analog and digital clock synchronizing circuits described above.

An object of the present invention for solving the above problems is integrated into the chip to configure the entire structure of an analog circuit having a digital circuit portion and a small jitter characteristics to first synchronize the fast clock and then drive the analog circuit again fine The present invention provides a mixed mode clock synchronizing circuit having a fast clock synchronizing time and a small jitter characteristic to enable a control to perform a high speed interface between an SDRAM or a chip.

1 is a block diagram of a mixed mode clock synchronization circuit (Mixed Mode DLL) according to the present invention.

FIG. 2 is an analog voltage controlled delay line (VCDL) circuit diagram of FIG. 1. FIG.

3 is a simulation waveform diagram of VCDL.

FIG. 4 is a digital fixed delay line (FDL) circuit diagram of FIG. 1. FIG.

5 is a timing diagram of a mixed mode clock synchronization circuit in accordance with the present invention.

FIG. 6 is a graph illustrating simulation results of initial phase difference and a synchronous cycle according to the type of a fixed delay cell (FDC) of FIG. 4. FIG.

7 is a graph of simulation results of jitter and static phase difference with respect to frequency.

8 is a simulated waveform diagram at 200 MHz.

The mixed mode clock synchronizing circuit having a fast clock synchronizing time and a small jitter characteristic according to the present invention for achieving the above object consists of an analog circuit having a digital circuit portion and a low jitter characteristic, After synchronization, the analog circuit is driven again to perform fine control.

The above objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a mixed delay clock locked circuit (Mixed Delay Locked Loop) having a fast clock synchronizing time and a small jitter characteristic according to the present invention.

In the figure, the present invention comprises a voltage controlled delay line (VCDL) portion of an analog circuit portion and a fixed delay circuit (FDL) portion of a digital circuit portion.

In addition, the analog circuit part is VCDL according to the phase frequency detector (PFD), internal clock detector (ID: Internal clock detector), charge pump (CP), 1 / 2Vcc generator, loop filter, control voltage It consists of a voltage to current converter (VI) and a VCDL to deliver the desired current.

Here, before the internal clock is generated, the phase frequency detector PFD is reset by the output of the internal clock detector ID so that the phase comparison is not performed so that the charge pump CP does not operate to charge and discharge the filter. Vctl is maintained at 1/2 Vcc, and then the initial delay time is measured by the fixed delay circuit (FDL) so that the internal clock detector (ID) operates the phase frequency detector (PFD) when an internal clock is generated. do.

In other words, if the whole circuit does not operate, connect the 1 / 2Vcc generator to the loop filter to keep Vctl at 1 / 2Vcc, and if mclk occurs in the MCG of the fixed delay circuit (FDL) after the operation, The Vctl stays near 1 / 2Vcc due to delay compensation by the initial fixed delay circuit (FDL).

Meanwhile, as shown in FIG. 2, the VCDL block includes a differential voltage control delay element (Delay Cell) and a double bias circuit (Replica biasing). In the existing DLL structure, the Vctl voltage at which the clock is synchronized is difficult to predict, but in the structure according to the present invention, since the phase difference between the external clock and the internal clock that is initially synchronized in the digital circuit is small (at the initial stage, the maximum phase difference is fixed delay cell ( FDC: Fixed Delay Cell) One stage delay time.) When synchronized, the Vctl voltage is near 1 / 2Vcc.

In other words, locked in the general DLL means that the Vctl voltage of the filter does not change because the amount of charge current and discharge current of the CP is the same. However, when the phase of external clock and internal clock is synchronized, PFD's output UP and DN signals have the same phase and the same width, and if ideal, CP flowing current by UP and DN has the same charge and discharge. Must have current. However, in the existing DLL, the Vctl voltage level when the external clock and the internal clock are synchronized cannot be known. Therefore, the charge and discharge current amounts are different due to the mismatch between the V _DS voltages of the PMOS and NMOS that charge and discharge the filter. This mismatch of charge / discharge currents causes a phase difference between the external clock and the internal clock when the DLL is synchronized. Therefore, to eliminate this phenomenon, the VDS must be matched and the clock must be synchronized at 1/2 Vcc.

Therefore, the driver of the charge pump (CP) can be optimized to almost completely match the current to charge and discharge the loop filter, the capacitor between CP and V-I.

3 is a waveform diagram simulating the Vctl voltage of the present invention using the conventional DLL method using only VCDL and VCDL and FDL. As shown in the simulation results, the clock synchronization time of the existing DLL (Conv. VCDL) is approximately 0.44 μs and 40 ns in the present invention (With FDL).

Meanwhile, the FDL of the digital circuit part is composed of a replica of a clock driver, a monitor driver, a time to digital converter (TDC), and a digital to time converter (DTC) .In the initial state, the control voltage of the VCDL is 1 /. It is kept at 2Vcc and PFD is not operated by ID.

4 is a digital fixed delay line (FDL) circuit diagram showing details of TDC and DTC. A block for measuring the initial clock delay time, DFF dividing the input clock, and Measure Clock Generator (MCG) are flip-flops and mclk occurs on the rising edge of the next external clock just after the first rising edge arrives at the pclk node. do. mclk will sample the delay time measured at the TDC. The measured delay time is transferred to the DTC so that the internal clock iclk is synchronized with the external clock after two cycles of the external clock.

In this structure, mclk is generated in the MCG to measure the initial delay time at the TDC and at the same time reset the DFF so that dclk no longer proceeds after the initial delay time measurement at the delay element array of the TDC, thereby reducing power consumption. do.

Figure 5 shows a timing diagram at low frequencies of the present invention. Equation 1 below holds true at the first stage for clock synchronization.

After two cycles of external clock in the initial state, t _monitor + t _dummy + t _comp is obtained for clock synchronization. Where t _monitor is the delay time of the driver replica, t _dummy is the delay time of the dummy gates, and t _comp is the delay time compensated by the FDL for clock synchronization in the first stage. After the clock synchronizing operation by the digital circuit, the delay time t _VCDL of the _VCDL is _changed by an analog circuit for fine synchronization of the clock. t _{f / f} represents the propagation delay time of DFF and MCG in the FDL, and the internal clock iclk is synchronized and output in the second cycle of the external clock eclk, and by the digital circuit FDL until then (initial step) Vctl is kept constant, and vctl is variable as a fine fine locking process proceeds based on the operation of the analog circuit VCDL.

In order to verify the circuit, the mixed mode clock synchronization circuit according to the present invention is designed using a 0.4 μm CMOS process, and FIG. 6 shows simulation results of different types of FDC at 200 MHz.

In the FDC according to the present invention, a NOR gate and an inverter, a NAND gate and an inverter, an inverter and an inverter, and an inverter having a differential structure can be used. When a differential inverter (Differential INV) is used, the external clock and the internal stage at the first stage are used. The maximum initial phase error was the smallest and the smallest lock-on cycles by the analog circuitry.

7 is a simulation result of static phase error and jitter between an external clock and a final synchronized internal clock. As shown in the figure, the sum of the static phase difference and jitter between clocks at a 200 MHz clock frequency is about 10 ps or less, and the clock is synchronized and has a low jitter characteristic in a relatively small clock cycle.

8 is a simulation result showing the clock synchronization at a 3.3V supply voltage and a 200MHz clock frequency. The internal clock is synchronized with the external clock with a small phase difference after the second clock cycle and is fully locked and synchronized with the external clock in the seventh clock cycle.

The power consumption of the mixed mode clock synchronizing circuit according to the present invention designed is 6 mA x 3.3 V at 200 MHz. When the mixed mode clock synchronizing circuit according to the present invention operates, the TDC operates only in the first stage and does not operate thereafter, and there is no power consumption. When not in operation, the 1 / 2Vcc generator consumes about 0.4µA of small current.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

As described above, according to the present invention, since it has a faster clock synchronization time and more improved low jitter than the conventional method, it can be employed where a low power and high speed clock interface is required. There is an effect that can be usefully used for the required chip.

Claims (6)

A clock synchronizing circuit that can be used for a clock synchronizing circuit, a data recovery circuit, a clock frequency multiplier or a frequency synthesizer, etc., Phase frequency detector PFD which compares the applied external clock eclk and internal clock iclk, detects and outputs the phase difference, and converts the output signal of the phase frequency detector PFD into a voltage control signal vctl. An analog circuit portion including a charge pump CP, a loop filter, and a voltage control delay circuit VCDL for delaying and outputting an external clock eclk in accordance with the control signal vctl; Comprising a plurality of fixed unit delay cells (FDC), when the rising edge of the external clock (eclk) is input, proceeds to the Time to Digital Converter (TDC) to control the voltage at the rising edge of the next external clock (eclk) The fixed unit transmits the delay time from the external clock eclk to the clock of the voltage control delay circuit VCDL by transmitting the TDC traveling distance of the output clock of the delay circuit VCDL to a digital to time converter (DTC). A digital circuit section comprising a fixed delay circuit FDL for generating the internal clock iclk by synchronizing with a delay cell FDC, and synchronizing an initial clock using the digital circuit section. A clock synchronizing circuit having a fast clock synchronizing time and a small jitter characteristic, wherein the clock is finely synchronized using the clock. The display device of claim 1, wherein the fixed delay circuit FDL includes a clock drive for driving and outputting the output clock of the voltage control delay circuit VCDL, and an output clock of the clock drive Monitor. DFF outputs pclk by dividing dclk by 2 and MCG generates clock mclk at the second rising edge of external clock eclk based on the output clock dclk and external clock eclk. In addition, the delay time measured by the time to digital converter (TDC) by the clock mclk is transferred to the digital to time converter (DTC), so that the internal clock iclk is transferred to the external clock eclk after two cycles of the external clock eclk. Clock synchronization circuit having a fast clock synchronization time and a small jitter characteristic. The fast clock according to claim 1 or 2, wherein the fixed unit delay cell (FDC) is configured of an inverter having a differential structure, a NOR gate and an inverter, a NAND gate and an inverter, or an inverter and an inverter. Clock sync circuit with sync time and small jitter characteristics. The method of claim 2, wherein a clock mclk is generated in the MCG to measure an initial delay time in the TDC, and at the same time, the DFF is reset to stop the operation of the TDC to reduce power consumption. A clock synchronizing circuit with fast clock synchronizing time and small jitter characteristics. 3. The apparatus according to claim 1 or 2, further comprising a 1/2 Vcc generator, wherein when the whole circuit is not operated, the 1/2 Vcc generator is connected to the loop filter to divide the control signal vclk. Keep at 2 Vcc, if mclk occurs in MCG of the fixed delay circuit (FDL) after operation, disconnect the loop filter and change the control signal (vclk) by the charge pump (CP) to change the clock. A clock synchronizing circuit having fast clock synchronizing time and small jitter characteristics, wherein the synchronizing is made to operate near 1/2 Vcc by a delay time compensation action caused by an initial fixed delay. The method of claim 1, further comprising an internal clock generator ID for detecting the generated internal clock iclk, so that the phase frequency comparator PFD does not operate until the internal clock iclk is generated. To prevent the charge pump CP from charging and discharging the loop filter so that the control signal vctl is maintained at 1/2 Vcc, and then the initial delay time is measured in the fixed delay circuit FDL. And operating the phase frequency comparator (PFD) when the internal clock (iclk) is generated.