KR100292460B1 - Method for executing conditional branch command and command executing device using the same - Google Patents

Abstract

PURPOSE: A method for executing a conditional branch command and a command executing device using the same are provided to rapidly execute a conditional branch command. CONSTITUTION: The method comprises steps of providing a conditional branching command to branch a control in case of selectively satisfying a condition, executing a branch command in 4 cycle period in case of satisfying the condition for branch command and replacing a command following to the conditional branch command with a control signal not to execute the following command while executing the branch command. The 4 cycle period consists of a first cycle generating a corresponding control signal by decoding the conditional branch command, a second cycle loading the address value to be branched and delaying one time, a third cycle loading the branching address value to a program counter and the fourth cycle decoding and executing the command read from the branching address value. In case of not satisfying the condition for the conditional branching command, the increase of program counter forcibly is added by 1 and the command following to the conditional branching command is decoded and executed.

Description

Conditional branch instruction execution method and instruction execution device using the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly, to a conditional branch instruction execution method and an instruction execution apparatus using the same for quickly performing conditional branch instructions.

In order to process digital signals at high speed, the microprocessor is provided with a digital signal processor (hereinafter referred to as "DSP"). Branch instructions, especially branch instructions, require high throughput. It will be described with reference to Figures 1 to 6 attached to the conventional DSP.

1 shows a schematic block diagram showing a conventional digital signal processing apparatus (DSP).

Conventional digital signal processing apparatuses have a Harvard Type structure having two separate Memory Bus structures.

The conventional DSP is a central processing unit consisting of a program addressing unit 200, an operation processing unit 300, and a multiplication unit 400 connected via the program address and program data buses 101 and 102 and the data address and data buses 601 and 602. 10, an auxiliary operation processing unit 500, a decoding unit 700, a program memory and a data memory 100, 600 are provided.

In addition, the conventional DSP adds a peripheral device (eg, a timer, a serial input / output device, a memory management device, etc.) for communication with an external device.

The program data bus 102 may decode instruction codes and immediate operands from the program memory 100 by using the program addressing unit 200, the operation processing unit 300, the multiplication unit 400, the memory addressing unit 500, and the decoding. Supply to the unit 700.

The data bus 601 is connected to the central arithmetic unit 10 including the arithmetic processing unit 300 and the multiplication unit 400, the auxiliary arithmetic processing unit 500, and the data memory 600.

The operation processing unit 300 executes a two's complement arithmetic operation and a Boolean operation using a 32-bit operation processing unit (ALU) 304 and an accumulator 305.

To this end, the arithmetic processing unit 300 is connected to an arithmetic processing unit 304 for performing two's complement operation on an input operand (operand) and data input to the arithmetic processing unit 304 by being connected to an input terminal of the arithmetic processing unit 304. Is connected to an output terminal of the arithmetic processing unit 304 to store a result of processing of the arithmetic processing unit 304, and the contents stored in the arithmetic processing unit 304 The accumulator 305 to be supplied and the post scaler 306 connected to the output terminal of the accumulator 305 and left-left-shifted are provided.

The first input data of the operation processing unit 300 is supplied via the data bus 601 in the data memory 600 or via the program data bus 102 in the program memory 100 for an immediate operand. Or is supplied from the output terminal of the multiplier 400.

The second input data of the operation processor 300 is supplied as the test / control bit 308 for the output of the accumulator 305 or the ZAIR instruction.

The prescaler 301 is a 16 bit from the data bus 601 by performing left-shifting in the range of 0 to 16 programmed by an instruction supplied from the program data bus 102 as a scaling shifter. The data is supplied and scaled to 32 bits of data and supplied to the arithmetic processing unit 304. At this time, the least significant bits (Least Significant Bits (LSBs)) of the output signals of the prescaler 301 supplied to the arithmetic processing unit 304 are filled with "0", and the most significant bits (MSBs) are Filled with " 0 " or optionally sign extended by sign extension mode bit SXM of status register ST1.

The accumulator 305 stores the output signal of the arithmetic processing unit 304 and supplies the arithmetic processing unit 304 with data stored via the first node N1 as second input data. This data is 32 bits long and is divided into higher order words (31 to 16 bits) and lower order words (15 to 0 bits). Higher and lower order words (0-31 bits) of the accumulator 305 are scaled in the post scaler 306 and supplied to the data memory 600 via the data bus 306.

The multiplier 400 includes a temporary register 401 connected in series with the prescaler 301, a multiplier 402 connected to the temporary register 401, and a processing result register connected to the multiplier 402. 403).

The temporary register 401 is a 16 bit register for storing one operand of the multiplier 402. The input data of the multiplier 400 is supplied from the data memory 600 via the data bus 601 or from the program memory 100 via the program data bus 102 to perform MAC / MACD instructions. Immediate data is supplied from the MPYK instruction word.

Multiplier 402 is a 16x16 bit parallel multiplier that performs two's complement multiplication by 16x16 bits, and stores the processing result in processing result register 403. The processing result register 403 is a 32-bit register that can access higher and lower words, respectively, by SPH / SPL instructions.

The post scaler 404 scales by supplying the output result data of the multiplier 402 from the process result register 403 to the arithmetic processing unit 304.

The program addressing unit 200 is connected to a program counter 205 and a program counter 205 for selectively loading an interrupt vector 202 to jump when an interrupt occurs. An eight-level hardware stack 206 is provided for storing the contents of the program counter 205 during the invocation of the subroutine.

The program counter 205 addresses the program memory 100 via the program address bus 101 or pushes it onto the stack 206. At this point, the stack pointer is automatically incremented to point to the next place at the top of the stack.

The auxiliary operation processing unit 500 is inputted to calculate the indirect address connected to the auxiliary register pointer 501, the auxiliary register AR 502 connected to the auxiliary register pointer 501, and the auxiliary register AR 502. Auxiliary arithmetic unit (ARAU) 503 for arithmetic processing of a signal to be processed, a data memory page pointer 504, and a data memory address bus (DMA: 505) are provided.

The data memory 600 is addressed by the data address bus 602, and the program buses 101 and 102 and the data buses 601 and 602 are on-chip data memory 600 in a single cycle for performing arithmetic processing. ) And the data from the internal program memory 100 are supplied to the central processing unit 10 and the auxiliary processing unit 500. The data address map can be extended to a total of 96K memory space by adding a 64K word address due to the 16 bit address bus and a 32K word address due to the global memory interface.

The program memory 100 has a 64K memory space. Data memory addressing methods include direct addressing (e.g., ADD 010h), indirect addressing (e.g., Add * +) by an auxiliary register file, and immediate addressing (Immediate addressing) mode by an operand.

In the direct memory addressing mode, the 9 bit data memory page pointer 504 divides the data memory 600 into 512 pages (1 page = 128 Word) and points to one of them and either the data bus 601 or the program data bus 102. Data is supplied from The data memory address bus (hereinafter referred to as "DMA") 505 takes the lower 7 bits of the instruction received from the program data bus and points to the desired word in the page. Thus, the data address bus 602 is formed of a 16 bit address of a 9 bit data memory page pointer 504 and a 7 bit DMA 505.

In the indirect addressing mode, the 16 bit auxiliary register (AR) 502 selected by the auxiliary register pointer 501 addresses the data memory 600 and the stored operand of the 16 bit auxiliary register 502 is the auxiliary operation processing unit ARAU; It is supplied to 503 and calculated. Eight auxiliary registers ARO to AR7 502 are used for indirect addressing or temporary data storage of the data memory 600.

Auxiliary register 502 and auxiliary register pointer (ARP) 501 transfer data from data memory 600, accumulator 305, processing result register 403, or immediate operand in instruction code via data bus 601. Supplied, the contents of the auxiliary register 502 are continuously processed by the auxiliary processing unit 503 and stored in the data memory 600 via the data address bus 602, and the data stored in the data memory 600 It is optionally loaded to the central processing unit 10 via the data bus 601.

The file of the auxiliary register 502 is connected to the auxiliary operation processing unit 503 and is automatically indexed while the data memory 600 is addressed. The function is as follows.

Indirect addressing arithmetic operations are not performed (for example, ADD *), AR (ARP) + 1 → AR (ARP) (for example ADD * +), AR (ARP) -1-AR (ARP). ) (E.g. ADD *-), AR (ARP)-> ARO (e.g. ADD * 0 +), AR (ARP)-> ARO (ARP) (e.g. ADD * 0-), AR ( ARP) + rc (ARO)-> AR (ARP) (e.g., ADD * BRO +), AR (ARP) -rc (ARP)-> AR (ARP) (e.g., ADD * BRO-). . Here, rc (ARO) refers to a bit reversed addressing mode for calculating (+,-) ARO with reverse carry propagation.

The auxiliary arithmetic unit 503 may not only be used for address processing in parallel with other arithmetic units, but may also perform general purpose arithmetic processing because the auxiliary register file is directly connected to and communicated with the data memory 600. . The BANZ instruction then allows the auxiliary register 502 to be used as a loop counter.

The auxiliary arithmetic unit 503 provides functions such as data and program block movement and data movement in order to use the memory efficiently. The BLKD command moves blocks in the data memory 600, and the BLKP command moves blocks in the program memory 100 to the data memory 600. Executing these instructions with repeat instructions RPT, RPTK effectively sets the repeat counter 800 from on-chip or off-chip memory and is used to execute repeat instructions repeatedly. Move command DMOV is a command that can copy one word from the currently addressed data memory 600 in the on-chip memory to the next higher location. Efficiently execute Z- ¹ delay algorithms such as convolution and data filtering.

The table read / write command (TBLR / TBLW) is a command that enables word transfer between the program memory 100 and the data memory 600, and the TBLR is a data memory 600 in the program memory 100. ), And ATBLW loads data from the data memory 100 and writes it to the program memory 100.

Many applications that require large dynamic range perform floating point operations. The normalization instruction implements a normalization function by left-shifting a fixed point number included in the accumulator 305.

The central processing unit 10 including the processing unit 300 and the multiplication unit 400 includes a 16 bit prescaler 301 and a 32 bit processing unit 304 connected to the program data bus 102 and the data bus 601. ), A process result register 403 connected to the output end of the 16x 16 bit parallel multiplier 402, a 16x 16 bit parallel multiplier 402, and a post scaler 404 connected to the output end of the process result register 403; And an accumulator 305 connected to the output terminal of the 32 bit arithmetic processing unit 304 and a post scaler 306 connected to the output terminal of the accumulator 305.

The prescaler 301 and the postscaler 306 and 404 are used as shifters for numerical scaling, bit extraction, extended-precision arithmetic, and overflow protection.

The four case shift mode PM 405 is used to shift the processing result register 403 value to the four case mode as shown in Table 1 below.

In case 4, the left shift specified in the shift mode PM 405 is used to implement fractional arithmetic or normalize the fractional product, and the right shift is 128 times without overflow. Enables execution of successive multiplication / cumulative operations. In four cases, the write shift of the shift mode PM 405 is always sign extended regardless of the sign extension mode (SXM) 303 state.

System control is also performed by the program counter 205, the hardware stack 206, the external reset signal RS, the interrupt control circuits 202, 203, 204, the status register, and the repetition counter 800.

The program counter 205 addresses an on-chip or off-chip program memory 100. When the program memory 100 is addressed by the program address bus 101, the program data bus 102 ) Is loaded into the instruction register IR in the decoder 700. When the instruction register IR is loaded, the program counter 205 is preparing to start the next instruction fetch. Decoder 700 generates various control output signals needed to execute the command.

To this end, the decoder 700 performs a four-stage pipeline operation, in which the instruction pipeline is related to the bus operation during the instruction execution period.

The four-stage pipeline of instruction fetch, decode, operand fetch, and execution is invisible except when the pipeline is broken, such as a branch. The operation of each stage is independent. Thus, one to four other instructions can be activated in any given cycle.

Table 2 below shows the operation of the four-stage pipeline.

The reset signal RS is a non-maskable external interrupt, which is an interrupt having the highest priority, forcing and interrupting processor execution to set the program counter 205 to "zero", and to register various registers. And status bits. Therefore, for normal operation of the system at power-on, the logic value of the reset signal should be kept low for at least 10 clock cycles.

Processor execution begins at location 0 and typically contains branch instructions to link to the system initialization routine.

When the reset signal is supplied to the processor, the processor sequentially performs the following operations. Program counter PC = 000h, status register ST0 = 0E00h, status register ST1 = 0770h, global memory register GREG = 00h, repeat counter RPTC = 00h, interrupt flex register IFR = 00h, interrupt mask register IMR = 00h, data bus has high impedance Initialize status, period register PRD = OFFFFh, time register TIM = OFFFFh, and other peripherals to be loaded into the time register.

There are two status registers inside the processor, namely, a first status register ST0 and a second status register ST1, which represent internal states, and the contents thereof are as shown in FIG.

In the first and second status registers ST0 and ST1, "ARP" is a pointer to an auxiliary register, "OV" is overflow flag, "OVM" is overflow mode, "INTM" is interrupt mask flag, and "DP" is Data page pointer, "APB" is the auxiliary register pointer buffer, "CNFO" is the Configuration flag, "TC" is the test bit flag, "SXM" is the sign extension mode, "C" is the carry bit ( Carry bit), "HM" is hold mode bit, "FSM" is frame sync mode bit, "XF" is external flex pin status bit, "FO" is format bit, format bit F0 = "0" If so, the serial port register consists of a 16 bit register. "TXM" is a transmission mode bit, "PM" is a shift mode in four cases, and the operation according to the case is shown in Table 1.

The repetition counter 800 is an 8-bit counter that can be loaded by the repetition instructions RPT and RPTK. When the number N is loaded, the repetition counter 800 executes N + 1 times if the next instruction is repeatedly executed.

When an idle instruction is executed or when the hold mode bit HM = 1 in the second status register ST1 and the logic value of the hold interrupt pin remains low, the processor enters the power down mode ( Power Down Mode). In power-down mode, power consumption is consumed significantly less than that normally consumed. The contents of the processor remain unchanged in power down mode, and when any interrupt is input, the power down mode is released and the processor continues to operate normally.

The processor includes three first to third external maskable interrupts (INT0 to INT2), three internal interrupts (RINT, XINTM, and TINT), and one software interrupt (TRAP) used by an external device to interrupt the processor. Is provided.

Table 3 shows the vector position, priority, and contents of the interrupt mask register of these interrupts, and FIG. 3 shows the contents of the interrupt mask register (IMR).

Each interrupt address typically has its own address space, which allows for branch instructions to be placed at that location.

In the conventional DSP shown in FIG. 1, a processing procedure of viewing and branching a value stored in the accumulator 305 will be described below.

If the program counter 205 reads the instruction code for supplying the address to the program memory 100 and adding the value of the data memory 600 called "ADD" and the value of the accumulator 305 and storing it in the accumulator 305 again. The decoder 700 interprets the command code and generates a control signal in each lower block. The data loaded through the data memory 600 is processed by the arithmetic processing unit 304 and the result is stored in the accumulator 305. If the next instruction is a branch instruction that refers to the value of the accumulator 305, even when the branch instruction code enters the decoder 700, when a new value is entered in the accumulator 305 in the pipeline structure, You have to wait 1 cycle.

Referring to Table 2, an instruction fetch is a cycle of reading an instruction from the program memory 100, and decoding is a cycle of generating a control signal by analyzing the read instruction code. to be. The operand fetch is a cycle of reading data to be processed from the data / program memories 600 and 100, and the execution is a cycle of processing data. Since each cycle is synchronized with the clock, the result of execution is stored in the accumulator 305 or the like in synchronization with the clock following the execution cycle.

4 and 5 show conditional branch timing diagrams in a conventional four stage pipeline.

4 and 5, the result of executing the ADD command is stored as a new accumulator value. If the ADD instruction is followed by a conditional fetch (CB) instruction followed by a branch address lk (Long Immediate), the CB instruction unconditionally waits three cycles until a new accumulator value is stored. After determining whether to branch or not based on the accumulator value, a control signal for loading lk to the program counter 205 is generated in the next cycle, and the address to branch to the next cycle is loaded into the program counter 205. You can branch successfully. At this time, if the condition is not satisfied (False), as shown in FIG.

This approach waits until a structurally new accumulator value comes out because the control signal controlling the program counter 205 comes out of the operand fetch cycle in synchronization with the clock of the decoding phase and then the program counter 205 in the next cycle. The program counter control signal, which decides whether to carry a branch address or to increase the program counter value by "1", follows the condition.

As a result, a conditional branch that references an accumulator value in a four-stage pipeline structure requires five cycles if conditions are met and three cycles if conditions are not met.

6 is a state diagram for generating a control signal required to execute a conditional branch instruction in a conventional four-stage pipeline structure.

The initial state is S1, and if the decoded instruction was a conditional branch, it proceeds through S2 to S3. In S3, if the accumulator condition is true, the branch instruction is executed while making a control signal to load the address to branch to the program counter 205 through S4 and S5.

If the accumulator condition is False, it returns from S3 to S1 and executes the next consecutive command. In case of generating a control signal using a state machine, a conventional method requires a total of five states for conditional branching and a conditional branch related program logic array (PLA). The code also needs 6 terms (S1, S2, S3 (True), S3 (False), S4, S5). As such, when the conditional branching is performed in the four-stage pipeline, if the whole instruction is an instruction that affects the accumulator value, the conditional branch instruction must wait one more cycle until the new value is loaded in the program counter 205.

Accordingly, an object of the present invention is to provide a conditional branch instruction execution method and a command execution apparatus using the same to quickly perform a conditional branch instruction.

1 is a schematic block diagram showing a conventional digital signal processing apparatus (DSP).

2 is a diagram showing the contents of a first state register STO and a second state register ST1 mounted in a processor in a conventional digital signal processing apparatus (DSP).

3 is a diagram showing the contents of an interrupt mask register in a conventional digital signal processing apparatus (DSP).

4 is a conditional branch timing diagram when a condition is satisfied in a four-stage pipeline in a conventional digital signal processing apparatus (DSP).

5 is a conditional branch timing diagram when a condition is not satisfied in a four-stage pipeline in a conventional digital signal processing apparatus (DSP).

6 is a branched state diagram of a four-stage pipeline structure in a conventional digital signal processing apparatus (DSP).

7 is a timing diagram when a conditional branch of a four-stage pipeline is satisfied in a conditional branch instruction execution method and an instruction execution apparatus using the same according to an embodiment of the present invention.

8 is a timing diagram when a conditional branch of a four-stage pipeline is not satisfied in a conditional branch instruction execution method and an instruction execution apparatus using the same according to an embodiment of the present invention.

9 is a detailed timing diagram of a conditional branch of a four-stage pipeline in a conditional branch instruction execution method and an instruction execution apparatus using the same according to an embodiment of the present invention.

10 is a schematic block diagram of a conditional branch instruction execution apparatus according to an embodiment of the present invention.

11 is a state diagram of a conditional branch in a conditional branch instruction execution method and an instruction execution apparatus using the same according to an embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

2: Program Logical Array (PLA) 4: Finite State Machine (FSM)

6,14 flip / flop 8,12,16 multiplexer

10: central processing unit 100: program memory

101: program address memory 102: program data memory

200: program addressing unit 201,603: CNF

202: interrupt vector 203: interrupt mask flag

204: interrupt mask register 205: chromagram counter

206: hardware stack 300: arithmetic processing unit

301 306 404 Scaler 302 overflow mode

303: sign extension mode 304,503: arithmetic processing unit

305: Accumulator 308: Test / Control Bits

400: multiplier 401: date and time register

402: Multiplier 403: Processing Result Register

405: shift mode in case of 500 500: auxiliary operation processing unit

501: auxiliary register pointer 502: auxiliary register

504: data memory page pointer 505: data memory address bus

600: data memory 601: data bus

602: data address bus

In order to achieve the above object, the conditional branch instruction execution method of the present invention comprises the steps of: supplying a conditional branch instruction that branches control only if the condition is optionally met; The first cycle in which the conditional instruction is decoded to generate a control signal, the second cycle of loading the delayed address value, and the third cycle of causing the delayed address value to be loaded into the program counter and the branched address value to be loaded. A branch is executed in a period of four cycles when the condition is satisfied for the branch instruction including a fourth cycle of decoding and executing the instruction read from the branch instruction, and the branch instruction if any instruction is supplied following the conditional branch instruction. And substituting a control signal for preventing any command from being executed while executing the operation.

A conditional branch instruction execution method of the present invention comprises the steps of: supplying a conditional branch instruction that branches to control only if the condition is optionally met; When the condition of the conditional branch instruction is not satisfied, the program counter is incremented by "1" to decode and execute any instruction supplied following the conditional branch instruction to execute the arbitrary instruction in a period of two cycles. Steps.

The conditional branch instruction execution device of the present invention is connected to a command supply means, a signal generation means for generating a control signal according to the type of command supplied and connected to the command supply means, and selectively connected to the signal generation means. First switching means for preventing a control signal from being executed, delay means for delaying an output signal of the first switching means connected to the first switching means; Second switching means connected to the delay means for selectively switching signals from the delay means, branch control means connected to the signal generating means for branching to a new state according to command conditions, signal generating means and branch control And second delay means, commonly connected to the means, for selectively delaying a signal from the branch control means and supplying the signal to the signal generating means and the branch control means.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 7 to 11.

7 and 8 illustrate a method of executing a conditional branch instruction according to an embodiment of the present invention, and a timing diagram of performing a conditional branch instruction of a four-stage pipeline in an instruction execution apparatus using the same.

7 to 8, a description will be given with reference to Fig. 1 showing a conventional DSP.

7 and 8, in the conditional branch instruction execution method and the instruction execution apparatus using the same according to the present invention, if the conditional branch instruction of the four-stage pipeline is satisfied in the cycle of determining the branch condition, The instruction to load the address lk to the program counter 205 in the current cycle can be issued and the branch can be conditionally branched into four cycles with successful branching in the next cycle.

If the condition is not met, the instructions following the conditional branch instruction are executed in order.

FIG. 9 is a timing diagram illustrating in detail the conditional branch instruction execution of FIGS. 7 and 8 according to an operation state of a DSP.

Referring to FIG. 9, each stage is represented by one cycle of a clock according to a signal flow.

9A shows the case when the conditional branch is satisfied, and FIG. 5B shows the case when the conditional branch is not satisfied.

The instruction read from the program memory 100 in the first stage Stage0 is loaded into the instruction register IR in the decoder 700 in the second stage Stage1 via the program data bus 102. The first step: S1) PLA starts to decode this command and generates a control signal that causes the outputted PLA out to read the processed data from the data memory 600 during the third stage (Stage2) in synchronization with the clock. (2nd step; S2)

Of the control signals supplied in the second step S2, the signal supplied to the arithmetic processing unit 304 is delayed by one cycle to perform the calculation in the fourth stage Stage3, and the result is accumulated in the fifth stage Stage4. 305. (3rd step; S3)

If the instruction read from the second stage Stage1 is a conditional branch instruction, a conditional branch instruction (hereinafter referred to as "CB") is loaded into the instruction register IR in the fourth step S4. The CB is decoded in the PLA so that a control signal according to it is carried out in the next cycle (S5; S5), and the lk (Long Immediate) value, which is the address to branch on the program bus in the third stage (Stage2), is the fourth stage (Stage3). ) Is placed in a register called immdp.

In the fourth stage (Stage3), the output PLA of the CB to the CB generates a control signal for loading the value loaded on the data bus DB to the program counter 205 in the sixth step S6. Let's do it. In the seventh step S7, the branched address lk loaded in immdp is delayed once, and then in the eighth step S8, lk is loaded on the data bus DB.

If the various conditions refer to the accumulator 304 in the fourth stage (Stage3) is met, the ninth step according to the instruction to store the lk carried on the data bus DB prepared in the sixth step (S6) to the program counter (205) In S9), the address lk which is to branch to the program counter 205 is loaded.

In a tenth step S10, the command code read from the lk address is executed while being decoded in the eleventh step S11.

At this time, in the twelfth step S12, the SACL command is loaded into the command register IR to be decoded to generate an output PLA of PLA for the SACL command in the fifth stage Stage4. In a thirteenth step S13, the SACL command is replaced with a NOP control code so that the SACL and the subsequent MAR command are not executed.

If the branch condition is not satisfied in the fifth stage (Stage4), the "PC load from DB (control signal for loading the value of the data bus to the program counter)" control signal generated in the sixth step S6 is "PC". normal increase of the program counter ", and the PLA output of the PLA for the SACL instruction decoded in the twelfth step S12 can be normally used as a control signal in the next cycle.

FIG. 10 illustrates a conditional branch instruction execution device of the present invention implementing the structure of the four-stage pipeline described with reference to FIGS. 7 to 9. 11 shows a conditional branch instruction execution method and conditional branch state diagram of an instruction using the same.

Referring to FIG. 10, the conditional branch instruction execution apparatus of the present invention receives a command code and a status and includes a PLA (2) for generating various command types and a control signal for use in each sub block, and a PLA ( 2) a finite state machine (hereinafter referred to as "FSM", 4), which receives a command and a current status signal from the PLA (2) and determines the next state. A flip / flop (6) connected to (4) to delay the output signal of the FSM (4) according to the logic value of the clock signal to feed back the status signal to the PLA (2) and the FSM (4). Equipped.

The conditional branch instruction execution device of the present invention is connected to the PLA (2) and immediately use the control signal generated from the PLA (2) or if the condition of the conditional branch (Conditional Branch) is satisfied, no operation control code (No an output signal of the second multiplexer 16 connected to the first and second multiplexers 8 and 16 for determining whether to substitute an operation control code) and an output terminal of the second multiplexer 16. A second flip / flop 14 for delaying the signal according to a clock signal, and a command for increasing the program counter by "1" if the condition is not met when a conditional branch instruction is input when the second flip / flop 14 is connected. And a third multiplexer 12 for outputting a control signal in which the output signal PLAout of the PLA 2 is delayed by one cycle when the condition is satisfied.

The following shows the source of the simplified PLA 2 needed to execute a conditional branch.

First state (S1), opbc → type1, nobrtype, immdpfrompb, noimmdtodb, pcnormal -------------------- (SS1)

Second state (S2), opbc → type1, brtype1, instfrompb, immd16todb, pcfromdb -------------------- (SS2)

The simplified FSM source of the conditional branch state diagram of FIG. 10 is as follows.

type1, first state (S1) → second state (S2) -------- (SS3)

type1, second state (S2) → first state (S1) -------- (SS4)

In the sources (SS1), (SS2), (SS3), and (SS4) of the PLA 2 and the FSM 4, the left side represents an input code and the right side represents an output code based on "→".

In the decoding section, if the command supplied to the PLA (2) is bc (SS1) generates a control code of type1, nobrtype, noimmdtodb, pcnormal to output to PLAout. At this time, the control signals except for type1 are supplied as signals for controlling the lower block or after the one cycle delay in the second flip / flop 14.

At present, if the state is the first state S1 and type1, the output state of the FSM 4 is outputted to the second state S2 of the FSM 4 output FSMout as shown in the state diagram in FIG. At this time, the control signal immdpfrompb is a command code for loading the value lk on the program bus into a register called immdp so as not to load lk in the command register IR at the same time.

Accordingly, as shown in FIG. 8, the CB code is loaded in the instruction register IR for two cycles. At this time, if the second state (S2) and the command is CB, PLA (2) generates a control signal such as (SS2). This step corresponds to the fourth stage Stage3 of FIG. 9. The control signal in this step comes out of pcfromdb which causes the program counter to load lk, which is an address value to branch to. Among the output values obtained from (SS2), a control signal called brtype is delayed in the fifth stage (Stage4) in FIG. 9 to confirm the condition of the accumulator, and when the condition is met, the control signal called metcond is activated.

The meetcond signal is supplied to the control signals of the first to third multiplexers 8, 16 and 12 to select an input.

In FIG. 9, when the control code of the fifth stage Stage4 sees the meetcond signal and the meetcond is “1”, the first input signal IN1 is output from the first and second multiplexers 8 and 16.

The control signals from the first input signal IN1 replace the output PLAout of the PLA 2 of the SACL from the fifth stage Stage4 of FIG. 9 with type1, nobrtype, instnoload, noimmdtodb, and pcnormal. All control signals are changed to no operation except stage steady state increment (PC + 1) of the program counter in stage Stage5.

Accordingly, the fifth stage Stage4 PLAout resulting from decoding the SACL instruction in FIG. 9 disappears.

The meetcondd signal is one cycle delayed from the meetcond signal. When this signal is activated, the outputs of the first and second multiplexers 8 and 16 of FIG. 9 are set as the second input signal IN2. The second input signals IN2 are type1, nobrtype, instfrompb, noimmdtodb, and pfcnormal. The second input signals IN2 are loaded into the instruction register IR in the next cycle (stage 7; Stage6) in the sixth stage Stage5 in FIG. It recovers.

The pfcnormal control signal increments the program counter "1". In FIG. 9, if the branch condition is not satisfied in the fifth stage (Stage4), meetcond = "0" is inactive.

At this time, the first and second multiplexers 8 and 12 of FIG. 9 normally output the first output signal PLAoutp1 and the second output signal PLAoutp2 of the PLA 2, and the third multiplexer. 12 outputs the normal program counter increment (PC + 1).

Therefore, when executing the conditional branch, pcfromdb, the control signal from the second cycle, is changed by the third multiplexer 12 to the steady state program counter increment (PC + 1) to execute the command following the conditional patch CB. do.

As described above, the conditional branch instruction execution method and the instruction execution apparatus using the same of the present invention can quickly perform a conditional branch instruction.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (11)

Optionally supplying a conditional branch instruction that branches control only if the condition is met; A first cycle in which the conditional instruction is decoded to generate a control signal, a second cycle of loading a delayed address value once, and a third cycle of causing the branched address value to be loaded into a program counter, and the branch. A branch is executed in a period of four cycles when the condition is satisfied for the branch instruction including a fourth cycle of decoding and executing the instruction read from the address value to be executed, and any instruction following the conditional branch instruction. And substituting a control signal for the arbitrary instruction not to be executed while executing the branch instruction if the branch instruction is supplied. The method as claimed in claim 1, wherein the branching is executed when the condition of the accumulator is satisfied by referring to a value of an accumulator for storing the result of an arithmetic processing unit that performs two's complement operation and a Boolean operation. How to perform a conditional branch instruction. Optionally supplying a conditional branch instruction that branches control only if the condition is met; If the condition of the conditional branch instruction is not satisfied, the increment of the program counter is forcibly increased by " 1 " to decode and execute any instruction supplied following the conditional branch instruction to execute the arbitrary instruction for two cycles. Conditional branch instruction execution method comprising the step of executing. Command supply means for supplying a command; Signal generation means connected to said command supply means for generating a control signal in accordance with the type of command supplied; First switching means connected to the signal generating means to selectively prevent the control signal from being executed; Delay means connected to said first switching means for delaying an output signal of said first switching means; Second switching means connected to said delay means for selectively switching a signal from said delay means; Branch control means connected to said signal generating means for branching to a new state according to command conditions; And second delay means commonly connected to said signal generating means and said branch control means for selectively delaying a signal from said branch control means and supplying it to said signal generating means and said branch control means. Branch instruction execution device. The conditional branch command execution according to claim 4, wherein the signal generating means is a program logic array (PLA) for generating a control signal to control a command type and a peripheral device by receiving an arbitrary command code and a status signal. Device. The signal generating means according to claim 4, further comprising: a conditional branch instruction for branching control only when a condition is satisfied; And the first switching means prevents the control signal of the signal generating means from being performed when the conditional branch instruction is satisfied. The signal generating means according to claim 4, further comprising: a conditional branch instruction for branching control only when a condition is satisfied; And the control signal of the signal generating means is decoded to be executed if the conditional branch instruction is not satisfied. 5. The conditional branch instruction execution device according to claim 4, wherein the first and second delay means delays the signal supplied thereto by one cycle according to the logic value of the clock signal. The signal generating means according to claim 4, further comprising: a conditional branch instruction for branching control only when a condition is satisfied; And if the conditional branch instruction is not satisfied, the second switching means outputs a command to increase the increment of the program counter by one. The signal generating means according to claim 4, further comprising: a conditional branch instruction for branching control only when a condition is satisfied; And the second switching means outputs a signal from the second delay means if the conditional branch instruction is satisfied. The method according to claim 4, wherein the branch control means is a finite state machine (FSM) for selectively determining a state which is in an initial state and a second state of a branched state according to a command condition supplied. Conditional branch instruction execution device.

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