KR100291345B1 - High definition television compatible clamp signal generation circuit - Google Patents

Abstract

The present invention relates to a compatible clamp signal generation circuit that can accommodate a current television signal (NTSC, PAL, SECAM, etc.) in a high definition television.

Generally, binary level synchronization signals are used in current television systems and ternary level synchronization signals are used in high-definition television systems. Conventionally, clamp pulse generation circuits that support both types of synchronization signals have not been developed. .

Therefore, the present invention detects the pedestal level of the video signal to generate a level detection signal, detects the sub-level of the synchronization signal to generate the synchronous detection signal, and compares the timings of the two detection signals to a level later than the synchronous detection signal. The clamp pulse included in the detection signal is provided to the video preamplifier. The present invention can generate accurate clamp pulse even when a binary level synchronization signal or a trilevel level synchronization signal is input, so that the present terrestrial broadcasting can be viewed through next-generation high-definition television. It is effective to maximize their convenience.

Description

A circuit for generating compatible clamp pulses in a HDTV

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clamp signal generating circuit used in a video system of a high definition television (HDTV). In particular, a compatible clamp signal generating circuit can accommodate a current television signal (NTSC, PAL, or SECAM) in a high definition television. It is about.

In general, a 'CLAMP' in a television means that a DC component removed when a video signal passes through a transmitting circuit is reproduced before the video signal is applied to a display device, thereby reproducing an image of correct brightness. In this clamp circuit, the DC level of the input video signal is made constant to prevent the DC level from being changed.

That is, the clamp circuit clamps the DC level at the timing provided by the clamp pulse, which includes a sync tip clamp that maintains the bottom level (sink tip) of the synchronous pulse as the clamp level, and a back. There is a back porch clamp that applies a clamp pulse to the porch section so that it is clamped at the pedestal level.

On the other hand, in the current television system (NTSC, PAL, SECAM) defined by CCIR601, the horizontal synchronization signal is defined to have a binary level (pedestal level and negative level), but it is newly attracting high-definition television (HDTV). ), It is recommended that the horizontal synchronization signal have three levels (pedestal level, negative level, and positive level).

Therefore, a high-definition television requires a clamp pulse generation circuit corresponding to the three-level level, and in particular, a clamp signal generation circuit capable of supporting both the current analog television type binary level and the HDTV type three level level for compatibility. Is required.

1 shows a video system of a high definition television to which the above clamp pulses are applied. That is, the video switching unit 11 selects one input terminal among a plurality of video input terminals (not shown), and transmits R, G, and B video signals to the video preamplifier 12, and the video preamplifier 12 The R, G, and B video signals are AC amplified, and the video output amplifier 13 amplifies the video signal output from the video preamplifier 12 to a level sufficient to drive the cathode end of the CRT 14.

In the present invention, the CRT is referred to as a display device, but the display device is not limited thereto, and a liquid crystal display device (LCD) or a plasma display device (PDP), which is a flat panel display device, may be used.

Meanwhile, a blanking pulse for blanking the sync signal included in the video signal and a clamp pulse for constantly reproducing the DC level of the video signal are applied to the video preamplifier 12. Among the video inputs, the synchronization signal of the video signal selected by the video switching unit 11 is selected and applied to the synchronization signal processing unit 18, and the synchronization signal is processed to detect a sublevel, based on the sublevel of the synchronization signal. The blanking pulse is generated and applied to the video preamplifier 12. The clamp signal generator 19 generates a clamp pulse and applies the clamp pulse to the video preamplifier 12.

In addition, the OSD processor 15 provides OSD data and a gain signal to the video preamplifier 12 to display an On Screen Display (OSD) screen together with the R, G, and B video signals on the CRT screen. The video bias unit 16 provides R, G, and B bias signals (R _bias , G _bias , and B _bias ) to adjust the bias of the R, G, and B video signals output from the video output amplifier 13. do.

However, in the video system of the high definition television as described above, the clamp signal generator can only generate the clamp pulse corresponding to the synchronous signal of the three level level or the clamp pulse corresponding to the synchronous signal of the binary level, and the binary level. A circuit for generating a clamp pulse corresponding to both the synchronous signal and the trilevel level has not been disclosed yet. Therefore, the development of a compatible clamp signal generation circuit capable of supporting both a binary level synchronization signal in a current television and a trilevel level synchronization signal in a high definition television with a simple configuration is required.

Accordingly, the present invention has been made to meet the above needs, and generates a compatible clamp pulse that supports both the two-level synchronization signal and the three-level synchronization signal, to watch the current terrestrial broadcasting through high-definition television. An object of the present invention is to provide a compatible clamp signal generating circuit of a high definition television.

The present invention for achieving the above object, the video preamplifier for processing and amplifying the R, G, B video signal based on the blanking pulse and the clamp pulse, and the R, G, B amplified by the video preamplifier A video system of a high definition television comprising a video output amplifier for amplifying a video signal and outputting the same to a display element, the video system comprising: a level detector for outputting a level detection signal in a pedestal level section of the video signal; A synchronization signal processor for receiving a horizontal synchronization signal and a video signal and detecting a sublevel section of the synchronization signal to output a synchronization detection signal; A timing comparison unit comparing the timing of the level detection signal with the synchronization detection signal and outputting a level detection signal of the back porch portion; And a clamp pulse output unit configured to output a clamp pulse included in the level detection signal period of the back porch portion output from the timing comparison unit to the video preamplifier.

1 is a block diagram showing a video system of a general high definition television;

2 is a block diagram showing a compatible clamp signal generation circuit of a high-definition television according to the present invention;

3 is a waveform diagram of each sub-signal of FIG. 2 when a high-definition television (HDTV) video signal is input;

4 is a waveform diagram of each sub-signal of FIG. 2 when a general analog television (NTSC) video signal is input.

Explanation of symbols on the main parts of the drawings

11: video switching unit 12: video preamplifier

13: video output amplifier 14: CRT

15: OSD Processor 16: Video Bias

17: synchronous switching unit 18: synchronous signal processing unit

19: clamp signal generator 21: A / D conversion unit

22: level detector 23: synchronization signal processing unit

24: timing comparison section 25: clamp pulse output section

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the video signal of the current television system and the video signal of the HDTV will be briefly described. In the current television system, in the NTSC system, in the composite video signal, approximately 4.7 μsec in a horizontal blank period of about 10.9 μsec, as shown schematically in FIG. 4, between the horizontal line H and the horizontal line H. There is a horizontal synchronizing pulse of-), followed by a front porch (FP) of about 1.5 microseconds prior to this synchronizing pulse, and a back porch (BP) of about 4.7 microseconds following this synchronizing pulse. In this binary level synchronization signal, the clamp pulse is located in the back porch (BP) period of the video signal.

Meanwhile, as shown in FIG. 3, a front porch (FP) and a front porch (FP) of about 0.593 μsec and about 0.593 μsec are shown between the horizontal line H and the horizontal line H in the composite video signal of the HDTV system. There are negative horizontal sync pulses, positive horizontal sync pulses of about 0.593 μsec, and back porch (BP) of about 1.943 μsec. In this tri-level synchronizing signal, the clamp pulse is located in the back porch BP period following the positive horizontal synchronizing pulse.

1 shows a video system of a general high definition television, which includes a video switching unit 11, a video preamplifier 12, a video output amplifier 13, a CRT 14 as a display element, and an OSD processor 15. ), A video bias unit 16, a synchronous switching unit 17, a synchronous signal processing unit 18, and a clamp signal generating unit 19.

2 shows a compatible clamp signal generation circuit according to the present invention, which includes an A / D converter 21, a level detector 22, a synchronization signal processor 23, and a timing comparator 24. And a clamp pulse output unit 25, and the clamp pulses output from the clamp pulse output unit 25 are provided to the video preamplifier 12.

Referring to FIG. 3, when the HDTV video signal is input, each sub-signal waveform of the configuration diagram shown in FIG. 2 will be described.

One of the R, G, and B video signals is input to the A / D converter 21. The R, G, and B video signals all include the same synchronization signal in the horizontal blanking period. This is because the same result can be obtained by only signal processing. The A / D converter 21 converts the input HDTV video signal to digital so that the level detector 22 can detect the pedestal level of the synchronization signal.

On the other hand, the HDTV video signal and the horizontal synchronization signal are input to the synchronization signal processor 23. The synchronization signal processor 23 uses the horizontal synchronization signal as the main synchronization signal and the synchronization signal included in the HDTV video signal as an auxiliary synchronization signal. As a result, the negative level included in the synchronization signal is detected, and the synchronization detection signal of the active negative level is output as shown in FIG. That is, when the horizontal synchronization signal is input, the negative level of the horizontal synchronization signal is detected and the synchronization detection signal is output. When the horizontal synchronization signal is not input, the negative level of the synchronization signal included in the HDTV video signal is output. Is detected and a synchronous detection signal is output. Of course, the sync signal processor 23 may invert the sync signal of the active negative level and output the sync signal of the positive positive level.

The HDTV video signal digitally converted by the A / D converter 21 is input to the level detector 22 and the pedestal level is detected. From the level detector 22, the active unit as shown in FIG. Level detection signal of level is output. Of course, the level detector 22 may invert the level detection signal of the active negative level and output the level detection signal of the positive active level.

The level detection signal (Fig. 3 (b)) output from the level detector 22 and the sync detection signal (Fig. 3 (a)) output from the synchronization signal processing section 23 are sent to the timing comparison section 24. Input, the two signals are compared with each other. At this time, the active portion of the level detection signal is located before and after the active portion of the synchronization detection signal. The active portion of the level detection signal located before the synchronization detection signal means the front porch of the synchronization signal, and the level located after the synchronization detection signal. The active portion of the detection signal means the back porch of the synchronization signal. In general, since the clamp pulse is located at the back porch of the sync signal, the timing comparator 24 detects the active portion of the level detection signal, which means the back porch of the sync signal, to generate a waveform as shown in FIG. Output

The clamp pulse output unit 25 receives the level detection signal of the back porch portion output from the timing comparator 24 to generate a clamp pulse as shown in FIG. 3 (d) to the video preamplifier 12. Output

Hereinafter, referring to FIG. 4, when the general NTSC video signal is input, each sub signal waveform of the configuration diagram shown in FIG. 2 will be described.

The A / D converter 21 converts the input NTSC video signal to digital so that the level detector 22 can detect the pedestal level of the synchronization signal. The NTSC video signal digitally converted by the A / D converter 21 detects the pedestal level at the level detector 22. From the level detector 22, the active unit (as shown in FIG. Level detection signal of level is output. Of course, the level detector 22 may output an active positive level detection signal by inverting the active detection level detection signal.

On the other hand, the NTSC video signal and the horizontal synchronizing signal are input to the synchronizing signal processing unit 23. When the horizontal synchronizing signal is input, the synchronizing signal processing unit 23 detects the negative level of the horizontal synchronizing signal and detects the synchronizing. When the horizontal synchronization signal is not input, the signal is output, and the sub-level of the synchronization signal included in the video signal is detected to output the synchronization detection signal. That is, the synchronization signal processing unit 23 outputs an active negative level synchronization detection signal as shown in FIG. 4A, and inverts the active detection level synchronization signal as necessary. In addition, an active positive level synchronization detection signal may be output.

The level detection signal (Fig. 4B) output from the level detector 22 and the synchronization detection signal (Fig. 4A) output from the synchronization signal processing section 23 are sent to the timing comparison section 24. Input and the two signals are compared. At this time, the active portion of the level detection signal is located before and after the active portion of the synchronization detection signal. The active portion of the level detection signal located before the synchronization detection signal means the front porch of the synchronization signal, and the level located after the synchronization detection signal. The active portion of the detection signal means the back porch of the synchronization signal. In general, since the clamp pulse is located at the back porch of the sync signal, the timing comparator 24 detects the active portion of the level detection signal, which means the back porch of the sync signal, to generate a waveform as shown in FIG. Output

The clamp pulse output unit 25 receives the level detection signal of the back porch portion output from the timing comparator 24 to generate a clamp pulse as shown in FIG. 3 (d) to the video preamplifier 12. Output

As described above, the present invention can generate accurate clamp pulse even when a binary level synchronization signal or a third level synchronization signal is input, so that the present terrestrial broadcasting can be viewed through a next-generation high-definition television. It is effective to maximize the convenience of users at low cost.

Claims (2)

A video preamplifier for signal processing and amplifying R, G, and B video signals based on a blanking pulse and a clamp pulse, and a video amplifying the R, G, B video signals amplified by the video preamp to a display device. In a high definition television comprising an output lamp, A level detector for outputting at least one level detection signal in a pedestal level section of the video signal; A synchronization signal processing unit which receives a horizontal synchronization signal and a video signal and scans a sublevel section of the synchronization signal to output a synchronization detection signal; A timing comparison unit comparing the timing of the at least one level detection signal with the synchronization detection signal and outputting a level detection signal of the back porch portion; And And a clamp pulse output unit for generating a clamp pulse included in the level detection signal period of the back porch portion output from the timing comparing unit and outputting the clamp pulse to the video preamplifier. The compatible clamp signal generation circuit of claim 1, further comprising an analog / digital converter configured to digitally convert the input video signal and output the digital signal to the level detector.