KR100287808B1 - Stacking method of semiconductor chip - Google Patents
Stacking method of semiconductor chip Download PDFInfo
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- KR100287808B1 KR100287808B1 KR1019980036556A KR19980036556A KR100287808B1 KR 100287808 B1 KR100287808 B1 KR 100287808B1 KR 1019980036556 A KR1019980036556 A KR 1019980036556A KR 19980036556 A KR19980036556 A KR 19980036556A KR 100287808 B1 KR100287808 B1 KR 100287808B1
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- semiconductor chip
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- semiconductor chips
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 129
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000003475 lamination Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 claims description 23
- 238000010030 laminating Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 238000007689 inspection Methods 0.000 description 10
- 238000012360 testing method Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/074—Stacked arrangements of non-apertured devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
개시된 내용은 검사된 반도체칩의 리드프레임을 변형시켜 적층하므로써 반도체칩을 효율적으로 적층할 수 있는 반도체칩의 적층방법에 관한 것이다. 본 발명의 적층방법은 반도체칩을 제작하고 검사한 후, 적층하고자 하는 일정수량의 반도체칩의 리드를 변형한 다음, 먼저 기판상부에 변형하지 않은 리드를 가진 반도체칩을 접합하고, 그 상부에 변형된 리드를 가진 반도체칩을 적층하는 단계로 수행된다. 따라서, 본 발명은 적층과정을 단순화하고 효율적으로 적층시키는 효과를 제공한다.The present disclosure relates to a stacking method of a semiconductor chip capable of efficiently stacking semiconductor chips by modifying and stacking lead frames of inspected semiconductor chips. In the stacking method of the present invention, after fabricating and inspecting a semiconductor chip, the lead of a predetermined number of semiconductor chips to be stacked is deformed, and then a semiconductor chip having an undeformed lead is first bonded on the substrate, and the upper part of the semiconductor chip is deformed. Stacking the semiconductor chips with the leads. Accordingly, the present invention provides the effect of simplifying and efficiently stacking the lamination process.
Description
본 발명은 반도체칩을 적층하는 방법에 관한 것으로, 특히 반도체칩을 다수로 적층하는 공정에 있어서 제작된 반도체칩을 검사한 다음, 리드프레임을 변형시켜 적층하므로써 반도체칩을 효율적으로 적층할 수 있는 반도체칩의 적층방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of stacking semiconductor chips. In particular, a semiconductor chip can be efficiently stacked by inspecting a semiconductor chip fabricated in a process of stacking a plurality of semiconductor chips and then deforming and stacking a lead frame. It relates to a stacking method of chips.
기술이 발달하고 전자기기들이 경박단소(輕薄短簫)화 됨에 따라, 좁은 공간내에 반도체칩을 효율적으로 실장하기 위한 패키지(package)기술이 주요 관심사가 되고 있다. 이에 따라 반도체칩을 복수로 적층하는 기술이 실용화되는 추세이다.As technology is developed and electronic devices are made light and small, package technology for efficiently mounting semiconductor chips in a narrow space has become a major concern. Accordingly, the technology of stacking a plurality of semiconductor chips has become a practical trend.
이하 도 1을 참조하여 종래 반도체칩 적층방법을 설명한다.Hereinafter, a conventional semiconductor chip stacking method will be described with reference to FIG. 1.
도시한 바와 같이, 종래의 적층방법은 크게 5단계로 구분할 수 있다. 제1리드 반도체칩 제작단계(S11)는 제1리드를 갖는 반도체칩(11)을, 제2리드 반도체칩 제작단계(S12)는 제2리드를 갖는 반도체칩(12)을 제작하는 단계이다. 그리고 제1검사단계(S13)는 제1리드 반도체칩(11)을, 제2검사단계(S14)는 제2리드 반도체칩(12)을 검사하는 단계이다. 적층단계(S15)는 검사단계(S13, S14)에서 양호한(good) 판정을 받은 반도체칩을 선별하여 적층하는 단계이다.As shown, the conventional lamination method can be largely divided into five steps. The first lead semiconductor chip manufacturing step S11 is a step of manufacturing a semiconductor chip 11 having a first lead, and the second lead semiconductor chip manufacturing step S12 is a step of manufacturing a semiconductor chip 12 having a second lead. In the first inspection step S13, the first lead semiconductor chip 11 is inspected, and in the second inspection step S14, the second lead semiconductor chip 12 is inspected. The stacking step S15 is a step of selecting and stacking semiconductor chips that have been judged good in the inspection steps S13 and S14.
두 개의 반도체칩(11, 12)에 있어서 바디(body; 111, 121)는 서로 같으나, 적층을 위해 리드프레임(112,122; 이하 `리드'라 함)은 서로 다르게 제작된다. 이 후, 제작된 반도체칩(11, 12)은 리드의 구조에 따라 해당 반도체칩을 검사하는 제1 및 제2 검사단계(S13,S14)를 거친다.Although the bodies 111 and 121 are the same in the two semiconductor chips 11 and 12, the lead frames 112 and 122 (hereinafter, referred to as “leads”) are manufactured differently for stacking. Thereafter, the fabricated semiconductor chips 11 and 12 go through first and second inspection steps S13 and S14 that inspect the semiconductor chip according to the structure of the lead.
적층단계(S15)는 검사단계(S13,S14)에서 정상으로 판정된 반도체칩을 선별하여 수행되는 데, 먼저 PCB(Printed Circuit Board, 인쇄회로기판)상부에 제1리드 반도체칩을 연결하고, 이 제1리드 반도체칩 상부에 각 리드들을 연결하여 적층하고자 하는 개수만큼 제2리드 반도체칩을 적층한다.The stacking step (S15) is performed by selecting the semiconductor chip determined to be normal in the inspection step (S13, S14), first connecting the first lead semiconductor chip on the PCB (Printed Circuit Board), The second lead semiconductor chips are stacked by the number of leads to be stacked by connecting the leads on the first lead semiconductor chip.
하지만 위와 같은 종래의 적층방법은, 제1리드 및 제2리드를 갖는 반도체칩을 서로 다른 설비에서 각각 제작해야 하는 문제점이 있다. 또한, 서로 다른 리드를 갖도록 제작된 반도체칩은 각각 다른 검사장비(tester)에서 검사를 수행해야 하는 번거로움이 있다. 이와 같이 제작단계 및 검사단계를 이중으로 수행하는 데에 장비의 문제, 각 단계의 중복에 따른 부수적인 과정 등 상당한 문제점이 있다.However, the conventional lamination method as described above has a problem in that semiconductor chips having a first lead and a second lead must be manufactured in different facilities. In addition, semiconductor chips fabricated to have different leads are cumbersome in that they must be inspected by different testers. As such, there are significant problems in the production and inspection steps, such as equipment problems, ancillary processes according to the overlap of each step.
따라서 본 발명의 목적은 전술한 문제점을 해결할 수 있도록, 한가지 형태의 리드프레임을 갖는 반도체칩을 제작하고 이를 검사한 후, 적층하고자 하는 일정수량 반도체칩의 리드를 변형하여 적층을 수행하는 반도체칩의 적층방법을 제공함에 있다.Accordingly, an object of the present invention is to fabricate a semiconductor chip having one type of lead frame and to inspect the same, and then to deform a predetermined amount of semiconductor chips to be stacked to perform stacking. The present invention provides a lamination method.
도 1은 종래 반도체칩 적층공정을 설명하기 위한 도면.1 is a view for explaining a conventional semiconductor chip stacking process.
도 2는 본 발명에 따른 반도체칩 적층방법을 설명하기 위한 도면.2 is a view for explaining a semiconductor chip stacking method according to the present invention.
도 3은 도 2의 반도체칩 제작단계에 대한 상세도.Figure 3 is a detailed view of the semiconductor chip manufacturing step of FIG.
도 4는 적층하기 위한 두 반도체칩의 핀구조도.4 is a fin structure diagram of two semiconductor chips for lamination;
도 5는 본 발명에 따른 리드의 적층부위에 대한 상세도.Figure 5 is a detailed view of the laminated portion of the lead in accordance with the present invention.
※ 도면의 주요부분에 대한 부호의 설명※ Explanation of code for main part of drawing
S11,S12 : 반도체칩 제작단계 S13,S14 : 검사단계S11, S12: Semiconductor chip manufacturing step S13, S14: Inspection step
S15 : 적층단계S15: lamination step
11 : 제1리드 반도체칩 12 : 제2리드 반도체칩11: first lead semiconductor chip 12: second lead semiconductor chip
S51 : 반도체칩 제작단계S51: semiconductor chip manufacturing stage
S511 : 다이제작단계 S512 : 본딩단계S511: die production step S512: bonding step
S513 : 몰딩 및 리드형성단계S513: molding and lead forming step
S52 : 시험검사단계 S53 : 리드변형단계S52: test inspection step S53: lead deformation step
S53 : 적층단계S53: lamination step
51,52 : 반도체칩51,52: Semiconductor Chip
501,502 : 반도체칩 리드 503 : 연결부501,502: semiconductor chip lead 503: connection part
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체칩의 적층방법은, (1) 반도체칩을 제작하는 단계; (2) 제1단계에서 제작된 반도체칩을 검사하는 단계; (3) 제2단계에서 검사한 반도체칩(들) 중 적층하고자 하는 일정수량 반도체칩의 리드를 변형하는 단계; 및, (4) 제2단계에서 검사된 양호한 반도체칩을 기판에 연결하고 기판에 연결된 반도체칩 상부에, 제3단계에서 변형시킨 리드를 갖는 반도체칩을 적어도 하나 이상, 반도체칩의 각 리드들을 서로 대응시켜 적층하는 단계에 의해 달성된다.Laminating method of a semiconductor chip according to the present invention for achieving the above object, (1) manufacturing a semiconductor chip; (2) inspecting the semiconductor chip fabricated in the first step; (3) deforming a predetermined number of leads of the semiconductor chip to be stacked among the semiconductor chip (s) examined in the second step; And (4) at least one semiconductor chip having the leads deformed in the third step on top of the semiconductor chip connected to the substrate by connecting the good semiconductor chip examined in the second step to each other, and each lead of the semiconductor chip being By correspondingly laminating.
이하, 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명한다. 도 2는 본 발명에 따른 반도체칩 적층방법을 도시한 것이다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 2 illustrates a semiconductor chip stacking method according to the present invention.
도시한 바와 같이, 본 발명의 적층방법은 크게 4단계로 구분할 수 있다. 반도체칩 제작단계(S51)는 적층하기 위한 반도체칩을 제작하는 단계이다. 본 발명의 적층방법에 따라 적층되는 반도체칩은 핀(pin)의 배열구조에 차이가 있으며, 핀배열의 차이는 뒷부분에서 자세히 설명한다. 제작된 반도체칩(51)은 본래의 기능을 제대로 수행하는 지 등을 시험하고 검사하는 시험검사단계(S52)를 거친다. 이 후 적층하고자 하는 일정수량의 반도체칩은 리드변형단계(S53)에서 리드를 변형한다. 그리고 마지막으로, 적층단계(S54)에서는 PCB기판 상부에 먼저 변형되지 않은 리드를 가진 반도체칩을 연결하고, 그 상부에 변형된 리드를 가진 반도체칩을 원하는 수량만큼 적층하게 된다.As shown, the lamination method of the present invention can be largely divided into four steps. The semiconductor chip manufacturing step S51 is a step of manufacturing a semiconductor chip for lamination. The semiconductor chips stacked according to the lamination method of the present invention have a difference in the arrangement of the pins, and the difference in the pin arrangement will be described in detail later. The manufactured semiconductor chip 51 is subjected to a test inspection step (S52) for testing and inspecting whether the original function is properly performed. After that, a predetermined number of semiconductor chips to be stacked are deformed in the lead deformation step S53. And finally, in the stacking step (S54), the semiconductor chip having unmodified leads is first connected to the upper part of the PCB, and the semiconductor chip having the deformed lead is stacked as many as desired.
각 단계를 자세히 설명하면, 반도체칩 제작단계(S51)에서는 핀(pin)배열이 다른 반도체칩을 제작하게 된다. `리드'(혹은 `리드프레임'이라고도 함)와 `핀'은 반도체칩 제작공정에서 몰딩(molding)하기 전후의 차이가 있는 것으로, 실제는 서로 같은 구조물을 가리킨다. 하지만 본 발명의 방법에 의해 적층되는 반도체칩은, 종래 기술과 달리 반도체칩 제작단계(S51)에서 리드의 형태가 동일하게 제작된다. 그러나, 반도체칩 제작단계(S51)에서는 리드의 형태가 동일할지라도 핀배열에 차이가 있는 반도체칩을 제작한다. 이는 적층 후 동작을 고려한 것이다.Each step will be described in detail. In the semiconductor chip manufacturing step S51, a semiconductor chip having a different pin arrangement is manufactured. 'Lead' (also called 'lead frame') and 'pin' are the differences before and after molding in the semiconductor chip manufacturing process, and actually refer to the same structure. However, the semiconductor chips stacked by the method of the present invention, unlike the prior art, the same shape of the lead is produced in the semiconductor chip manufacturing step (S51). However, in the semiconductor chip manufacturing step (S51), even though the shape of the lead is the same, a semiconductor chip having a difference in pin arrangement is manufactured. This takes into account the post-lamination operation.
반도체칩 제작단계(S51)는 도 3에 자세히 나타내었다. 도 3은 반도체칩 제작단계를 상세하게 나타낸 도면이다.The semiconductor chip manufacturing step S51 is shown in detail in FIG. 3. 3 is a view showing a semiconductor chip manufacturing step in detail.
도 3에 도시한 바와 같이, 적층하기 위한 반도체칩은 핀(리드)배열이 서로 다르게 제작된다. 본 발명의 설명에서는 2개의 64M SDRAM을 이용하여 적층하는 방법을 일예로 든다.As shown in Fig. 3, the semiconductor chips for lamination are fabricated with different fin (lead) arrangements. In the description of the present invention, a method of stacking using two 64M SDRAM as an example.
먼저 다이(die)를 제작하는 다이제작단계(S511)가 수행된다. 다이는 반도체칩의 실질적인 기능을 수행하는 집적회로가 웨이퍼(wafer)에 제작된 것을 의미한다.First, a die fabrication step S511 of manufacturing a die is performed. Die means that an integrated circuit that performs a substantial function of a semiconductor chip is fabricated on a wafer.
두번째 본딩단계(S512)에서는 다이의 핀(리드)배열을 변경하며 본딩(bonding)을 하게 되는 데, 다수의 핀 중 특히 칩선택단자(Chip Selection)의 위치를 NC(No Connection, 미연결단자;사용하지 않음)단자에 번갈아 연결하는 특징이 있다. 이러한 공정은 한국특허출원 제98-29723호(명칭;적층패키지를 위한 반도체칩 및 반도체칩의 적층패키지 방법)에 자세히 기재되어 있다. 여기서 A형 반도체칩은 CS단자가 19번 핀이고 B형 반도체칩은 CS단자가 36번 핀이다. 이 후 몰딩하여 리드(핀)를 형성하기 위해 몰딩 및 리드형성단계(S513)단계를 수행하여, 서로 다른 핀 배열을 갖는 A형 및 B형 반도체칩을 완성한다.In the second bonding step (S512), bonding is performed while changing the pin (lead) arrangement of the die. Among the plurality of pins, in particular, the position of the chip selection terminal (Chip Selection) is NC (No Connection); There is a feature to connect alternately to the terminal. Such a process is described in detail in Korean Patent Application No. 98-29723 (name: semiconductor chip for lamination package and lamination package method of semiconductor chip). In this case, the CS terminal has pin 19 and the CS terminal has pin 36. Thereafter, molding and lead forming steps (S513) are performed to mold to form leads (fins), thereby completing A-type and B-type semiconductor chips having different fin arrangements.
도 4a 및 도 4b는 두가지 A형 및 B형 반도체칩의 핀 배열을 설명하기 위한 도면이다.4A and 4B are diagrams for describing pin arrangements of two A-type and B-type semiconductor chips.
도시한 바와 같이, 본 발명에서 예로 들고 있는 두 반도체칩(A형,B형)은 다수의 기능을 수행하기 위한 핀들을 구비하고 있으며, 도 4a의 A형 반도체칩과 도 4b의 B형 반도체칩의 각 핀들의 위치는, 19번 및 36번 핀의 위치를 제외하고는 모두 같다. 즉, A형 반도체칩에서 19번의 CS(Chip Selection)핀은, B형 반도체칩에서는 36번 핀으로 변경되어 있다. NC핀은 반도체칩내부의 다이와 연결되지 않은 것을 나타낸다. CS핀은 반도체칩이 동작하도록(enable) 선택하기 위한 핀이다. 즉, 각 반도체칩의 CS핀에 신호가 인가되어야 해당 반도체칩이 동작가능상태로 되는 것이다.As shown, the two semiconductor chips (types A and B) shown in the present invention are provided with pins for performing a plurality of functions. The type A semiconductor chip of FIG. 4A and the type B semiconductor chip of FIG. 4B are illustrated. The positions of the pins in are the same except for the positions of pins 19 and 36. That is, the 19th CS (Chip Selection) pin of the A type semiconductor chip is changed to the 36th pin of the B type semiconductor chip. The NC pin is not connected to the die inside the semiconductor chip. The CS pin is a pin for selecting a semiconductor chip to be enabled. That is, a signal is applied to the CS pin of each semiconductor chip to make the semiconductor chip operable.
이렇게 제작·완성된 반도체칩은 도 2에 도시한 바와 같이, 시험검사단계(S52)가 수행된다. 이 단계(S52)는 제작되어 완성된 반도체칩이 정상인지를 판별해 내기 위한 과정이다.The semiconductor chip thus manufactured and completed is subjected to a test inspection step S52, as shown in FIG. This step S52 is a process for determining whether the manufactured and completed semiconductor chip is normal.
이 후, 정상으로 판정된 일정수량의 반도체칩은 적층하기 위해 리드를 변형시키는 리드변형단계(S53)가 수행된다. 도시한 바와 같이 적층단계(S54)에서 PCB기판에 최초로 접합시키는 가장 하부의 반도체칩(51)은 반도체칩 제작단계(S51)에서 제작된 형태대로 리드를 변형하지 않고 그대로 접합한다. 그러나 두 번째 층부터 적층시키는 반도체칩(52)은 리드변형단계(S53)을 거친다. 이 리드변형단계(S53)는 반도체칩 제작단계(S51)에서 형성시킨 리드를, 적층이 용이하도록 `ㄱ'자 형태로 변형하는 단계이며, 적층단계(S54)에서 적층될 상태를 감안하여 변형후의 리드길이를 조절하고 적층이 용이하도록 리드를 다듬는 과정 등이 포함된다.Thereafter, the lead deformation step S53 of deforming the leads for stacking the predetermined number of semiconductor chips as normal is performed. As shown, the lowermost semiconductor chip 51 that is first bonded to the PCB substrate in the lamination step S54 is bonded as it is without deformation in the shape produced in the semiconductor chip manufacturing step S51. However, the semiconductor chip 52 stacked from the second layer is subjected to the lead deformation step S53. The lead deformation step S53 is a step of deforming the lead formed in the semiconductor chip manufacturing step S51 into a letter 'A' shape for easy lamination, and considering the state to be stacked in the lamination step S54, This includes adjusting the lead length and trimming the lead to facilitate lamination.
적층단계(S54)에서는 PCB기판 상부에 리드를 변형하지 않은 반도체칩(51)을 맨 하부층에 접합시키고 이 상부에는 변형된 리드를 갖는 반도체칩(52)들을 필요한 개수만큼 적층한다.In the stacking step S54, the semiconductor chip 51 without the lead is deformed is bonded to the lowermost layer on the upper part of the PCB, and the semiconductor chip 52 having the deformed lead is stacked on the upper part as many times as necessary.
종래의 기술과 달리, 본 발명의 적층방법은 리드의 길이에 특징이 있다. 이 특징은 도 5에 도시하였다. 도 5는 반도체칩 리드길이 변형 및 적층공정을 자세히 설명하기 위한 도면이다.Unlike the prior art, the lamination method of the present invention is characterized by the length of the lead. This feature is shown in FIG. 5 is a view for explaining the semiconductor chip lead length deformation and lamination process in detail.
도시한 바와 같이, 도 5a는 적층하고자 하는 반도체칩들을 적층할 지점에 위치시킨 상태를, 도 5b는 상부 및 하부반도체칩의 리드가 연결된 상태를 나타낸 것이다. 도면에서 501은 하부 반도체칩의 리드프레임을 나타내고, 502는 상부 반도체칩의 리드프레임 끝단을 나타내며, 503은 상부 및 하부 반도체칩의 연결부를 나타낸 것이다.As shown, FIG. 5A illustrates a state in which semiconductor chips to be stacked are positioned at positions to be stacked, and FIG. 5B illustrates a state in which leads of upper and lower semiconductor chips are connected. In the drawing, 501 denotes a lead frame of the lower semiconductor chip, 502 denotes a lead frame end of the upper semiconductor chip, and 503 denotes a connection portion of the upper and lower semiconductor chips.
상부 및 하부 반도체칩의 리드(501,502)를 연결하면 도 5b에 도시한 바와 같은 연결부(503)가 형성된다. 이 연결부는 볼(ball)과 같은 모양으로 형성되는 데, 이는 리드프레임간의 간격 등에 의해 장력을 받아서 자연적으로 형성되는 것으로 리드프레임의 간격이 중요한 작용을 한다.When the leads 501 and 502 of the upper and lower semiconductor chips are connected, the connecting portion 503 as shown in FIG. 5B is formed. The connection part is formed in a ball-like shape, which is naturally formed under tension by the gap between the lead frames, and the gap between the lead frames plays an important role.
즉, 종래에는 적층하기 전에 적층할 지점을 맞추어 상하부 반도체칩들을 위치시키면, 상부반도체칩의 리드(502)길이가 너무 길거나 또는 긴 리드들이 많아서 하부반도체칩의 리드(501)에 닿게되면, 솔더링(soldering)으로 각 리드들을 연결할 때 흔들림 등에 의해 상부 및 하부반도체칩의 리드들을 정확히 유지시키기 어려웠고, 적층된 후의 높이 및 평형상태의 편차 등이 크게 발생했으며, 또 연결된 겉모양과 달리 각 리드들이 내부적·전기적으로 잘 연결되었는 지를 알 수 없었다.That is, conventionally, if the upper and lower semiconductor chips are positioned in accordance with a point to be stacked before stacking, when the length of the lead 502 of the upper semiconductor chip is too long or there are many leads, the lead 501 of the lower semiconductor chip is soldered. When connecting the leads by soldering, it was difficult to accurately maintain the leads of the upper and lower semiconductor chips by shaking, etc., and the deviation of the height and equilibrium state after stacking occurred greatly. It was not known whether it was connected electrically.
하지만 본 발명에서는 리드들을 다듬을 때 상하부 반도체칩간 리드들의 이격간격을 미소하게 짧게 한 후 전기를 잘 통하게 하는 물질로 솔더링(soldering)하여 연결하므로써, 자연적으로 연결볼이 발생함과 동시에 상하부의 리드들도 내부적으로 그리고 전기적으로 잘 연결되도록 한 것이다.In the present invention, however, the lead gap between the upper and lower semiconductor chips is slightly shortened when soldering the leads, and then connected by soldering with a material that conducts electricity well. It is well connected internally and electrically.
본 발명의 방법은 설명에서 예시한 TOSP형태의 리드를 가진 반도체칩들을 적층하는 것에 국한되지 않고 다른 형태의 리드들을 가진 반도체칩들도 적용할 수 있으며, 또한 위와 같이 2층으로 적층된 반도체칩상부에 계속 적층하려면 리드가 변형된 반도체칩을 상부에 계속적으로 적층하면 된다.The method of the present invention is not limited to stacking semiconductor chips having a TOSP type lead as illustrated in the description, and may also apply semiconductor chips having other types of leads. In order to continue stacking on the semiconductor chip, the lead-deformed semiconductor chip may be continuously stacked on top.
상술한 바와 같이 본 발명은, 하나의 리드프레임 형태로 제작된 반도체칩을 제작하고 검사한 후, 양호한 반도체칩 중 적층하기 위한 반도체칩의 리드를 변형하여 적층하므로써, 적층과정을 단순화하여 효율적으로 적층시키는 효과를 제공한다.As described above, the present invention manufactures and inspects a semiconductor chip fabricated in the form of a single lead frame, and then deforms and stacks the semiconductor chip leads for stacking among the good semiconductor chips, thereby simplifying the stacking process and efficiently stacking them. It provides an effect.
Claims (5)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980036556A KR100287808B1 (en) | 1998-09-04 | 1998-09-04 | Stacking method of semiconductor chip |
| JP10374773A JP3035534B2 (en) | 1998-07-23 | 1998-12-28 | Laminated package and method of laminating the same |
| US09/232,026 US6242285B1 (en) | 1998-07-23 | 1999-01-15 | Stacked package of semiconductor package units via direct connection between leads and stacking method therefor |
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| KR1019980036556A KR100287808B1 (en) | 1998-09-04 | 1998-09-04 | Stacking method of semiconductor chip |
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| KR20000018790A KR20000018790A (en) | 2000-04-06 |
| KR100287808B1 true KR100287808B1 (en) | 2001-04-16 |
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| JPH07235636A (en) * | 1994-02-21 | 1995-09-05 | Fujitsu Ltd | Semiconductor device and laminated structure thereof |
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| JPH07235636A (en) * | 1994-02-21 | 1995-09-05 | Fujitsu Ltd | Semiconductor device and laminated structure thereof |
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