KR100283886B1 - Display of video graphics array - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device of a video graphics array, which is to divide and display information of a screen displayed on a monitor horizontally or vertically.

The present invention as described above comprises a monitor controller for generating a screen control signal including a register required for monitor control, and a screen division point detecting means for detecting a screen split point horizontally / vertically in accordance with the screen split signal generated by the monitor controller. And an address selection control means for generating an address selection control signal according to the result signal obtained by the screen division point detection means and a screen division signal generated by the monitor controller, and generated by the monitor controller according to the control signal obtained by the address selection control means. A memory address selecting means for selecting a predetermined address and an address for loading an address selected by the memory address selecting means according to control signals generated by the address selection control means and a monitor controller and finally generating an address for accessing the display memory means. It is achieved by constituted by any generation means.

Description

Display of video graphics array

1 is a block diagram of a display device of a conventional video graphics array.

2 is a configuration diagram showing the main portion of FIG. 1 in more detail.

3 is an explanatory diagram showing a horizontal division display according to FIG.

4 is a configuration diagram of a display device of a video graphics array of the present invention.

FIG. 5 is a detailed view of the screen dividing point detecting means of FIG.

6 is a detailed view of the address selection control means of FIG.

7 is a detailed view of the memory address selecting means of FIG.

FIG. 8 is an exemplary view illustrating split screen display according to FIG. 4.

8 (a) is a diagram showing a horizontal division display of the screen,

8 (b) shows a vertical display of the screen.

9 is an output timing diagram of FIGS. 4 and 7 in the horizontal division display mode.

10 is an output timing diagram of FIGS. 4 to 7 in the vertical division display mode.

* Explanation of symbols for main parts of the drawings

200: monitor controller 201: screen dividing point detection means

202: address selection control means 203: memory address selection means

204: address generating means

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to screen display in a video graphic array (VGA), which is one of the graphics subsystems. In particular, the present invention relates to a video for displaying information of a screen displayed on a display monitor by dividing it horizontally or vertically. A display device of a graphic array.

In general, the video graphics array, which is one of the graphics subsystems, has registers necessary to reduce the timing of the display monitor's horizontal synchronization signal, vertical synchronization signal, blank area, and display area.

The registers are compatible with the registers within each manufacturer's monitor controller (CRT Controller) chip used to control the CGA, MDA and Hercules boards. More special registers are used.

As such, a display apparatus of a conventional video graphic array generates an address at an allotted time and outputs information to be displayed on a screen and records it on a recording medium, as shown in FIGS. 1 and 2 of the accompanying drawings. A start address register for generating an address to generate the screen information stored on the recording medium and displaying it on the screen at a predetermined time, and outputting a vertical / horizontal synchronization signal (HS) and various control signals; And a monitor controller 101 having a line comparison register, a vertical line counter means 107 for continuously counting a horizontal synchronization signal HS generated by the monitor controller 101, and the vertical line counter means 107. ) And the line address value that specifies the position of the second screen on the screen generated by the line comparison register of the monitor controller 101. And a start address value for detecting the first means of the horizontal scan line generated in the start address register by detecting the vertical synchronizing signal VS generated by the monitor controller 101 and the comparing means 108 generating the resultant signal. And the address generating means 102 for counting the count vent CVNT generated by the monitor controller 101, increasing the address, outputting the address, and clearing the count value according to the result signal obtained by the comparing means 108. And display memory means 103 for outputting the screen data stored in the corresponding time by the address obtained by the address generating means 102, and generating characters corresponding to the data generated by the display memory means 103. The character generating means 104 and the character generating means 104 in accordance with a control signal generated by the monitor controller 101. The attribute processing means 105 for processing the written characters as attributes and outputting the dot information as dot information and the horizontal / vertical synchronization signal HS (VS) generated by the monitor controller 101. The display monitor 106 which displays the dot information of the 105 on a screen is comprised.

In this way, the screen display apparatus of the conventional video graphic array configured as shown in FIG. 1 first generates an address through the address generating means 102 at the time when the central processing unit 100 is allocated, thereby displaying the display memory means 103. After recording the information to be displayed on the screen, the monitor controller 101 generates an address at the time when it is allocated, and inputs the information stored in the display memory means 103 into the character generating means 104.

The character generating means 104 processes the character information to be displayed on the actual screen according to the information input from the display memory means 104 and inputs it to the attribute processing means 105.

The attribute processing means 105 processes the input character information as an attribute by the control signal of the monitor controller 101 and inputs it to the display monitor 106, the display monitor 106 of which the monitor controller 101 Character information processed in accordance with the horizontal / vertical synchronization signal (HS) (VS) input from the display is displayed on the screen.

In this way, what information is displayed on which position of the screen is dependent on the address generating means 102 that determines what information the monitor controller 101 reads from among the information stored in the display memory means 103.

In CGA and MDA, which did not have a screen division function, addresses increased in the order that the monitor scans the screen using the start address register in the monitor controller 101. Generates.

The screen splitting function is a function of how to generate this address, and the concept of the method is shown in FIG.

That is, in FIG. 3, the screen of the display monitor 106 is horizontally divided into two parts. In the upper left corner of the first screen A, information in the display memory means 103 designated by the start address register is displayed. The information in the display memory means 103 is displayed at the left corner of the two screens B. FIG.

The operation of such a function will be described in detail with reference to FIG. 2. The monitor controller 101 generates a horizontal synchronization signal HS and a vertical synchronization signal VS for controlling a screen division display function. As shown in FIG. 3 at the time of initialization, the line comparison register specifying the position of the start address value D1, which is a signal of the start address register specifying the first position of the first horizontal scanning line of the display monitor 106 screen, and the position of the second screen on the screen. The user programmed the line address value D2 in the monitor controller 101 in advance.

Thus, the horizontal / vertical synchronization signal HS (VS) and the count vent CVNT are generated in the monitor controller 101, and the start address value D1 and the line address value D2 are generated in the start address register and the line comparison register. When generated, the address generator 102 detects the vertical synchronizing signal VS generated from the monitor controller 101, loads the start address value D1 of the start address register, and counts according to the input count vent CVNT. Will start.

Meanwhile, the vertical line counter means 107 counts the horizontal synchronizing signal HS generated by the monitor controller 101 and supplies the count value D3 to the comparing means 108, and the comparing means 108. Compares the line address value D2 generated in the line comparison register of the monitor controller 101 with the coefficient value D3 for the line address obtained from the vertical line counter means 107, and equals the equal signal Equal. Is generated and input to the clear terminal of the address generating means 102.

Accordingly, the address generating means 102 counts according to the count vent CVNT of the monitor controller 101, and when the equalizing signal is supplied from the comparing means 108, clears the counted value and outputs the memory. The address signal D4 is made " 0 ", then counted according to the count vent CVNT generated from the monitor controller 101, and the memory address signal D4 is increased to be input to the display memory means 103. If the above process is repeatedly performed by searching for the vertical synchronization signal VS, as described above, the information stored in the display memory means 103 is changed according to the change of the output memory address signal D4. The generating means 104 and the attribution processing means 105 are sequentially displayed on the screen of the display monitor 106, and the contents of the screen are divided into two parts as shown in FIG.

However, in the display apparatus of the conventional video graphic array, in the method of horizontally dividing the screen, the information displayed on the second screen is always the first address ("0") of the display memory means at the position designated by the line comparison register. Displayed from the information in the address, the soft application programmer using the video graphics array has no way of displaying the information of the other area on the second screen. There was a problem in the use that the number cannot be divided and the screen cannot be divided vertically, and only the horizontal division is displayed.

Accordingly, an object of the present invention is to provide a display device of a video graphics array so as to divide and display information of a screen displayed on a display monitor horizontally or vertically according to a user's selection by using hardware in view of such a conventional problem. In providing.

As a means for achieving the object of the present invention, a monitor controller for generating a signal for screen control by including at least one or more registers necessary for the control of the monitor, a screen split signal generated by the monitor controller and horizontal / vertical Screen division point detection means for detecting a screen division point horizontally / vertically in accordance with a synchronization signal, a result signal detected by the screen division point detection means, and a maximum scan line value and horizontal synchronization of a character size generated by the monitor controller An address selection control means for generating and outputting an address selection control signal according to a signal and a screen division signal, and an address selection control signal according to a horizontal / vertical screen division mode obtained by the address selection control means. Memory address selection means for selecting an address And an address generating means for loading an address selected by the memory address selecting means according to the control signals generated by the address selection control means and the monitor controller and finally generating an address for accessing the display memory means. When described in detail with reference to the accompanying drawings of the present invention.

4 is a block diagram of a display device of a video graphics array according to the present invention. As shown therein, a register required for monitor control, a vertical division address register for horizontal and vertical division display, a horizontal division address register, and a character clock comparison register are shown in FIG. And a monitor controller 200 for generating a signal for screen control, and a screen split mode signal S1, a horizontal sync signal S3, a character clock S2, and a line comparison generated by the monitor controller 200. Screen splitting point detecting means 201 for detecting a screen splitting point in the horizontal / vertical direction and outputting the resultant signal S5 according to the value D8 of the register and the value D6 of the character clock comparison register; Result signal S5 according to the horizontal / vertical screen division obtained by the division point detecting means 201 and the maximum scan line value D7 and the number of the character size generated by the monitor controller 200. Horizontal / vertical selection control signal (S6) (S7), maximum scan comparison event signal (S8) according to the flat synchronization signal (S3), the screen division mode signal (S1), the character clock (S2), and the vertical synchronization signal (S4). And the address selection control means 202 for generating and outputting the load signal S9 and the control signal S6-S8 according to the horizontal / vertical screen division mode supplied from the address selection control means 202. Memory address selecting means 203 for selecting the address values D1-D6 generated by the monitor controller 200 and memory address selecting means in accordance with the load signal S9 generated by the address selection controlling means 202. An address that loads the address signal A3 selected at 203, counts the address A3 according to the character clock S2 generated by the monitor controller 200, and finally accesses the display memory means (not shown). It consists of the address generating means 204 which generates (A4).

As shown in FIG. 5, the screen dividing point detecting unit 201 is a line counter unit 201a which counts the number of lines of the horizontal synchronization signal S3 generated and input by the monitor controller 200. And a character counter 201b for counting the number of times the character clock S2 generated and input by the monitor controller 200 and the screen division mode signal S1 generated by the monitor controller 200. A first selector 201c for selectively outputting the output count value of the line counter 201a and the character counter 201b, and the value D8 of the line comparison register generated and input by the monitor controller 200 according to the present invention. ) And a second selector 201d for selectively outputting the value D6 of the character clock comparison register according to the screen division mode signal S1, and the first and second selector 201c and 201d. Obtained line count and line comparison register value or character clock value Comparing the value of the character clock compare register each to constitute a resulting signal (S5) to the first comparing unit (201e) for input to the address selection control unit (202).

In the above description, the address selection control means 202 divides the horizontal / vertical synchronization signals S3 and S4 input according to the screen division mode signal S1 generated by the monitor controller 200 as shown in FIG. The third and fourth selection units 10 and 13 and the oragate for generating and loading the load signal S9 and the horizontal selection control signal S6 by selecting and ORing the result signal S5 of the point detecting means 201. 11) and a horizontal selection control generation unit 202a composed of the first flip-flop 12 and the vertical synchronization signal S4 and the horizontal selection control according to the screen division mode signal S1 generated by the monitor controller 200. Selects and outputs the logical sum signal of the generator 202a, and compares the maximum synchronization line signal S8 and the maximum scan line value D7 of the character size with the maximum scan comparison event signal S8 and the vertical selection control signal A row scan counter 14, a second comparing section 15, a fifth selecting section 16, and a character line for inputting S7 to the memory address selecting means 203; Constitute a cloud taboo 17 and the decoder unit 18, the vertical selection control generation unit (202b) made of a.

In addition, the memory address selection means 203 is a horizontal address value (D2) and a vertical address value (D1) (D3) input in accordance with the control signal (S6-S8) obtained from the address selection control means (202). ), The horizontal / vertical address generator 203a, which adds and selectively controls the horizontal display enable register value D5 and the character comparison register value D6 and outputs the horizontal address signal A1 and the vertical address signal A2. And the horizontal and vertical address signals A1 and A2 obtained by the horizontal / vertical address generator 203a in accordance with the screen division mode signal S1 of the monitor controller 200 to generate the address generating means 204. And a horizontal / vertical address selection unit 203b to be input.

In the above, the horizontal / vertical address generator 203a is fed back to the value D4 obtained by summing the value of the start address register and the offset register from the monitor controller 200 as shown in FIG. The obtained value is added through the first adder 20 and the value of the vertical / horizontal address selected by the sixth selector 21 according to the added signal and the horizontal selection control signal S6 of the address selection control means 202. (D1) and (D2) are selected through the seventh selector 22 according to the vertical selection control signal S7, and the selected signal through the second flip-flop 23 is the maximum of the address selection control means 202. A horizontal address selector 203a1 for synchronizing with the scan comparison event signal S8 and outputting it to the horizontal address A1, a value D1 (D3) of the vertical address generated by the monitor controller 200, and a horizontal display in Compute the value of the enable register (D5) and the character clock compare register (D6) Second, third adders 24, 28, subtractors 27, and eighth to comparatively select and generate vertical addresses A2 by the control signals S6-S8 of the high address selection control means 202. The vertical address selector 203a2 includes the tenth selectors 25, 29, 31, and the third and fourth flip-flops 26, 30.

Thus, the operational effects of the present invention configured as described in detail with reference to FIGS. 4 to 10 as follows.

The horizontal and vertical address values D1, D2, and D3 from the monitor controller 200, the sum of the latch values of the start address register and the offset register value, and the horizontal display enable register. A value D5, a value D6 of the character clock comparison register, a maximum scan line value D7 of the character size indicating the number of lines of character size, and a value D8 of the line comparison register are generated and output. In addition, a vertical synchronization signal S4 as shown in FIG. 9A, a horizontal synchronization signal S3 as shown in FIG. 10B, and a character clock S2 are generated to select the screen division point detecting means 201 and address selection. Input to the control means 202, memory address selection means 203.

The line counter unit 1 of the screen division point detecting unit 201 has a horizontal synchronization signal S3 generated and input from the monitor controller 200 and counts how many times the current line is. (3), the character counter unit 2 counts the number of times the character clock S2 generated and input from the monitor controller 200 and inputs it to the first selection unit 3 described above. do.

In addition, the value D8 of the line comparison register and the value D6 of the character clock comparison register generated and output from the monitor controller 200 are input to the second selector 4.

At this time, the screen split mode signal S1 for splitting the screen horizontally and vertically from the monitor controller 200 is generated with a high potential, that is, a horizontal split display mode, so that the first and second screen splitting point detecting means 201 can be used. When input to the second selector (3) (4), the first selector (3) selects the value counted by the line counter unit (1) and inputs it to the first comparison unit (5), the second The selection unit 4 selects the value D8 of the line comparison register generated from the monitor controller 200 by the screen division mode signal (horizontal division display mode) S1 and inputs it to the first comparison unit 5. Done.

The first comparator 5 of the screen splitting point detecting means 201 is a current line value and a line by the horizontal synchronous signal S3 selected and input from the first and second selection parts 3 and 4. Compared with the value D8 of the comparison register, if the values are the same, the high-level equal signal Equal (S5) as shown in (b) of FIG. 9 is generated to generate the horizontal selection control generation unit of the address selection control means 202 ( 202a).

The third selection unit 10 configured in the horizontal selection control generating unit 202a of the address selection control unit 202 is generated by the monitor controller 200 and inputted by the screen division mode signal (horizontal division mode S1). When the vertical synchronization signal S4 is selected and input to one input terminal of the oragate 11, the oragate 11 is a high potential input from the first comparator 5 of the screen splitting point detecting means 201. The equal signal S5 and the vertical synchronizing signal S4 are logically combined to be input to the fifth selector 16 of the fourth selector 13 and the vertical select control generator 202b, and the first flip-flop 12 ).

The first flip-flop 12 generates the horizontal selection control signal S6 as shown in (c) of FIG. 9 as the input terminal of the output signal of the ora gate 11 and inputs it to the memory address selecting means 203. Done.

In addition, the fourth selection unit 13 of the horizontal selection control generation unit 202a blocks the horizontal synchronization signal S3 by the screen division mode signal S1 generated by the monitor controller 200 and the oragate 11. Selects the signal OR and inputs it to the address generating means 204 as a load signal S9 as shown in FIG. 9 (difference), and the fifth selecting part 16 of the vertical selection control generating part 202b monitors. Blocks the vertical synchronization signal S4 input by the screen division mode signal S1 generated by the controller 200 and selects the OR signal from the OA gate 11 to clear the character line counter 17. do.

Accordingly, the vertical selection control signal S7 as shown in FIG. 9 (bar) outputted through the character line counter unit 17 and the decoder unit 18 is not inputted to the memory address selection unit 203, and the vertical selection control generation unit The count value of the horizontal synchronous signal S3 through the row scan counter 14 of 202b and the maximum scan line value D7 of the character size are compared through the second comparator 15 so as to be equal to each other. As shown in FIG. 5E, the maximum scan comparison event signal S8 is input to the memory address selecting means 203. FIG.

The memory address selection means 203 generates an address according to the horizontal selection control signal S6, the vertical selection control signal S7 and the maximum scanning event signal S8 generated by the address selection control means 202. Selects the memory address to be loaded.

That is, the sixth selector 21 of the horizontal address generator 203a1 configured in the memory address selector 203 is configured to generate the ninth selected signal according to the horizontal select control signal S6 generated by the horizontal select control generator 202a. As shown in (a) of FIG. 7, the input value D1 and the value D2 of the horizontal address are periodically selected and input to the seventh selector 22, and the first adder 20 is a monitor controller. The value D4 obtained by adding the latch value of the start address register from 200 to the offset register is added to the seventh selector 22 by adding the horizontal address A1 fed back and input.

The seventh selector 22 vertically selects the values D1 and D2 of the added value added from the first adder 20 and the vertical / horizontal address values selected and input from the sixth selector 21. The vertical selection control signal S7 of the control generator 202b selects and inputs the second flip-flop 23 as shown in FIG.

The second flip-flop 23 is a maximum scanning comparison event signal (S8) of the vertical selection control generation unit 202b with a value selected and input from the seventh selection unit 22 as shown in FIG. In synchronism with FIG. 9, a horizontal address A1 as shown in FIG. 9A is generated and input to the horizontal / vertical address selection unit 203b.

The subtractor 27 of the vertical address generator 203a2 configured in the memory address selector 203 is configured to compare the value D5 of the vertical display enable register generated from the monitor controller 200 with the character clock comparison register. The difference value D6 is subtracted and the difference value is input to the third adder 28. The second adder 24 and the third adder 28 correspond to the value D6 of the character clock comparison register and the ( G), the value output from the third flip-flop 26 and the difference value of the subtractor 27 and the value output from the fourth flip-flop 30, as shown in FIG. The data is added to the eighth and ninth selectors 25 and 29.

The eighth selector 25 of the vertical address generator 203a2 vertically selects an input value added from the second adder 24 and a value D1 of the vertical address input from the monitor controller 200. According to the control signal S7, as shown in FIG. 10 (e), it is periodically selected and input to the third flip-flop 26, and the ninth selector 29 is added from the third adder 28. The fourth flip-flop 30 is periodically selected by selecting the input value and the value D3 of the vertical address input from the monitor controller 200 as shown in FIG. 10 (bar) according to the vertical selection control signal S7. Will be entered.

The third and fourth flip-flops 26 and 30 are configured by the eighth and ninth selectors 25 and 29 to synchronize the input values with the maximum scan comparison event signal S8, respectively. (G) Input the same output value to the tenth selector 31, and the tenth selector 31 is configured according to the horizontal select control signal S6 of the horizontal select control generator 202a. 3, the value output from the fourth flip-flop 26 (30) is selected, and the vertical address A2 as shown in FIG. 10 (difference) is input to the horizontal / vertical address selection unit 203b.

The horizontal / vertical address generator 203b of the memory address selection means 203 generates a horizontal / vertical address when the screen division mode signal S1 from the monitor controller 200 is high potential, that is, the horizontal division display mode. The horizontal address A1 generated by the unit 203a is selected, and when the screen division mode signal S1 is low potential, that is, in the vertical division display mode, the vertical address A2 is selected and input to the address generating means 204. Done.

In this case, in the horizontal division display mode, the address generating means 204 has an address A3 selected and input from the horizontal / vertical address generating unit 203b to actually access the display memory means ( A4) is generated. If the load signal S9 generated by the horizontal selection control generation unit 202a of the address selection control unit 202 is high potential, the address A3 of the horizontal / vertical address selection unit 203b is changed. If the load and the load signal (S9) is low potential, the count is started by the character clock (S2) input from the monitor controller 200.

The count continues until the next load signal S9 becomes high potential, and when the load signal S9 becomes high potential, the address A3 of the horizontal / vertical address selection unit 203b is loaded again.

By repeating this operation continuously, an address A4 for accessing the actual display memory means such as (k) in FIG. 9 is generated.

When the address A4 of the display memory is generated after the system is reset, the vertical sync signal S4 is generated, and then the value of the start address register is loaded so that the character clock S2 is performed during the horizontal sync signal S3 period. Is repeated until the value of the start address register is loaded and the maximum scan event signal S8 is generated, and the start address register is latched when the maximum scan event signal S8 is generated. The offset register value D4 is loaded by the horizontal synchronizing signal S3 and counted again.

If the equal signal S5 from the screen division detecting means 201 becomes high potential while repeating the above process, the vertical start address register is loaded and the same operation is performed as in the operation after the vertical synchronization signal S4 is generated. As shown in Fig. 8A, the screen is divided horizontally.

That is, as shown in FIG. 8A, the contents of the address designated by the start address register SAR of the monitor controller 200 are displayed on one screen A of the display monitor, and the vertical start address register VSAR The contents of the address designated by) are displayed on the second screen (B).

On the other hand, when the screen split mode signal S1 from the monitor controller 200 is generated and output at a low potential, that is, in the vertical split display mode, the entire operation method and sequence are similar to the horizontal split display mode. Part of the description will be omitted.

That is, in the vertical division display mode, the second selection unit 201d of the screen division point detecting unit 201 sets the value D6 of the character clock comparison register generated by the monitor controller 200 by the screen division mode signal S1. ) Is input to the first comparison unit 5, and the first selection unit 3 selects the character count value of the character counter unit 2 which counts the number of times the current character clock S2 is selected. To be input to the first comparator 5.

Accordingly, the first comparison unit 5 compares the character clock count value selected by the first and second selection units 1 and 2 with the value D6 of the character clock comparison register and is equal to tenth. The equal signal S5 as shown in FIG.

The equal signal S5 output from the first comparator 5 of the screen splitting point detecting means 202 is equal to (b) in FIG. 10 by the horizontal selection control generating part 202a of the address selection controlling means 202. The vertical selection control signal S7 as shown in (d) of FIG. 10 is generated using the same horizontal synchronization signal S3, and the horizontal output from the first flip-flop 12 of the horizontal selection control generation unit 202a. The selection control signal S6 is changed as shown in FIG.

Also, the second comparison unit 15 of the vertical selection control generation unit 202b compares the output signal of the row scan counter unit 14 with the maximum scan line value D7 of the character size, as shown in FIG. A maximum scan comparison event signal S8 is generated.

When the horizontal address A1 is generated by the horizontal / vertical address generator 203a, the sum value D4 is used in the horizontal division mode, but the value D5 and the character of the horizontal display enable register are used in the vertical division mode. The value D6 of the clock comparison register is used.

Then, the horizontal / vertical address selection unit 203b selects the vertical address A2 generated by the horizontal / vertical address generation unit 203a by the screen division mode signal S1 and inputs it to the address generating means 204. The address generating means 204 divides the screen vertically as shown in FIG. 8 (b) by performing the same operation as in the horizontal division mode with the input vertical address A2.

That is, the contents of the address designated by the start address register SAR are displayed on the first screen A of the display monitor, and the contents of the address designated by the horizontal start address register HSAR are displayed on the second screen B. FIG. .

As described in detail above, according to the present invention, since the screen information displayed on the display monitor can be displayed by dividing it horizontally or vertically using hardware, the burden on the programmer applying the software is significantly reduced, and the video graphic array Alternatively, software programs in the graphics subsystem can be diversified.

Claims (11)

A monitor controller for generating a signal for screen control by including at least one register required for monitor control, and a screen split point detection for detecting a screen split point horizontally or vertically according to a screen split control signal generated by the monitor controller Address selection control means for generating an address selection control signal in accordance with the detection signal obtained by the means and the screen division point detection means and the screen division control signal generated by the monitor controller, and according to the address selection control signal obtained by the address selection control means. Memory address selection means for selectively outputting the address generated by the monitor controller, and horizontal / vertical addresses selected by the memory address selection means in accordance with the control signals generated by the address selection control means and the monitor controller and finally display. A screen display of the video graphics array characterized in that it consists of an address generating means for generating an address for accessing the memory means. 2. The memory address selection means according to claim 1, wherein the memory address selection means operates to select a value of a register for horizontal / vertical division input from the monitor controller according to the horizontal / vertical selection control signal and the maximum scan comparison event signal obtained by the address selection control means. Horizontal / vertical address generating means for generating and outputting a horizontal address and vertical address, and horizontal / vertical address selecting means for selectively outputting the horizontal / vertical address obtained by the horizontal / vertical address generating means according to the screen division mode signal of the monitor controller. Display apparatus of a video graphics array, characterized in that consisting of. The display apparatus of claim 1, wherein the screen splitting point detecting means comprises: a line counter unit for line counting the horizontal synchronization signal generated by the monitor controller, a character counter unit for counting character clocks generated by the monitor controller, and A first selector for selecting outputs of the line counter and the character counter according to the generated screen division mode signal; and a value of the line comparison register and the character clock comparison register generated by the monitor controller according to the screen division mode signal. A second selector for selective output and a line count value obtained by the first and second selectors and the value of the line comparison register or the value of the character clock and the value of the character clock comparison register, respectively, are compared and the resultant signal is obtained. A screen of a video graphics array characterized by comprising a first comparison unit input to an address selection control means The market value. The display device according to claim 1, wherein the address selection control means generates a horizontal selection control signal and a load signal with horizontal / vertical synchronization signals according to the result signal obtained by the screen division point detection means and the screen division mode signal generated by the monitor controller. According to the horizontal selection control generation unit and the result signal obtained from the screen division point detecting means and the screen division mode signal generated by the monitor controller, the maximum scan comparison event signal and the vertical selection control are performed with the horizontal / vertical synchronization signal and the maximum scan line value. And a vertical selection control generator for generating a signal. 3. The horizontal / vertical address generating means according to claim 2, wherein the horizontal / vertical address generating means comprises the sum of the registers generated in the monitor controller and the value of the vertical / horizontal address in accordance with the horizontal / vertical selection control signal and the maximum scan comparison event signal. A horizontal address generator for generating a horizontal address by selecting and calculating a value, a value of a character clock comparison register, a value of a line comparison register, and a horizontal display enable register according to the horizontal / vertical selection control signal and the maximum scan comparison event signal. And a vertical address generator which generates a vertical address by arithmetic selection of a value of and a value of a horizontal / vertical address. The display device of claim 4, wherein the horizontal selection control generation unit comprises: a third selector for selecting a horizontal / vertical synchronous signal according to the screen division mode signal; and a logic element configured to logic a value selected by the third selection unit and a screen division mode signal And a first flip-flop for generating a horizontal selection control signal by receiving an output of the logic device as a clock terminal and a feedback value as a data terminal, and outputting the output value and the horizontal synchronization signal of the logic device according to a screen division mode signal. And a fourth selector which selects and generates a load signal. 5. The method of claim 4, wherein the vertical selection control generation section compares the column scan counter for counting the input horizontal synchronization signal in the column scanning direction with the count value obtained from the column scan counter and the maximum scan line value of the character size. A second comparator for generating a scan comparison event signal, a fifth selector for selecting a vertical synchronization signal and an output signal of a logic element according to the screen split mode signal, and a second comparator according to a selection value obtained from the fifth selector. And a character line counter unit for counting the maximum scan comparison event signal of the comparison unit, and a decoder unit for decoding a count value of the character line counter unit to generate a vertical selection control signal. The display apparatus of claim 5, wherein the horizontal address generator comprises: a first adder for adding the sum value and the feedback value generated by the monitor controller; a sixth selector for selecting a horizontal / vertical address value according to a horizontal selection control signal; A seventh selector for selecting and outputting the output value of the first adder and the value obtained by the sixth selector according to a vertical selection control signal, and generating a horizontal address by synchronizing the output value of the seventh selector with a maximum scan comparison event signal And a second flip-flop. 6. The vertical address generator of claim 5, wherein the vertical address generator comprises a second adder configured to add a value and a feedback value of the character clock comparison register generated by the monitor controller, and output values of the second adder and a value of the vertical address to the vertical select control signal. An eighth selector for selective output, a third flip-flop for outputting the output value of the eighth selector in synchronization with a maximum scan comparison event signal, and a value of the character clock comparison register and a value of a horizontal display enable register; A subtractor for obtaining a difference; a third adder for adding a difference value and a feedback value of the subtractor; a ninth selector for selectively outputting an output value and a vertical address value of the third adder according to a vertical selection control signal; The fourth flip-flop which outputs the selected value obtained by the selection unit in synchronization with the maximum scan comparison event signal, and the output value of the third flip-flop and the output value of the fourth flip-flop Selection screen display of the video graphics array characterized in that it constituted by selection of claim 10 selected in accordance with a control signal for generating a vertical address. The display device of a video graphic array according to claim 1, wherein the register required for monitor control further comprises a vertical / horizontal split address register and a character clock comparison register. 8. The screen display device of claim 7, wherein the logic element is an ogate.