KR100282932B1 - Thin film device - Google Patents

Abstract

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Description

Thin film device

1A to 1N are views for explaining a method of manufacturing an active matrix type color liquid crystal display device according to the present invention.

FIG. 2A is a plan view of an essential part showing one pixel of a liquid crystal display of an active matrix type color liquid crystal display device to which the present invention is applied; FIG.

FIG. 2B is a cross-sectional view showing a portion cut by the cutting line IIB-IIB of FIG. 2A and a periphery of the sealing portion.

FIG. 2C is a cross-sectional view showing a portion cut by the cutting line IIC-IIC of FIG. 2A. FIG.

3 is a plan view of an essential part for explaining a liquid crystal display in which a plurality of pixels shown in FIG. 2A are arranged.

4 to 6 are plan views showing predetermined layers of the pixels shown in FIG. 2A, respectively.

FIG. 7 is a plan view of an essential part showing a state where the pixel electrode layer and the color filter layer shown in FIG. 3 overlap.

8 is an equivalent circuit diagram showing a liquid crystal display of an active matrix type color liquid crystal display device.

9 is an equivalent circuit diagram of a pixel shown in FIG. 2A.

10 is a time chart showing driving voltages of scan signal lines by a DC offset system.

11 and 12 are plan views for explaining predetermined steps which are part of the manufacturing method of the liquid crystal display device shown in FIG.

FIG. 13 is a view for explaining a method of manufacturing another active matrix type color liquid crystal display device according to the present invention; FIG.

<Explanation of symbols for main parts of drawing>

SUB: Transparent glass substrate GL: Scan signal line

DL: Video signal line GI: Insulation film

GT: gate electrode AS: i-type semiconductor layer

SD: source electrode or drain electrode

PSV: protective film BM: shading film

LC: liquid crystal TFT: thin film transistor

ITO: transparent pixel electrode ₁ g: a first conductive film on the scanning signal line

g ₂ : second conductive film of scanning signal line

d ₁ : a first conductive film of a source electrode or a drain electrode

d ₂ : second conductive film of the source electrode or the drain electrode

d ₃ : third conductive film of source electrode or drain electrode

Cadd: holding capacitor Cgs: overlap capacitance

Cpix: Liquid Crystal Capacitor GTM: Gate Terminal

(1): drain terminal (4): ITO film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film device, and more particularly, to a thin film device for use in an active matrix liquid crystal display device using a thin film transistor (TFT) or the like.

In an active matrix liquid crystal display element, a nonlinear element (switching element) is provided corresponding to each of a plurality of pixel electrodes arranged in a matrix. Since the liquid crystal for each pixel is always driven (duty ratio 1.0) in theory, the active method employing the time division driving method has a better contrast compared to the so-called simple matrix method, and the technology cannot be omitted particularly in color. Going to be. A typical switching device is a thin film transistor (TFT).

In the conventional method of manufacturing an active matrix liquid crystal display device, the first layer of the gate terminal is formed by the conductive film constituting the scan signal line, the insulating film used as the gate insulating film is formed, and then the video signal line is formed. The second layer of the gate terminal is formed of the conductive film, and after forming the protective film, the uppermost layer of the gate terminal is formed.

In addition, an active matrix liquid crystal display device using TFT is described in, for example, 12.5 type active matrix system employing a redundant configuration, described on page 193-210 of Nikkei Electronics, published on December 15, 1986 by Nikkei McGrawhill Corporation. Color liquid crystal display ”.

In addition, in the conventional method of manufacturing an active matrix liquid crystal display device, as disclosed in US Patent No. 3,824,003, after forming an insulating film used as a gate insulating film, the drain terminal is formed.

However, in the method of manufacturing such a liquid crystal display device, since the second layer of the gate terminal is formed after the insulating film used as the gate insulating film is formed, the first layer of the terminal is formed by forming the insulating film used as the gate insulating film. Since the surface of the layer is contaminated and poor contact occurs with the first and second layers of the terminal, the resistance of the terminal portion increases. In addition, since the uppermost layer of the gate terminal is formed after the protective film is formed, the surface of the second layer of the terminal is contaminated, resulting in poor contact between the second layer and the uppermost layer of the terminal, thereby increasing the resistance of the terminal portion.

In the method of manufacturing such a liquid crystal display device, since the drain terminal is formed after the insulating film used for the gate insulating film is formed, the scan signal line and the gate electrode are formed, and the insulating film used for the gate insulating film is formed. The surface of the transparent glass substrate is contaminated, and the drain terminal is easily peeled off.

An object of the present invention is to provide a thin film device having an external connection terminal with high reliability.

In order to achieve the above object, the present invention is a thin film device in which a thin film structure is formed on a main surface of one substrate, and includes a plurality of thin film transistors having a gate, a source, and a drain, and a source or drain of the transistor. A plurality of video signal lines electrically connected to one side, a first conductive film formed on the main surface of the substrate, a second conductive film formed on the main surface of the substrate, made of aluminum, and a gate of the thin film transistor. A plurality of scan signal lines formed of the first conductive film and the second conductive film, an insulating film formed on the substrate, and a protective film substantially covering the second conductive film of the scan signal line, and covered with the protective film. The second conductive film of the scan signal line has a plurality of terminals having an unsupported uppermost layer, and the uppermost layer of the corresponding gate terminal Through the first conductive film, and provides a thin film device characterized in that the electrically connected.

Preferably, the gate terminal and the uppermost layer are made of a transparent conductive film.

Also, preferably, the first conductive film is made of chromium.

According to an embodiment of the present invention, there is provided a thin film device which can prevent wiring from electric corrosion due to moisture atmosphere or the like.

Hereinafter, an active matrix type color liquid crystal display device to which the present invention is applied will be described in detail with reference to the drawings.

In addition, in all the drawings for explaining the liquid crystal display device, the same reference numerals are added to components having the same function, and description thereof will be omitted.

FIG. 2A is a plan view showing one pixel and its periphery of an active matrix type color liquid crystal display device to which the present invention is applied, and FIG. 2B is a cross section and a display panel of a portion cut by the cutting line IIB-IIB of FIG. 2A. Fig. 2C is a cross sectional view showing a portion cut by the cutting line IIC-IIC in Fig. 2A. FIG. 3 (a plan view of the main part) shows a plan view when the plurality of pixels shown in FIG. 2A is disposed.

[Pixel arrangement]

As shown in Fig. 2A, each pixel is composed of two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or vertical signal lines) DL. It is arrange | positioned in an intersection area | region (namely, the area | region enclosed by four signal lines). Each pixel includes a thin film transistor TFT, a pixel electrode IT01, and an additional capacitance Cad. The scan signal lines GL extend in the column direction and are arranged in plural in the row direction. The video signal lines DL extend in the row direction and are arranged in plural in the column direction.

[Overall structure of panel section]

As shown in FIG. 2B, a thin film transistor TFT and a transparent pixel electrode IT01 are formed on the lower transparent glass substrate SUB1 based on the liquid crystal layer LC, and the upper transparent eutectic substrate SUB2 is formed. On the side, a color filter FIL and a light blocking black matrix pattern BM are formed. The lower transparent glass substrate SUB1 has a thickness of about 1.1 mm, for example.

In the center portion of Fig. 2B, a cross section of one pixel portion is shown, but the left side is a left edge portion of the transparent glass substrates SUB1 and SUB2, and a cross section of a portion where an external lead wire is present. The right side shows a cross section of the right edge portion of the transparent glass substrates SUB1 and SUB2 where no external drawing wiring exists.

Each of the displayed sealing materials SL on the left and right sides of FIG. 2B is configured to seal the liquid crystal LC, and the transparent glass substrates SUB1 and SUB2 except for the liquid crystal sealing opening (not shown). It is formed along the entire edge. The sealing agent SL is formed of an epoxy resin, for example.

The common transparent pixel electrode IT02 on the upper transparent glass substrate SUB2 side is connected to an external lead-out wiring formed of silver paste material SIL on the lower transparent glass substrate SUB1 side for at least one position. The external lead-out wiring is formed in the same manufacturing process as each of the gate electrode GT, the source electrode SD1, and the drain electrode SD2.

Each layer of the alignment films ORI1 and ORI2, the transparent pixel electrode IT0, the common transparent pixel electrode IT0, the protective film PSV1, the PSV2, and the insulating film GI is formed inside the sealing part SL. Is formed. The polarizing plate POL is formed on the outer surface of each of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2.

The liquid crystal LC is sealed between the lower alignment film ORI1 and the upper alignment film ORI2 for setting the alignment of the liquid crystal molecules, and sealed by the sealing portion SL.

The lower alignment film ORI1 is formed on the upper portion of the protective film PSV1 toward the lower transparent glass substrate SUB1.

On the inside (liquid crystal side) surface of the upper transparent glass substrate SUB2, a light shielding film BM, a color filter FIL, a protective film PSV2, a common transparent pixel electrode COM02 and an upper alignment film ORI2 are formed. Laminated sequentially.

The liquid crystal display device separately forms respective layers on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and then overlaps the upper and lower transparent glass substrates SUB1 and SUB2, respectively. It assembles by sealing liquid crystal LC in between.

[Thin Film Transistor (TFT)]

The thin film transistor TFT operates such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain becomes small, and when the bias is zero, the channel resistance becomes large.

The thin film transistors TFT of each pixel are divided into three (multiple) in the pixel, and are composed of thin film transistors (split thin film transistors) TFT1, TFT2, and TFT3. Each of the thin film transistors TFT1 to TFT3 has substantially the same size (same channel length and width). Each of the thin film transistors TFT1 to TFT3 divided in this manner is mainly composed of a gate electrode GT, a gate insulating film GI, and an i-type (non-doped intrinsic conductive crystal impurities) amorphous silicon (Si). It consists of an i-type semiconductor layer AS, a pair of source electrodes SD1, and a drain electrode SD2. Further, the source / drain is inherently determined by the bias polarity therebetween, and in the circuit of the present display device, its polarity is inverted during operation, so it should be understood that the source / drain alternates during operation. However, in the following description, for convenience, one side is fixed and represented by a source, and the other side is fixed and represented by a drain.

[Gate Electrode (GT)]

As shown in detail in FIG. 4 (a plan view of the layers g1, g2, and AS in FIG. 2A), the gate electrode GT is perpendicular to the scan signal line GL in the vertical direction (FIG. It is comprised in the shape which protrudes in the upper direction in FIG. 4 (it branched in T shape). The gate electrode GT is configured to protrude to each formation region of the thin film transistors TFT1 to TFT3. Each gate electrode GT of the thin film transistors TFT1 to TFT3 is formed integrally (as a common gate electrode) and is formed continuously to the scan signal line GL. The gate electrode GT is formed of the first conductive film g1 of the scan signal line of a single layer so as not to form a large step in the region where the thin film transistor TFT is formed. The first conductive film g1 of the scan signal line is formed using, for example, a chromium (Cr) film formed by sputtering, and has a film thickness of about 1000 (Å).

The gate electrode GT is slightly larger than the semiconductor layer AS so as to completely cover the semiconductor layer AS (as viewed from below) as shown in FIGS. 2A, 2B, and 4. Is formed. Therefore, when the backlight BL such as a fluorescent lamp is mounted below the substrate SUB1, the opaque Cr gate electrode GT shades the semiconductor layer AS, and thus the backlight layer is exposed to the semiconductor layer AS. It is hard to reach | attain, and it is hard to produce deterioration of the conductive shape by light irradiation, ie, the OFF characteristic of TFT. In addition, with respect to the original size of the gate electrode GT, the gate electrode has a margin for positioning the gate electrode and the source / drain electrode, which is necessary to span between the source / drain electrodes SD1 and SD2. The inner length of the channel width W having a minimum width and the ratio of the distance between the source electrode and the drain electrode (channel length) L, that is, the mutual conductance gm, are determined. Condition for W / L).

It goes without saying that the size of the gate electrode used in this embodiment is larger than the original size described above.

Considering the gate electrode GT only for the function of the gate and the function of light shielding, the gate electrode GT and the scan signal line GL may be integrally formed in a single layer, in which case Si is used as an opaque conductive material. A1 containing, pure A1, or A1 containing Pd can be selected.

[Scanning signal line (GL)]

The scan signal line GL is composed of a plurality of films including the first conductive film g1 of the scan signal line and the second conductive film g2 of the scan signal line superimposed thereon. The first conductive film g1 of the scan signal line GL is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT and is integrally formed. The second conductive film g2 of the scan signal line is formed of, for example, an aluminum (A1) film having a film thickness of about 1000 to 5500 kPa by a sputtering technique. The second conductive film g2 of the scan signal line is configured to reduce the resistance of the scan signal line GL and to speed up the signal transfer speed (improve the information recording characteristic of the pixel).

In addition, the scan signal line GL is configured to have a smaller width of the second conductive film g2 of the scan signal line than the width of the first conductive film g1 of the scan signal line. In other words, the stepped shape of the sidewall of the scan signal line GL is gentle.

[Gate Insulation Film (GI)]

The insulating film GI is used for each gate insulating film of the thin film transistors TFT1 to TFT3. The insulating film GI is formed over the gate electrode GT and the scan signal line GL. The insulating film GI is formed using, for example, a silicon nitride film formed by plasma CVD and has a film thickness of about 3000 (Å).

[Semiconductor Layer (AS)]

As shown in FIG. 4, the i-type semiconductor layer AS is used for each channel-shaped region of the plurality of thin film transistors TFT1 to TFT3.

The i-type semiconductor layer AS is formed of an amorphous silicon film or a polysilicon film, and is formed at a film thickness of about 1800 (Å).

In the i-type semiconductor layer AS, the substrate SUB1 is external to the plasma CVD apparatus by exchanging components of the supply gas in the same plasma CVD apparatus, subsequent to the formation of the Si ₃ N ₄ gate insulating film GI. It is formed without exposing it. Similarly, the N ⁺ layer do (doped with Fig. 2b) doped with "P" for ohmic contact is also formed continuously in a thickness of about 400 (mm). Subsequently, the lower substrate SUB1 is drawn out from the CVD apparatus, and by the photo processing technique, the N ⁺ layer d0 and the i layer AS are shown in FIGS. 2A, 2B and 4 as shown in FIG. Patterning is performed in an independent island shape.

As shown in detail in FIGS. 2A and 4, the i-type semiconductor layer AS extends at a crossover portion between the scan signal line GL and the image signal line DL. The i-type semiconductor layer AS extended in this manner is configured to reduce the possibility of a short circuit occurring between the scan signal line GL and the video signal line DL at the intersection.

Source, drain electrodes SD1, SD2

The source electrode SD1 and the drain electrode SD2 of the plurality of thin film transistors TFT1 to TFT3 are divided into FIGS. 2A, 2B, and 5 (layers d1 to 2A of FIG. As shown in detail in the plan view of d3), the semiconductor layers AS are formed separately from each other.

Each of the source electrode SD1 and the drain electrode SD2 is a first conductive film d1 of the source electrode or the drain electrode, a second electrode of the source electrode or the drain electrode from a lower layer connected to the N ⁺ type semiconductor d0. The third conductive film d3 of the conductive film d2, the source electrode, or the drain electrode is sequentially stacked. Each of the first conductive film d1, the second conductive film d2, and the third conductive film d3 of the source electrode SD1 includes the drain electrode SD2, the first conductive film d1, and the second conductive film. It is formed in the same manufacturing process as each of (d2) and the third conductive film d3.

The first conductive film d1 of the source electrode or the drain electrode forms a chromium film having a thickness of 500 to 1000 mu (a thickness of about 600 mu in this embodiment) by sputtering. Since the chromium film has the property of increasing stress when the film thickness is large, it should be formed in a range not exceeding the film thickness of about 2000 (kPa). The chromium film has preferable contact conditions with respect to the N ⁺ type semiconductor layer d0. The chromium film has a function of preventing the aluminum contained in the second conductive film d2 of the source electrode or the drain electrode described later from being diffused into the N ⁺ type semiconductor layer d0 by forming a so-called barrier layer.

As the first conductive film d1 of the source electrode or the drain electrode, in addition to the chromium film, a high melting point metal (Mo, Ti, Ta, W) film and a solid solution metal silicide (MoSi ₂ , TiSi ₂ , Tasi ₂ , WSi ₂₎ ) May be formed into a film.

After patterning the first conductive film d1 of the source electrode or the drain electrode by photo processing, N or the first conductive film d1 of the source electrode or the drain electrode is masked by the mask. ⁺ Layer d0 is removed. That is, except for the first conductive film d1 of the source electrode or the drain electrode, the N ⁺ layer d0 remaining on the i layer AS is removed by self-alignment. At this time, since the N ⁺ layer do is etched to remove the same portion as its thickness, the surface of the i layer AS is etched to some extent. The extent to which the surface is etched can be controlled according to the etching time.

Next, the second conductive film d2 of the source electrode or the drain electrode is formed of aluminum having a thickness of 3000 to 5500 kPa (about 3500 kPa in this embodiment) by sputtering. The aluminum film has a smaller stress than the chromium film and can be formed with a thick film thickness. The aluminum film serves to reduce the resistance of the source electrode SD1, the drain electrode SD2, and the image signal line DL. The second conductive film d2 of the source electrode or the drain electrode may be formed of an aluminum film containing silicon (Si) or copper (Cu) as an additive in addition to the aluminum film.

After the second conductive film d2 of the source electrode or the drain electrode is patterned by a photo processing technique, a third conductive film d3 is formed. The third conductive film d3 is a transparent conductive film (Induim-Tin-Oxide (IT0)) having a film thickness of 1000 to 2000 (2000) in this embodiment by about sputtering. nesa film). The third conductive film d3 not only forms the source electrode SD1, the drain electrode SD2, and the image signal line DL, but also forms the transparent pixel electrode IT01.

Each of the first conductive film d1 of the source electrode SD1 and the first conductive film d1 of the drain electrode SD2 is a second conductive film d2 and a third conductive film d3 of the source electrode or the drain electrode. ), It is larger inward (in the direction of the center of the channel region). That is, in these portions, the first conductive film d1 of the source electrode or the drain electrode is arranged so as to define the gate length L of the thin film transistor TFT regardless of the layers d2 and d3. .

As previously described, the source electrode SD1 is connected to the transparent pixel electrode IT01. The source electrode SD1 has a stepped shape of the i-type semiconductor layer AS (the film thickness of the first conductive film g1, the film thickness of the N ⁺ layer d0, and the film thickness of the i-type semiconductor layer AS). And the same step as the film thickness obtained in total). Specifically, the source electrode SD1 has a transparent pixel electrode (1) compared to the first conductive film d1 and the first conductive film d1 of the source electrode formed along the stepped shape of the i-type semiconductor layer AS. IT01) and the second conductive film d2 of the source electrode formed on the upper side of the first conductive film d1 in a smaller size and exposed from the second conductive film, and the first conductive film d1 is exposed. The third conductive film d3 is connected to the third conductive film d3. The second conductive film d2 of the source electrode SD1 cannot form a thick chromium film of the first conductive film d1 due to an increase in stress, and can cover the stepped shape of the i-type semiconductor layer AS. Since it does not exist, it is comprised so that the said i type semiconductor layer AS may be covered. That is, the step coverage is improved by forming the second conductive film d2 of the source electrode thickly. Since the second conductive film d2 of the source electrode can be formed thick, it greatly contributes to the reduction of the resistance of the source electrode SD1 (the same applies to the drain electrode SD2 and the image signal line DL). . Since the third conductive film d3 cannot cover the stepped shape associated with the i-type semiconductor layer AS of the second conductive film d2 of the source electrode, the size of the second conductive film d2 of the source electrode is determined. It is arrange | positioned so that it may connect to the 1st conductive film d1 of the source electrode exposed by making it small. The first conductive film d1 and the third conductive film d3 of the source electrode not only have good adhesiveness to each other but also have a small stepped shape between the two electrodes, so that they can be reliably connected.

[Pixel electrode (ITO1)]

The transparent pixel electrode IT01 is formed for each pixel, and constitutes one of the pixel electrodes of the liquid crystal display unit. The transparent pixel electrode IT01 is divided into three transparent pixel electrodes (divided transparent pixel electrodes) E1, E2, and E3 corresponding to each of the plurality of divided thin film transistors TFT1 to TFT3. It is divided. The transparent pixel electrodes E1 to E3 are connected to the source electrode SD1 of the thin film transistor TFT, respectively.

Each of the transparent pixel electrodes E1 to E3 is patterned to have substantially the same area.

In this way, the thin film transistor TFT of one pixel is divided into a plurality of thin film transistors TFT1 to TFT3, and the transparent thin film transistors TFT1 to TFT3 divided into a plurality of thin film transistors TFT1 to TFT3 are thus divided. By connecting each of the pixel electrodes E1 to E3, even if one divided portion (e.g., TFT1) is pointed to a point, the point of view of the pixel as a whole does not result in a pointed point (i.e., TFT2 and TFT3 have no defects. Therefore, the probability of a point defect can be reduced, and it is difficult to observe the said defect.

In addition, each of the transparent pixel electrodes E1 to E3 of the pixel is configured to have substantially the same area, whereby each of the transparent pixel electrodes E1 to E3 and the common transparent pixel electrode IT02 are combined. It is possible to uniformly form each of the liquid crystal capacitors Cpix.

[Protective Film (PSV1)]

The passivation film PSV1 is formed on the thin film transistor TFT and the transparent pixel electrode IT01. The protective film PSV1 is mainly formed so as to code the thin film transistor TFT from moisture or the like. The protective film PSV1 should have high transparency and high moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by plasma CVD, and is formed to a film thickness of about 8000 (Å).

Light shielding film (BM)

On the upper substrate SUB2 side, a light shielding film BM is formed so that external light (for example, light from above in FIG. 2B) is not incident on the i-type semiconductor layer AS used as the channel shape region. The pattern is as shown by the diagonal line of 6 degrees. FIG. 6 is a plan view showing only the IT0 film layer d3, the filter layer FIL, and the light shielding film BM in FIG. 2A. The light shielding film BM is formed of a material having high light shielding property to light, for example, an aluminum film or a chromium film. In this embodiment, the chromium film is formed to a film thickness of about 1300 by sputtering. .

Therefore, the semiconductor layer AS common to the thin film transistors TFT1 to TFT3 is sandwiched by the upper light blocking film BM and the lower gate electrode GT, and the sandwiched portion is exposed to external natural light or backlight. It is not exposed. The light shielding film BM is formed around the pixel as indicated by the oblique portion in FIG. That is, the light shielding film BM is formed in a lattice shape (black matrix), and the effective display area of one pixel is partitioned by the lattice. Therefore, the outline of each pixel is made clear by the light shielding film BM and the contrast is improved. That is, the light shielding film BM has a light shielding function for the semiconductor layer AS and a light shielding function of a so-called black matrix.

It is also possible to mount the backlight on the “SUB2” side, and “SUB1” to the observation side (external exposure side).

[Common Electrode (ITO2)]

The common transparent pixel electrode IT02 faces the transparent pixel electrode IT01 formed for each pixel on the lower transparent glass substrate SUB1, and the optical state of the liquid crystal is between the pixel electrode IT01 and the common electrode IT02. It changes in response to the potential difference (electric field). The common voltage Vcom is applied to the common transparent pixel electrode IT02. The common voltage Vcom is an intermediate potential between the low level driving voltage Vdmin and the high level driving voltage Vdmax applied to the image signal line DL.

[Color filter (FIL)]

The color filter FIL is comprised by dyeing the dye in the base material formed from resin materials, such as an acrylic resin. The color filter FIL is formed in a dot shape for each pixel at a position opposite to the pixel (Fig. 7), and is assigned to each color (Fig. 7 is the third conductive film d3 of Fig. 3 Only the color filter layer FIL is illustrated, and each of the red filter R, the blue filter B, and the green filter G is represented by a 45 ° diagonal line, a 135 ° diagonal line, and a 45 ° and 135 ° cross diagonal line. have).

As shown in FIG. 6, the color filter FIL is slightly larger to completely cover the pixel electrodes IT01 (E1 to E3), and the light blocking film BM is formed of the color filter FIL and the pixel electrode IT01. The peripheral portion of the pixel electrode IT01 is formed inward from the edge portion so as to overlap the edge portion of the pixel electrode IT01.

The color filter FIL can be formed as follows. First, a dyeing substrate is formed on the surface of the upper transparent glass substrate SUB2, and the dyeing substrate other than the red filter forming region is removed by a photo processing technique. Next, the dyeing base material is dyed with a red dye and subjected to an adhesive treatment to form an adhesive filter (R). Next, the same fixing is performed, and the green filter G and the blue filter B are sequentially formed.

The protective film PSV2 is formed in order to prevent the dye which dyed the said color filter FIL in a different color from being attached to liquid crystal LC. The protective film PSV 2 is formed of a transparent resin material such as acrylic resin or epoxy resin, for example.

[Pixel arrangement]

The plurality of pixels of the liquid crystal display unit are arranged in the same column direction as the direction in which the scan signal line GL extends, as shown in FIGS. 3 and 7, and the pixel columns X1, X2, and X3. ), And (X4) .... Each pixel of the pixel columns X1, X2, X3, X4, ... is used to position the thin film transistors TFT1 to TFT and the transparent pixel electrodes E1 to E3. The configuration is the same. That is, each pixel of the odd pixel columns X1, X3, ... constitutes the arrangement positions of the thin film transistors TFT1 to TFT3 on the left side, and the transparent pixel electrodes E1 to E3. Pixels in each of the even-numbered column (X2) and (X4) .... located in the next step of) .... and each pixel of the odd-numbered column (X1), (X3) .... Line symmetry is shown with respect to the signal line DL. That is, each pixel of the pixel columns X2, X4, ... constitutes an arrangement arrangement of the thin film transistors TFT1 to TFT3 on the right side, and the pixels of the transparent pixel electrodes E1 to E3 are formed. The arrangement position is configured on the left side. Each pixel of the pixel columns X2, X4 .... is ½ times the distance between the pixels in the column direction with respect to each pixel of the pixel columns X1, X3 .... It is arranged to move. That is, when the interval between the pixels of the pixel column X is set to 1.0 (1.0 pitch), each pixel interval becomes 1.0 in the pixel column X of the next stage, and therefore, the column direction from the pixel column X of the preceding stage. They are shifted by 0.5 pixel intervals (0.5 pitch). The video signal line DL, which does not extend in the row direction between each pixel, extends in the column direction by a distance (0.5 pitch) that is ½ times the distance between the pixels between each pixel column X.

As a result, as shown in FIG. 7, the same color as the pixel of the pixel column X of the front end in which the predetermined color filter is formed (for example, the pixel of the pixel column X3 in which the red filter R is formed). A 1.5 times pixel spacing (1.5 pitch) may be formed between the pixels of the next pixel column X in which the filter is formed (for example, the pixels of the pixel column X4 in which the red filter R is formed). The color filter FIL of RGB becomes a triangular arrangement. The triangular arrangement structure of RGB of the color filter FIL can improve the state which mixed each color, and can therefore improve the resolution of a color image.

Further, the image signal line DL extends in the column direction between each pixel column X by a half pixel interval, so that the image signal line DL does not intersect the adjacent image signal line DL. As a result, the necessity of leading around the video signal line DL is eliminated, and the area occupied by the video signal line DL can be reduced. Therefore, the detour of the image signal line DL can be eliminated and the multilayer wiring structure can be removed.

[Equivalent Circuit of Display Panel]

The equivalent circuit of the liquid crystal display device is shown in FIG. (XiG), (Xi + 1G) ... are connected video signal lines DL of pixels on which the green filter G is formed. (XiB), (Xi + 1B) ... are the video signal lines DL connected to the pixel on which the blue filter B is formed. (Xi + 1R), (Xi + 2R), ... are the video signal lines DI connected to the pixel on which the red filter R is formed. These video signal lines DL are selected by the video signal driver circuit. (Yi) is a scan signal line GL for selecting the pixel column X1 shown in FIGS. 3 and 7. Similarly, each of (Yi + 1), (Yi + 2), ... is a scanning signal line GL for selecting each of the pixel columns X2, X3, .... These scanning signal lines GL are connected to the vertical scanning path.

[Structure of maintenance capacity (Cadd)]

Each of the transparent pixel electrodes E1 to E3 is formed in an L shape so as to overlap with the next scanning signal line GL at the end opposite to the end connected to the thin film transistor TFT. . In the above superposition, as is apparent from Fig. 2C, each of the transparent pixel electrodes E1 to E3 is one electrode PL2, and the scan signal line GL of the next stage is the other electrode ( A storage capacitor element (capacitive element) Cad of PL1) is formed. The dielectric film of the storage capacitor cadd is formed of the same layer as the insulating film GI used as the gate insulating film of the thin film transistor TFT.

As is apparent from FIG. 4, the storage capacitor Cad is formed in a portion where the width of the first film g1 of the gate line GL is widened. In addition, the portion of the first film g that crosses the drain line DL is narrowed in order to reduce the possibility of shorting the drain line.

Similar to the source electrode SDI, the transparent pixel electrode IT01 is disconnected when covering the stepped shape between the transparent pixel electrodes E1 to E3 overlapping each other to form the storage capacitor electrode line g1. In order to avoid this, an island region including the first conductive film d1 of the source electrode or the drain electrode and the second conductive film d2 of the source electrode or the drain electrode is formed. The island region is formed as small as possible so as not to lower the area (opening ratio) of the transparent pixel electrode IT01.

[Equivalent Circuit of Holding Capacity (Cadd) and Its Operation]

An equivalent circuit of the pixel shown in FIG. 2A is shown in FIG. In FIG. 9, "Cgs" is a parasitic capacitance formed between the gate electrode GT and the source electrode SDI of the thin film transistor TFT. The dielectric film of the parasitic capacitance Cgs is the insulating film GI. "Cpix" is a liquid crystal capacitor formed between the transparent pixel electrode IT01 (PIX) and the common transparent pixel electrode IT02 (COM). The dielectric films of the liquid crystal capacitor Cpix are liquid crystal LC, protective film PSV1, alignment films ORI1, and ORI2. The potential is (V1c) the midpoint potential.

The storage capacitor Cad functions to reduce the influence of the gate potential variation? Vg on the midpoint potential (pixel electrode potential) V1c when the thin film transistor TFT switches. If you express this as an expression

ΔV1c = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg

Becomes Here, "ΔV1c" represents the amount of change in the midpoint potential due to "ΔVg". The variation amount ΔV1c causes a DC component applied to the liquid crystal, but the value of the variation amount can be reduced according to the extent to which the holding capacitance Cad is increased. In addition, the holding capacitor Cad has a function of lengthening a discharge time, thereby accumulating image information for a long time after the TFT is turned off. Reduction of the direct current component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce the so-called seizing in which the previous image remains upon switching of the liquid crystal display screen.

As described above, the gate electrode GT is large so as to completely cover the semiconductor layer AS, and the overlapping area between the source electrode SDI and the drain electrode SD2 increases, and thus the parasitic capacitance Cgs. This increases, causing the adverse effect that the midpoint potential V1c is susceptible to the influence of the gate (scanning) signal Vg. However, the adverse effect can be eliminated by arranging the holding capacitance Cad.

The holding capacitance of the holding capacitor Cadd is a recording characteristic of the pixel, and is set to a value of about 4 to 8 times (4 · Cpix <Cadd <8 · Cpix) with respect to the liquid crystal capacitor Cpix, and the overlapping capacitance ( Cgs) is set to about 8 to 32 times (8 · Cgs <Cadd <32 · Cgs).

[Connection method of holding electrode (Cadd)]

The scanning signal line GL (or the scanning signal line GL at the first stage) of the last stage used as the capacitor electrode line is connected to the common transparent pixel electrode V _com (IT02) as shown in FIG. . As shown in FIG. 2B, the common transparent pixel electrode IT02 is connected to the external lead-out wiring by the silver paste material SL at the periphery of the liquid crystal display device. Further, the conductive layers g1 and g2 of the scan signal lines, which are part of the external lead-out wiring, are formed in the same manufacturing process as the scan signal lines GL. As a result, the final unit capacitance electrode line GL can be easily connected to the common transparent pixel electrode IT02.

Alternatively, as indicated by the dotted line in FIG. 8, the capacitor electrode line GL at the last stage (first stage) may be connected to the scan signal line GL at the first stage (final stage). The above connection can be made by internal wiring or external drawing wiring in the liquid crystal display.

[DC offset compensation by holding scan signal]

The liquid crystal display device first drives the scan signal line DL as shown in FIG. 10 (time chart) based on the DC cancellation method described in Japanese Patent Application No. 62-95125 filed by the present applicant. By controlling the voltage, the DC component applied to the liquid crystal LC can be further reduced. In Fig. 10, "Vi" is a drive voltage of an arbitrary scan signal line GL, and "Vi + 1" is a drive voltage of a next scan signal line GL. "Vee" is a low level drive voltage Vdmin applied to the scan signal line GL, and "Vdd" is a high level drive voltage Vmax applied to the scan signal line GL. Potential focus for each of the timing _{(t = t 1 ~t 4)} (V1c) ( see Figure No. 9), the voltage change amount (△ △ V ₁ ~ V ₄₎ of the are as follows:

t = t ₁ : ΔV ₁ =-(Cgs / C) V2

t = t ₂ : ΔV ₂ = + (Cgs / C) (V1 + V2)-(Cadd / C) V2

t = t ₃ : ΔV ₃ =-(Cgs / C) V1 + (Cadd / C) ・ (V1 + V2)

t = t ₄ : ΔV ₄ =-(Cadd / C) V1

However, the total pixel capacity is C = Cgs + Cpix + Cadd.

Here, if the driving voltage applied to the scan signal line GL is sufficient (see “Note” below), the DC voltage applied to the liquid crystal LC is

ΔV ₃ + ΔV ₄ = (CaddV2-CgsV1) / C

Since Cadd · V2 = Cgs · V1, the DC voltage applied to the liquid crystal LC becomes zero.

"Note": The fluctuation of the scanning line Vi at the time (t ₁ ) and (t ₂ ) affects the midpoint potential (V1c), but the midpoint potential (V1c) during the period (t ₂ ) to (t ₃ ). Becomes the same potential as the video signal potential through the signal line Xi (sufficient for recording the video signal). The potential applied to the liquid crystal is substantially determined by the potential immediately after the TFT is turned off (the TFT off period is overwhelmingly longer than the on period). Therefore, when calculating the direct current component applied to the liquid crystal, the periods t _{1 to} t ₃ can be almost ignored, and it should be considered that the potential immediately after the TFT is turned off, that is, the time t ₃ is between the time t ₄ . This is the effect that occurs during the transition. In addition, the polarity of the video signal Vi is inverted for each frame or line, and the DC component related to the video signal is zero.

That is, based on the DC offset method, the amount of reduction caused by the registration of the midpoint potential V1c due to the overlap capacitance Cgs is transferred to the holding capacitor Cadd and the scanning signal line GL (capacitive electrode line) of the next stage. The DC component applied to the liquid crystal LC can be made extremely small by increasing the driving voltage to be applied. As a result, the liquid crystal display device can improve the lifetime of the liquid crystal LC. Of course, when the gate GT is enlarged to improve the light shielding effect, the value of the holding capacitance Cad may be increased accordingly.

A method of manufacturing an active matrix type color liquid crystal display device according to the present invention will be described with reference to FIG. First, as shown in FIG. 1A, a first conductive film g1 of a scan signal line made of chromium having a thickness of 1100 (Å) is formed on a lower transparent glass substrate SUB1 made of 7059 glass (trade name). ) Is formed by sputtering. Next, the first conductive film g1 of the scan signal line is selectively etched by the photo etching technique using the second cerium ammonium nitrate solution as the etching solution, thereby the first layer of the scan signal line GL, the gate electrode GT, The electrode PL1 of the storage capacitor Cadd, the dustproof pattern (the pattern formed with protrusions on both the portions in which the gate terminal GTM is connected collectively and the portions in which the drain terminal is collectively connected), the board number and the TEG pattern At the same time, the first layer of the gate terminal GTM is formed. Is carried out for 1 minute, and then, after removing the resist removing solution to S502 (trade name), an ashing process of the _{O 2 (ashing process of O 2} ) on. Next, a second conductive film g2 of the scan signal line made of aluminum-filadium, aluminum-silicon, aluminum-silicon titanium, aluminum-silicon-copper, or the like is formed to a thickness of 1000 by sputtering. Next, by selectively etching the second conductive film g2 of the scan signal line by a photo etching technique using a mixed solution of phosphoric acid, nitric acid and acetic acid as the etching solution, a second layer of the scan signal line GL is formed. A second conductive film g2 is also formed on the first conductive film g1 of the gate terminal GTM. In this case, as shown in FIG. 11A, the end of the second conductive film g2 on the first conductive film g1 of the gate terminal GTM is positioned about 10 mu m away from the end of the insulating film GI. Is determined. Next, SF ₆ gas is introduced into the dry etching apparatus to remove residues such as silicon, and then the resist is removed. Next, ammonia gas, silane gas, and nitrogen gas were introduced into the plasma CVD apparatus to form a silicon nitride film having a thickness of 3500 (Å), and then silane gas, hydrogen gas, and phosphine gas were introduced into the plasma CVD apparatus. Then, an i-type amorphous silicon film having a thickness of 2100 (mm) is formed, and an N ⁺ type silicon film having a thickness of 300 mW is formed. Next, the i-type semiconductor layer AS is formed by selectively etching the N ⁺ -type silicon film and the i-type amorphous silicon film by a photo etching technique using SF ₆ and CC1 ₄ as dry etching gases. Next, after removing the resist, the resist RST1 is formed, and the insulating film GI is formed by selectively etching the silicon nitride film using SF ₆ as a dry etching gas. Next, as shown in FIG. 1 (b), before removing the resist RST1, the gate terminal GTM is formed by using a developer NMD (trade name) and a mixed solution of phosphoric acid, nitric acid and acetic acid. The second conductive film g2 of the scan signal line formed on the first conductive film g1 is removed. Next, as shown in FIG. 1C, after removing the resist RST1, a first conductive film d1 of a source electrode or a drain electrode made of chromium having a thickness of 600 mV is formed by sputtering. . Next, by selectively etching the first conductive film d1 of the source electrode or the drain electrode by a photo etching technique, a first layer of the image signal line DL, the source electrode SD1, and the drain electrode SD2 is formed. At the same time, a second layer of the gate terminal GTM is formed. In this case, the width of the first conductive film d1 of the source electrode or the drain electrode is made larger than the width of the first conductive film g1 of the scan signal line, and as shown in FIG. 12A, the gate terminal GTM. An end portion of the first conductive film d1 of the source electrode or the drain electrode on the first conductive film g1 of is extended on the insulating film GI. Next, before removing the resist, CC 1 ₄ and SF ₆ are introduced into the dry etching apparatus, and the N ⁺ type silicon film is selectively etched to form the N ⁺ type semiconductor layer d0. Next, after removing the resist, an ashing treatment of O ₂ is performed for 1 minute. Next, as shown in FIG. 1 (d), the second conductive film of the source electrode or the drain electrode made of aluminum-filadium, aluminum-silicon, aluminum-silicon titanium, or aluminum-silicon-copper having a thickness of 3500 kPa (d2) is formed by sputtering. Next, by selectively etching the second conductive film d2 of the source electrode or the drain electrode by a photo etching technique, a second layer of the image signal line DL, the source electrode SD1, and the drain electrode SD2 is formed. At the same time, the second conductive film d2 is also formed on the first conductive film d1 of the gate terminal GTM. In this case, as shown in FIG. 12A, the end of the second conductive film d2 on the first conductive film d1 constituting the second layer of the gate terminal GTM is the end of the protective film PSV1. Is positioned on the outside of the. Next, after removing the resist, ashing treatment of O ₂ is performed for 1 minute. Next, a third conductive film d3 made of an ITO film having a thickness of 1200 Å is formed by sputtering. Next, the third conductive film d3 is selectively etched by a sizing etching technique using a mixed solution of hydrochloric acid and nitric acid as an etching solution, thereby forming the first portion of the image signal line DL, the source electrode SD1, and the drain electrode SD2. Three layers and a transparent pixel electrode IT01 are formed. Next, after removing the resist, ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a silicon nitride film having a thickness of 1 탆. Next, a resist film RST2 is formed and the silicon nitride film is selectively etched using SF ₆ as the dry etching gas, thereby forming the protective film PSV1. Next, as shown in FIG. 1E, before removing the resist RST2, the first conductive film of the gate terminal GTM is formed by using a developing solution NMD and a mixed solution of phosphoric acid, nitric acid, and acetic acid. (d1), the second conductive film d2 is removed. Next, an IT0 film having a film thickness of 1200 (1200) is formed by sputtering. Next, the top layer TML of the gate terminal GTM is formed by selectively etching the IT0 film by a photo-etching technique using a mixed solution of hydrochloric acid and nitric acid as the etching solution.

In the method of manufacturing the liquid crystal display device, the second conductive film g2, which should constitute the second layer of the scan signal line GL, is formed, and the scan signal line constituting the first layer of the gate terminal GTM is formed. The second conductive film g2 of the scan signal line is formed on the first conductive film g1. After the insulating film GI is formed, the second conductive film g2 of the source electrode or the drain electrode on the first conductive film g1 of the gate terminal GTM is removed. As a result, since the surface of the first conductive film gl of the gate terminal GTM is not contaminated, the first conductive film g1 of the gate terminal GTM and the first conductive film g of the source electrode or the drain electrode ( Contact failure can be prevented from occurring between d1). The second conductive film d2, which should form the second layer of the video signal line DL, is formed on the first conductive film d1 constituting the second layer of the gate terminal GTM, and the protective film PSV1. ), And then the second conductive film d2 of the source electrode or the drain electrode on the second layer of the gate terminal GTM is removed. As a result, since the surface of the first conductive film d1 of the source electrode or the drain electrode forming the second layer of the gate terminal GTM is not contaminated, the first conductive film d1 of the gate terminal GTM is not contaminated. And contact failure between the top layer TML can be prevented. Therefore, the resistance of the gate terminal GTM can be reduced.

Another method of manufacturing the active matrix color liquid crystal display device according to the present invention will be described with reference to FIG. First, as shown in FIG. 13 (a), the first conductive film g1 having a scanning signal property is formed on the lower transparent glass substrate SUB1 by sputtering. Next, by selectively etching the first conductive film g1 of the scan signal line, the first layer of the scan signal line GL, the gate electrode GT, and the electrode PL1 of the storage capacitor element Cad are simultaneously formed. The first layer of the gate terminal GTM is formed. Next, the second conductive film g2 of the scan signal line is formed by sputtering. Next, by selectively etching the second conductive film g2 of the scan signal line, a second layer of the scan signal line GL is formed. Next, after the resist is removed to form a silicon nitride film, an i-type amorphous silicon film is formed, and an N ⁺ -type silicon film is formed. Next, the i-type semiconductor layer AS is formed by selectively etching the N ⁺ -type silicon film and the i-type amorphous silicon film. Next, after removing the resist, the resist RST1 is formed, and the silicon nitride film is selectively etched to form the insulating film GI. Next, before removing the resist RST1, a mixed solution of hydrochloric acid and nitric acid is used to treat the surface of the first conductive film g1 of the gate terminal GTM. Next, as shown in Fig. 13B, after removing the resist RST1, the first conductive film d1 of the source electrode or the drain electrode is formed by sputtering. Next, by selectively etching the first conductive film d1 of the source electrode or the drain electrode, the first layer of the image signal line DL, the source electrode SD1, and the drain electrode SD2 is formed, and the gate terminal A second layer of (GTM) is formed. Next, before removing the resist, the N ⁺ type silicon film is selectively etched to form the N ⁺ type semiconductor layer d0. Next, as shown in Fig. 13C, after removing the resist, the second conductive film d2 of the source electrode or the drain electrode is formed by sputtering. Next, by selectively etching the second conductive film d2 of the source electrode or the drain electrode, a second layer of the video signal line DL, the source electrode SD1, and the drain electrode SD2 is formed. Next, after removing the resist, the third conductive film d3 is formed by sputtering. Next, the third conductive film d3 is selectively etched to form the third layer of the image signal line DL, the source electrode SD1, the drain electrode SD2, and the transparent pixel electrode IT0. Next, after removing the resist, a silicon nitride film is formed. Next, a resist RST2 is formed and the silicon nitride film is selectively etched to form the protective film PSV1. Next, before removing the resist RST2, a mixed solution of hydrochloric acid and nitric acid is used to remove the surface of the first conductive film d1 of the source electrode or the drain electrode constituting the second layer of the gate terminal GTM. Process. Next, as shown in FIG. 13 (d), after removing the resist RST2, an IT0 film is formed by sputtering. Next, the IT0 film is selectively etched to form the uppermost layer TML of the gate terminal GTM.

In the method of manufacturing the liquid crystal display device, after the insulating film GI is formed, the first conductive film g1 of the scan signal line constituting the first layer of the gate terminal GTM is formed using a mixed solution of hydrochloric acid and nitric acid. ) Surface. Therefore, since the surface of the first conductive film g1 of the scan signal line forming the first layer of the gate terminal GTM can be cleaned, the first conductive film g1 and the source electrode or drain of the gate terminal GTM can be cleaned. It is possible to prevent the occurrence of contact failure between the first conductive film d1 of the electrode. In addition, since the protective film PSV1 is formed, the source electrode or the drain electrode, which is the second layer of the gate terminal GTM, uses the mixed solution of hydrochloric acid and nitric acid to treat the surface of the first conductive film d1. The source electrode or the drain electrode constituting the second layer of the gate terminal GTM may clean the surface of the first conductive film d1. Therefore, it is possible to prevent contact failure between the first conductive film d1 of the gate terminal GTM and the uppermost layer TML. Therefore, the gate terminal GTM can reduce the resistance.

Next, a method of manufacturing an active matrix type color liquid crystal display device according to the present invention will be described with reference to FIG. First, as shown in FIG. 1 (j), sputtering the first conductive film g1 of the scan signal line made of chromium having a thickness of 1100 μs on the lower transparent glass substrate SUB1 made of 7059 glass (trade name). Form by. Next, by selectively etching the first conductive film g1 of the scan signal line by a photo etching technique using a cerium ammonium nitrate solution as the etching solution, the first layer of the scan signal line GL, the gate electrode GT and The electrode of the storage capacitor Cadd is formed, and at the same time, the first layer of the drain terminal 1 and a part of the image signal line DL are formed. In this case, as shown in FIG. 11B, an end portion of a part of the video signal line DL made of the first conductive film g1 is positioned in the inner direction of the insulating film GI. Next, after removing the resist removing solution to S502 (trade name), it is carried out for 1 minute ashing treatment in O _2. Next, sputtering the second conductive film g2 made of aluminum-filadium (Pd), aluminum-silicon, aluminum-silicon-titanium (Ti), or aluminum-silicon-copper (Cu) and the like and having a thickness of 1000 mW Form by. Next, by selectively etching the second conductive film g2 of the scan signal line by a photo etching technique using a mixed solution of phosphoric acid, nitric acid and acetic acid as the etching solution, a second layer of the scan signal line GL is formed. A second conductive film g2 of the scan signal line is formed on the drain terminal 1 and the first conductive film g1 of the scan signal line that is part of the image signal line DL. In this case, as shown in FIG. 11B, an end portion of the second conductive film g2 of the scan signal line is placed on the first conductive film g1 of the scan signal line that is part of the drain terminal 1 and the video signal line DL. It is positioned about 10 (mu m) away from the end of the insulating film GI. Next, SF ₆ gas is introduced into the dry etching apparatus to remove residues such as silicon, and then the resist is removed. Next, ammonia gas, silane gas, and nitrogen gas were introduced into the plasma CVD apparatus to form a silicon nitride film having a thickness of 3500 GPa. Then, silane gas, hydrogen gas, and phosphine gas were introduced into the plasma CVD apparatus, and the thickness was 2100 GPa. And an i-type amorphous silicon film having a thickness of N, and an N ⁺ -type silicon film having a thickness of 300 Å. Next, the i-type semiconductor layer AS is formed by selectively etching the N ⁺ -type silicon film and the i-type amorphous silicon film by a photo etching technique using SF ₄ , CC 1 ₆ as dry etching gas. Next, after removing the resist, the resist 2 is formed, and the insulating film GI is formed by selectively etching the silicon nitride film using SF ₆ as the dry etching gas. Next, as shown in FIG. 1 (k), before removing the resist 2, using the developing solution NMD (trade name) and a mixed solution of phosphoric acid, nitric acid and acetic acid, the drain terminal 1 and the phase signal line The second conductive film g2 of the scan signal line formed on the first conductive film g1 of the scan signal line which is a part of the DL is removed. Next, as shown in FIG. 1 (1), after removing the resist 2, a first conductive film d1 of a source electrode or a drain electrode made of chromium having a thickness of 600 mV is formed by sputtering. . Next, by selectively etching the first conductive film d1 of the source electrode or the drain electrode by a photo etching technique, a first layer of the image signal line DL, the source electrode SD1, and the drain electrode SD2 is formed. At the same time, the second layer of the drain terminal 1 is formed. Next, before removing the resist, CC 1 ₄ and SF ₄ are introduced into the dry etching apparatus, and the N ⁺ type silicon film is selectively etched to form the N ⁺ type semiconductor layer d0. Next, after removing the resist, ashing treatment of O ₂ is performed for 1 minute. Next, as shown in FIG. 1 (m), the film thickness is 3500 (mm) of aluminum-filadium (Pd), aluminum-silicon, aluminum-silicon-titanium (Ti) or aluminum-silicon-copper ( The second conductive film d2 of the source electrode or the drain electrode made of Cu) or the like is formed by sputtering. Next, by selectively etching the second conductive film d2 of the grain electrode by a photo etching technique, a second layer of the video signal line DL, the source electrode SD1, and the drain electrode SD2 is formed and the drain terminal A second conductive film d2 of the drain electrode is also formed on the first conductive film d1 of (1). In this case, as shown in Fig. 12B, the end of the second conductive film d2 of the drain electrode formed on the first conductive film d1 of the drain electrode constituting the second layer of the drain terminal 1 is It is positioned outside the end of the protective film PSV1. Next, after removing the resist, ashing treatment of O ₂ is performed for 1 minute. Next, a third conductive film d3 made of an IT0 film having a thickness of 1200 Å is formed by sputtering. Next, the third conductive film d3 is selectively etched by a photoetching technique using a mixed solution of hydrochloric acid and nitric acid as an etching solution, whereby the third of the image signal line DL, the source electrode SD1, and the drain electrode SD2 is etched. A layer and a transparent pixel electrode IT01 are formed. Next, after removing the resist, ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a silicon nitride film having a thickness of 1 (mu m). Next, the resist 3 is formed, and the protective film PSV1 is formed by selectively etching the silicon nitride film using SF ₆ as the dry etching gas. Next, as shown in FIG. 1 (n), before removing the resist 3, the first conductive film of the drain terminal 1 is prepared by using a developer NMD and a mixed solution of phosphoric acid, nitric acid and acetic acid. The second conductive film d2 of the drain electrode formed on d1) is removed. Next, an IT0 film 4 having a thickness of 1200 mu m is formed by sputtering. Next, the third layer of the drain terminal 1 is formed by selectively etching the IT0 film 4 by a photo etching technique using a mixed solution of hydrochloric acid and nitric acid as an etching solution.

In the method of manufacturing the liquid crystal display device, the first conductive film g1 of the scan signal line forms the first layer of the scan signal line GL, the electrodes of the gate electrode GT, and the storage capacitor Cadd. The first layer of the drain terminal 1 and part of the video signal line DL are formed. The first layer of the terminal 1 of the lower transparent glass substrate SUB1 is formed by forming the first layer of the scan signal line GL, the gate electrode GT, the electrode of the storage capacitor Cadd, and the insulating film GI. Since the lower surface of the surface is prevented from being contaminated, the drain terminal 1 does not peel off. In addition, since an end portion of the video signal line DL formed of the first conductive film g1 of the scan signal line is positioned in the insulating film GI, it is possible to prevent the video signal line DL from being disconnected. Further, the second conductive film g2 of the scan signal line used to form the second layer of the scan signal line GI is the first conductive film g1 of the scan signal line that constitutes the first layer of the drain terminal 1. It is formed on the top. Since the second conductive film g2 of the scan signal line formed on the first conductive film g1 of the drain terminal 1 is removed after the insulating film GI is formed, the first conductive film of the drain terminal 1 ( to prevent contamination of the surface of g1). Therefore, it is possible to prevent a poor contact between the first terminal film g1 of the scan signal line, which is part of the drain terminal 1 and the image signal line DL, and the first conductive film d1 of the source electrode or the drain electrode. have. In addition, the second conductive film d2 of the drain electrode, which should constitute the second layer of the image signal line DL, is drained by the second conductive film d2 of the drain electrode forming the second layer of the drain terminal 1. A passivation film PSV is formed on the first conductive film d1 of the electrode. Next, the second conductive film d2 of the drain electrode formed on the second layer of the drain terminal 1 is removed, whereby the first conductive film of the drain electrode forming the second layer of the drain terminal 1 ( to prevent contamination of the surface of d1). Therefore, it is possible to prevent the occurrence of poor contact between the first conductive film d1 and the IT0 film 4 of the drain terminal 1.

A manufacturing method of the color liquid crystal display device of the actimetric matrix system according to the present invention will be described with reference to FIG. First, as shown in FIG. 13 (j), the first conductive film g1 of the scan signal line is formed on the lower transparent glass substrate SUB1 by sputtering. Next, by selectively etching the first conductive film g1 of the scan signal line, the first layer of the scan signal line GL, the gate electrode GT, the first layer of the drain terminal 1, and the image signal line DL A portion of the electrode and the electrode of the storage capacitor Cadd are formed, and a part of the first layer of the drain terminal 1 and a portion of the image signal line DL are formed. Next, the second conductive film g2 of the scan signal line is formed by sputtering. Next, by selectively etching the second conductive film g2 of the scan signal line, a second layer of the scan signal line GL is formed. Next, after the resist is removed to form a silicon nitride film, an i-type amorphous silicon film and an N ⁺ -type silicon film are formed. Next, the i-type semiconductor layer AS is formed by selectively etching the N ⁺ -type silicon film and the i-type amorphous silicon film. Next, after removing the resist, the resist 2 is formed, and the silicon nitride film is selectively etched to form the insulating film GI. Next, before removing the resist 2, the mixed solution of hydrochloric acid and nitric acid is used to treat the surface of the drain terminal 1 and the first conductive film g1 of the scan signal line which is part of the video signal line DL. . Next, as shown in FIG. 13 (k), after removing the resist 2, the first conductive film d1 of the source electrode or the drain electrode is formed by sputtering. Next, by selectively etching the first conductive film d1 of the source electrode or the drain electrode, the first layer of the image signal line DL, the source electrode SD1, and the drain electrode SD2 is formed, and the drain terminal The second layer of (1) is formed. Next, before removing the resist, the N ⁺ type silicon film is selectively etched to form the N ⁺ type semiconductor layer d0. Next, as shown in FIG. 13 (1), after removing the resist, the second conductive film d2 of the source electrode or the drain electrode is formed by sputtering. Next, by selectively etching the second conductive film d2 of the source electrode or the drain electrode, a second layer of the image signal line DL, the source electrode SD1, and the drain electrode SD2 is formed. Next, after removing the resist, the third conductive film d3 is formed by sputtering. Next, the third conductive film d3 is selectively etched to form the third layer of the image signal line DL, the source electrode SD1, the drain electrode SD2, and the transparent pixel electrode IT01. Next, after removing the resist, a silicon nitride film is formed. Next, the resist 3 is formed and the silicon nitride film is selectively etched to form the protective film PSV1. Next, before removing the resist 3, a mixed solution of hydrochloric acid and nitric acid is used to treat the surface of the first conductive film d1 of the drain electrode constituting the second layer of the drain terminal 1. Next, as shown in FIG. 13 (m), after removing the resist 3, the IT0 film 4 is formed by sputtering. Next, the third layer of the drain terminal 1 is formed by selectively etching the IT0 film 4.

In the method of manufacturing the liquid crystal display device, after the insulating film GI is formed, scanning is performed to form the first layer of the drain terminal 1 and a part of the image signal line DL by using a mixed solution of hydrochloric acid and nitric acid. The surface of the first conductive film g1 of the signal line is treated. Therefore, since the surface of the first conductive film g1 of the scan signal line constituting the first layer of the drain terminal 1 and part of the image signal line DL can be cleaned, the drain terminal 1 and the video signal line DL Contact failure between the first conductive film g1 of the scan signal line, which is a part of?, And the first conductive film d1 of the drain electrode, can be prevented. In addition, after the protective film PSV1 is formed, the surface of the first conductive film d1, which is the second layer of the drain terminal 1, is treated using a mixed solution of hydrochloric acid and nitric acid. Since the surface of the first conductive film d1 constituting the second layer can be cleaned, it is possible to prevent a poor contact between the first conductive film d1 of the drain terminal 1 and the IT0 film 4. Can be.

As mentioned above, although this invention was demonstrated concretely based on the said Example, this invention is not limited to the said Example, Of course, it can be variously modified in the range which does not deviate from the summary.

For example, the present invention can be applied to a liquid crystal display device in which each pixel of the liquid crystal display portion is divided into two or four portions. However, when the number of divisions of the pixels is too large, the aperture ratio is lowered, and as described above, the degree of division of 2 to 4 is reasonable. In addition, the light shielding effect can be obtained without dividing the pixel. Further, in the above embodiment, the reversed stagger structure formed in the order of the gate electrode, the gate insulating film, the semiconductor layer, and the source / drain electrode is dealt with. It is also valid for the in stagger structure.

As described above, in the manufacturing method of the liquid crystal display device according to the present invention, the first conductive film which should constitute the second layer of the first signal line is formed, and the first conductive film is formed on the first layer of the terminal. Since the first conductive film on the first layer of the terminal is removed after the insulating film used for the gate insulating film is formed, the surface of the first layer of the terminal is not contaminated. Therefore, it is possible to prevent the occurrence of poor contact between the first layer and the second layer of the terminal, so that the resistance of the terminal portion can be reduced.

In addition, since the insulating film is formed and the surface of the first layer of the terminal is treated with acid, the surface of the first layer of the terminal can be cleaned. As a result, occurrence of poor contact between the first layer and the second layer of the terminal can be prevented, so that the resistance of the terminal portion can be reduced.

Further, a third conductive film on which the second layer of the second signal line is to be formed is formed, and a third conductive film is formed on the terminal. Since the third conductive film formed on the terminal is removed after the protective film is formed, the surface of the terminal is not contaminated. Therefore, it is possible to prevent the occurrence of poor contact between the terminal and the uppermost layer, whereby the resistance of the terminal portion can be reduced.

In addition, after the protective film is formed, the surface of the second layer of the terminal is treated with acid, so that the second surface of the terminal can be washed. As a result, it is possible to prevent the occurrence of poor contact between the terminal and the uppermost layer, so that the resistance of the terminal portion can be reduced.

In the method for manufacturing a liquid crystal display device according to the present invention, a first conductive film on which a first signal line is to be formed is formed, and a first layer of a terminal connected to the second signal line is formed. By forming the first signal line and forming the insulating film used as the gate insulating film, the surface of the substrate formed under the first layer of the terminal is not contaminated, so that the terminal is not peeled off.

Further, a second conductive film which should constitute the second layer of the first signal line is formed, and a second conductive film is formed on the first layer of the terminal. If the second conductive film is removed from the first layer of the terminal after forming the insulating film used as the gate insulating film, the surface of the first layer of the terminal is not contaminated. Therefore, it is possible to prevent the occurrence of poor contact between the first layer and the second layer of the terminal.

In addition, when an insulating film is formed and the surface of the first layer of the terminal is treated with acid, the surface of the first layer of the terminal can be cleaned, resulting in poor contact between the first layer and the second layer of the terminal. Can be prevented.

Further, a fourth conductive film on which the second layer of the second signal line is to be formed is formed, and a fourth conductive film is formed on the second layer of the terminal. Next, if the fourth conductive film on the second layer of the terminal is removed after the protective film is formed, the surface of the second layer of the terminal will not be contaminated, so that the poor contact between the second layer and the third layer of the terminal It can be prevented from occurring.

In addition, if the surface of the second layer of the terminal is treated with an acid after forming the protective film, the surface of the second layer of the terminal can be washed, so that a poor contact between the second layer and the third layer of the terminal occurs. Can be prevented.

As mentioned above, the present invention exhibits remarkable effects.

Claims (3)

A thin film device having a thin film structure formed on a main surface of one substrate, comprising: a plurality of thin film transistors having a gate, a source, and a drain, and a plurality of images electrically connected to one of a source or a drain of the thin film transistor. A signal line, a first conductive film formed on a main surface of the substrate, made of chromium, a second conductive film formed on a main surface of the substrate, made of aluminum, and electrically connected to a gate of the thin film transistor, A plurality of scan signal lines comprising a first conductive film and a second conductive film, an insulating film formed on the substrate, a protective film substantially covering the thin film transistor and the second conductive film of the scan signal line, and covered with the protective film. It has a plurality of terminals having a top layer having no portion, the top layer of the terminal is made of a transparent conductive film , Thin film devices, characterized in that the uppermost layer of the gate terminal corresponding to the second conductivity film of the scanning signal line, through which the first conductive film, electrically connected to each other. The thin film device according to claim 1, wherein the protective film is made of a silicon nitride film. The thin film device according to claim 2, wherein the protective film is a silicon nitride film formed by a plasma CVD apparatus.

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