KR100281542B1 - A power management apparatus for reducing power consumption in dynamic circuit - Google Patents

Abstract

The present invention is to provide a power adjusting device for reducing power consumption without losing data stored in an idle condition of the dynamic circuit. To this end, the present invention provides a single clock that can reduce power consumption without losing data stored in an idle condition. A dynamic apparatus for use, comprising: clock generating means for generating an internal clock signal in response to a clock signal input from an external device; An internal dynamic circuit operating in response to the single clock; And an electric power adjusting device for reducing power consumption of the internal dynamic circuit, wherein the electric power adjusting device is output from the internal dynamic circuit and is enabled from an idle condition and is output from an external device. Control means for generating a control signal in response to a triggering signal enabled during an idle condition and a release signal indicating an idle condition of the internal dynamic circuit in an external power down mode; Clock dividing means receiving and dividing the internal clock signal in response to the control signal to generate a divided clock signal; And a clock selecting means for selecting one of the internal clock signal and the divided clock signal in response to the control signal and outputting the selected one clock to the single clock of the internal dynamic circuit.

Description

A power management apparatus for reducing power consumption in dynamic circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor circuits, and more particularly, to a power regulation apparatus for reducing power consumption without losing data stored in an idle condition of a dynamic circuit.

In general, a dynamic circuit can be implemented with a small number of transistors, the system timing problem is relatively simple, the implementation area is small compared to a static circuit, and when a load device is turned on. Power consumption only occurs because of the low power consumption is used a lot of advantages. However, the problem of the dynamic circuit is that if the clock signal is cut off in order to reduce power consumption during the idle condition, the data is not lost by the internal data storage element in the case of the static circuit. It is lost.

Therefore, in order to reduce power consumption without losing data during idle conditions in the dynamic circuit, the precharge time, which consumes little power, is increased, and the power consumption is high. The evaluation time requires the generation of a clock signal that is shortened.

The present invention has been made based on the above-described requirements, and an object thereof is to provide a power regulation apparatus capable of reducing power consumption without losing data stored in an idle condition of a dynamic circuit.

1 is a block diagram of a dynamic circuit including the power regulation device of the present invention.

FIG. 2 is a block diagram of a dynamic microprocessor operating in response to a clock signal of two phase phase incorporating the power regulation device of the present invention. FIG.

3 is an internal configuration diagram of a clock divider.

4A and 4B are internal configuration diagrams of a clock selector.

5 is an internal configuration diagram of a control unit.

* Explanation of symbols for main parts of the drawings

100: power control device 120: clock generator

140: dynamic circuit 150: clock divider

160: clock selection unit 170: control unit

The present invention for achieving the above object is a clock for generating an internal clock signal in response to a clock signal input from an external device in a dynamic device using a single clock, which can reduce power consumption without losing data stored in an idle condition Generating means; An internal dynamic circuit operating in response to the single clock; And an electric power adjusting device for reducing power consumption of the internal dynamic circuit, wherein the electric power adjusting device is output from the internal dynamic circuit and is enabled from an idle condition and is output from an external device. Control means for generating a control signal in response to a triggering signal enabled during an idle condition and a release signal indicating an idle condition of the internal dynamic circuit in an external power down mode; Clock dividing means receiving and dividing the internal clock signal in response to the control signal to generate a divided clock signal; And clock selecting means for selecting one of the internal clock signal and the divided clock signal in response to the control signal and outputting the selected one of the internal clock signal to the single clock of the internal dynamic circuit.

Further, a dynamic apparatus using a two-phase clock signal capable of reducing power consumption without losing data stored in an idle condition, comprising: clock generating means for generating an internal clock signal in response to a clock signal input from an external device; An internal dynamic circuit which receives the two-phase clock signal and performs various operations; And an electric power adjusting device for reducing power consumption of the internal dynamic circuit, wherein the electric power adjusting device is output from the internal dynamic circuit and is enabled from an idle condition and is output from an external device. Control means for generating a control signal in response to a triggering signal enabled during an idle condition and a release signal indicating an idle condition of the internal dynamic circuit in an external power down mode; Clock dividing means receiving and dividing the internal clock signal in response to the control signal to generate a divided clock signal; And in response to the control signal, convert the divided clock signal into a first clock pair of a first clock signal and a second clock signal, and convert the internal clock signal into a second clock of a third clock signal and a fourth clock signal. And a clock selecting means for converting the pair into a pair and selecting one of the first clock pair and the second clock pair and outputting the pair to the internal dynamic circuit.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram diagram of a power regulation apparatus according to an embodiment of the present invention capable of reducing power consumption without losing data stored in an idle condition of a dynamic circuit, and responding to an external clock signal phiE. Of the present invention for reducing power consumption of the internal dynamic circuit 140 by showing a clock generator 120 generating an internal clock signal phiI and an internal dynamic circuit 140 that performs substantially all operations. It is shown to show the connection with the power regulation device 100.

The power adjusting device 100 of the present invention may include an internal triggering signal (Si) output from the internal dynamic circuit 140, a triggering signal Se input from the outside, and a release signal input from the outside. The controller 170 generates a control signal Sc in response to Re, and divides the internal clock signal phiI output from the clock generator 120 in response to the control signal Sc to divide the internal clock. A clock divider 150 for generating a clock phiD having a lower frequency than the signal phiI, and an output from the internal clock signal phiI and the clock divider 150 in response to the control signal Sc. The clock selector 160 selects one of the divided clock signals phiD and outputs the same to the dynamic circuit 140. At this time, the release signal Re input from the outside informs the idle condition of the internal dynamic circuit in the power down mode. In the normal operation, the internal dynamic circuit 140 does not generate the internal triggering signal Si, and the controller 170 does not send the control signal Sc to the clock divider 150 and the clock selector 160. . Therefore, in this case, the clock selector 160 selects the internal clock signal phiI among the divided clock signal phiD and the internal clock signal phiI generated from the clock generator 120 to thereby select the internal dynamic circuit 140. In this case, the dynamic circuit 140 performs a normal operation.

Next, in an idle condition, the internal dynamic circuit 140 generates an internal triggering signal Si, and in response to the triggering signal Si, the controller 170 controls the clock divider 150 and the clock selector 160. To supply the control signal Sc. At this time, the clock divider 150 starts clock pulse counting in response to the control signal Sc. As a result, the clock divider 150 generates a clock signal phiD having a frequency lower than that of the internal clock signal phiI. . The clock selector 160 selects the divided clock signal phiD in response to the control signal Sc and outputs the divided clock signal phiD as a clock signal of the internal dynamic circuit 140. Accordingly, the dynamic circuit 140 operates by the divided clock signal phiD having a frequency lower than that of the internal clock signal phiI in the normal operation, and consumes less power in the normal operation.

FIG. 2 is a block diagram diagram of a power regulation apparatus according to an embodiment of the present invention capable of reducing power consumption without losing data stored in an idle condition of a dynamic circuit, and responding to an external clock signal phiE. And a clock generation unit 120 for generating an internal clock signal phiI, and a dynamic microprocessor 220 that operates in response to a clock signal having a two-phase phase. It is shown to show the connection with the power adjustment device 200 of the present invention to reduce the power consumption of.

Referring to FIG. 2, the apparatus 200 for adjusting power of the present invention is similar to the configuration illustrated in FIG. 1, but the clock selector 210 divides the clock signal phiD in response to the control signal Sc. ) Selects one of the first clock pair (phix1, phix2) that converted the two-phase clock signal and the second clock pair (phiy1, phiy2) that converted the internal clock signal (phiI) to the two-phase clock signal. Output to the dynamic microprocessor 220 using the phase clock, the controller 170 is an internal triggering signal (Si) output from the dynamic microprocessor 220, an external triggering signal (Se) input from the outside And a control signal Sc synchronized with the phiy1 in response to a release signal Re received from the outside.

Similar to the above embodiment, in the normal operation, the dynamic microprocessor 220 does not generate the internal triggering signal Si, and the controller 170 also transmits a control signal to the clock divider 150 and the clock selector 210. Do not send Sc). Accordingly, in this case, the clock selector 210 selects the internal clock signal phiI from the divided clock signal phiD and the internal clock signal phiI generated from the clock generator 120 to perform 2-phase conversion. The two clock pairs phy1 and phiy2 are supplied to the dynamic microprocessor 220, where the dynamic microprocessor 220 performs normal operation.

Next, in an idle condition, the dynamic microprocessor 220 generates an internal triggering signal Si, and in response to the triggering signal Si, the controller 170 may divide the clock divider 150 and the clock selector 210. To supply the control signal Sc. At this time, the clock divider 150 starts clock pulse counting in response to the control signal Sc, thereby generating a clock signal phiD divided at a low frequency. In addition, the clock selector 210 selects the divided clock signal phiD in response to the control signal Sc and clocks the first clock pairs phix1 and phix2, which are two-phase-converted, to the clock of the dynamic microprocessor 220. Output as a signal. Accordingly, the dynamic microprocessor 220 is operated by the low-frequency two-phase clock signals phix1 and phix2 in normal operation and consumes less power than in normal operation.

FIG. 3 is an internal circuit diagram of the clock divider 150 included in the power adjusting device of FIGS. 1 and 2 according to an embodiment of the present invention. The internal clock signal phiI is generated in response to the control signal Sc. The first T-flip flop 300 is divided into two outputs and the two divided signals output from the first T-flip flop 300 are received in response to a control signal Sc. From the second T-flip-flop 310 for outputting the clock signal, the logical multiplication gate 320 to receive and multiply the control signal Sc and the internal clock signal (phiI) as an input, and from the logical multiplication gate 320 A final divided clock after receiving and outputting an output signal, a divided clock signal from the first T-flip flop 300, and a divided clock signal from the second T-flip flop 310 as inputs The logic sum gate 330 outputs a signal phiD.

Referring to the operation of the clock divider 150 having such a configuration, when the control signal Sc is enabled with “HIGH”, the first T-flip flop 300 and the second T-flip flop are performed. An operation 310 is performed to output two divided clock signals and four divided clock signals, respectively, and an internal clock signal phiI is output through the AND gate 320. At this time, a divided clock signal phiD having a long precharge time and a short evolution time is generated through a logic sum gate 330 that receives the divided clock signal, the divided clock signal, and the internal clock signal phiI. do. Next, when the control signal Sc is disabled, the first T-flip-flop 300 and the second T-flip-flop 310 do not operate, and the clock signal divided through the logic sum gate 330 is performed. (phiD) is fixed at the "low" level.

4A and 4B are internal circuit diagrams of a clock selector 210 included in the power control apparatus of FIG. 2 according to an embodiment of the present invention, and convert a divided clock signal phiD into a two-phase clock signal. The first converter 400 generating the first clock pairs phix1 and phix2, and the second converter generating the second clock pairs phiy1 and phiy2 by converting the internal clock signal phiI into a two-phase clock signal. 420, in response to a control signal Sc, one of the first clock pairs phix1 and phix2 and the second clock pairs phiy1 and phiy2 output from the converters 400 and 420 is selected to select a dynamic microprocessor ( The switching unit 440 outputs to the 220.

Referring to FIG. 4A, the first converter 400 receives the inverted signal of the divided clock signal phiD and a phix2, and a first negative AND gate 401 for outputting a negative logic product and outputting the negative logic product. A first delay unit 405 for delaying the signal output from the gate 401 for a predetermined time and outputting phix1, and a second negative AND gate for receiving the logical clock signal phiD and phix1 and performing a negative logic multiplication. 402 and a second delay unit 406 for outputting phix2 by delaying a signal output from the second negative AND gate 402 for a predetermined time, and the second converter 420 includes an internal clock signal phiI. A third negative AND gate 403 that receives the inverted signal and phiy2 and outputs the negative logic multiply and outputs phiy1 by delaying the signal output from the third negative AND gate 403 for a predetermined time; 3 delay section 407, internal clock signal phiI and phiy1 A fourth negative AND gate 404 for receiving and outputting a negative logic product, and a fourth delay unit 408 for outputting phiy2 by delaying a signal output from the fourth negative AND gate 404 for a predetermined time period; do. In such a configuration, the first converter 400 and the second converter 420 may prevent the respective clocks of the first clock pairs phix1 and phix2 and the second clock pairs phy1 and phiy2 from overlapping each other. In order to receive the divided clock signal phiD and the internal clock signal phiI, the first clock pairs phix1 and phix2 and the second clock pairs phiy1 and phiy2 are generated so as not to have a “high” level at the same time. .

Referring to FIG. 4B, the switching unit 440 selects and outputs one of phix1 and phiy1 in response to the control signal Sc and phix2 and phiy2 in response to the control signal Sc. And a second clock selector 460 which selects and outputs one of the second clock selectors 460, and the clock selectors 450 and 460 respectively receive and output a logical multiplication gate 441, which receives and receives a logic signal phix1 or phix2 and a control signal Sc, respectively. 443), AND gates 442 and 444 for receiving and multiplying phiy1 or phiy2 and the inverted control signal Sc as inputs, and AND gates 441 and 443 and AND gates 442 and 444 And OR logic gates 445 and 446 for outputting one of phix1 and phiy1 or outputting one of phiy1 and phiy2.

FIG. 5 is an internal configuration diagram of the control unit 170 provided in the power adjusting device of FIG. 2 according to an embodiment of the present invention, and includes an internal triggering signal (Si) output from the dynamic microprocessor 140, It is composed of a plurality of logic gates for driving in response to an external triggering signal Se input from the outside and a release signal Re input from the outside, and generating a control signal Sc synchronized with the phiy1.

Referring to the overall operation in the above-described configuration, first, in the case of normal operation, the release signal Re, the external triggering signal Se, and the internal triggering signal Si are not input, whereby the control unit 170 controls the control signal. The clock divider 150 under the control of the control signal Sc does not perform the division operation without transmitting (Sc). In addition, the second converter 420 of the clock selector 210 under the control of the control signal Sc receives the internal clock signal phiI to generate second clock pairs pyy1 and phiy2, and the clock selector The switching unit 440 of 210 selects the second clock pairs phy1 and phiy2 output through the second converter 420 and outputs the two-phase clock signals of the dynamic microprocessor 220.

Next, in the case of an idle condition, for example, assuming that the dynamic microprocessor 220 performs the 'HOLD' instruction, this is transmitted to the internal triggering signal Si, and the internal triggering signal Si is 2 during normal operation. It is input to the control unit 170 in synchronization with phiy1 of the phase clock. The controller 170 outputs the control signal Sc to the "high" level, the clock divider 150 starts the division operation, and the switching unit 440 of the clock selector 210 switches the first converter 400. ) To supply the first clock pairs phix1 and phix2 to the dynamic microprocessor 220. As a result, it receives much lower power than normal operation by receiving the divided low frequency clock signal.

In order to return to normal operation from an idle condition, an external triggering signal Se is supplied from the outside, so that the controller 170 outputs a "low" level as the control signal Sc, and the clock divider 150 divides the operation. The switch 440 supplies the second clock pairs phy1 and phiy2 to the dynamic microprocessor 220.

In the power down mode, the external triggering signal Se is made high and a low frequency clock signal is input to the dynamic microprocessor 220, thereby reducing power consumption without loss of information.

As described above, the power adjustment device proposed in the present invention can be applied to a low power circuit using a dynamic circuit because power down operation can be performed without loss of information while maximizing the advantages of the dynamic logic.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

In order to prevent the loss of information, the present invention as described above generates a clock signal with a longer precharge time and a shorter elapsed time and applies it to a dynamic circuit without interrupting the clock signal like a static circuit under idle conditions. This allows the power-down operation of the dynamic circuit without loss of stored information, and thus has the effect of realizing a low power circuit with a smaller area than the static circuit.

Claims (12)

In a dynamic device using a single clock that can reduce power consumption without losing stored data during idle conditions, Clock generation means for generating an internal clock signal in response to a clock signal input from the outside; An internal dynamic circuit operating in response to the single clock; And It includes a power adjusting device for reducing the power consumption of the internal dynamic circuit, The power adjustment device, An internal triggering signal output from the internal dynamic circuit and enabled in an idle condition, a triggering signal output from the external and enabled in an idle condition and a release signal indicating an idle condition of the internal dynamic circuit in an external power down mode. Control means for generating a control signal in response to the signal; Clock dividing means receiving and dividing the internal clock signal in response to the control signal to generate a divided clock signal; And Clock selection means for selecting one of the internal clock signal and the divided clock signal in response to the control signal to output the single clock of the internal dynamic circuit; Including, dynamic device using a single clock. The method of claim 1, wherein the clock division means, First flip-flop means for dividing the internal clock signal by two in response to the control signal; Second flip-flop means for receiving a two-divided signal output from the first flip-flop means in response to the control signal and dividing the two-divided signal again to output a four-divided clock signal; First logic means for receiving and ORing the control signal and the internal clock signal; And The divided clock signal after receiving and logically outputting the output signal outputted from the first logic means, the divided clock signal from the first flip-flop means, and the divided clock signal output from the second flip-flop means Second logic means for outputting Including, dynamic device using a single clock. The method of claim 2, wherein the first flip-flop means and the second flip-flop means, Dynamic device using a single clock, characterized in that the T-flip-flop. In a dynamic device using a two-phase clock signal, which can reduce power consumption without losing stored data during idle conditions, Clock generation means for generating an internal clock signal in response to a clock signal input from the outside; An internal dynamic circuit which receives the two-phase clock signal and performs various operations; And It includes a power adjusting device for reducing the power consumption of the internal dynamic circuit, The power adjustment device, An internal triggering signal output from the internal dynamic circuit and enabled in an idle condition, a triggering signal output from the external and enabled in an idle condition and a release signal indicating an idle condition of the internal dynamic circuit in an external power down mode. Control means for generating a control signal in response to the signal; Clock dividing means receiving and dividing the internal clock signal in response to the control signal to generate a divided clock signal; And In response to the control signal, converts the divided clock signal into a first clock pair of a first clock signal and a second clock signal, and converts the internal clock signal into a second clock pair of a third clock signal and a fourth clock signal. A clock selection means for converting to and outputting one of the first clock pair and the second clock pair to the internal dynamic circuit; A dynamic device using a two-phase clock signal, comprising a. The method of claim 4, wherein the clock division means, First flip-flop means for dividing the internal clock signal by two in response to the control signal; Second flip-flop means for receiving a two-divided signal output from the first flip-flop means in response to the control signal and dividing the two-divided signal again to output a four-divided clock signal; Logic means for receiving and multiplying the control signal and the internal clock signal; And An output signal output from the logic means, a clock signal divided by two from the first flip-flop means, and a clock signal divided by four from the second flip-flop means are received and logically combined and output as the divided clock signal. Second logic means A dynamic device using a two-phase clock signal, comprising a. The method of claim 5, wherein the first flip-flop means and the second flip-flop means, A dynamic device using a two-phase clock signal, characterized in that it is a T-flip-flop. The method of claim 4, wherein the clock selection means, First conversion means for converting the divided clock signal into the two-phase clock signal to generate the first clock pair; Second conversion means for converting the internal clock signal into the two-phase clock signal to generate the second clock pair; And Switching means for selecting one of the first clock pair and the second clock pair in response to the control signal and outputting the selected signal to the internal dynamic circuit; A dynamic device using a two-phase clock signal, comprising a. The method of claim 7, wherein the first conversion means, First logic means for receiving the delayed clock signal and the second clock signal and performing a negative logic multiplication to output the second clock signal; First delay means for delaying a signal output from the first logic means for a predetermined time and outputting the first clock signal; Second logic means for receiving the delayed clock signal and the first clock signal and performing a negative logic multiplication to output the delayed clock signal; And Second delay means for delaying the signal output from the second logic means for a predetermined time and outputting the second clock signal; A dynamic device using a two-phase clock signal, comprising a. The method of claim 7, wherein the second conversion means, First logic means for receiving the delayed clock signal and the fourth clock signal and performing a negative logic multiplication to output the fourth clock signal; First delay means for delaying the signal output from the first logic means for a predetermined time and outputting the third clock signal; Second logic means for receiving the delayed clock signal and the third clock signal and performing a negative logic multiplication to output the third clock signal; And Second delay means for delaying the signal output from said second logic means and outputting it as said fourth clock signal; A dynamic device using a two-phase clock signal, comprising a. The method of claim 7, wherein the switching means, First selecting means for selecting and outputting any one of the first clock signal and the third clock signal in response to the control signal; And Second selection means for selecting and outputting any one of the second clock signal and the fourth clock signal in response to the control signal; A dynamic device using a two-phase clock signal, comprising a. The method of claim 10, wherein the first selection means, First logic means for receiving and ANDing the first clock signal and the control signal; Second logic means for receiving and ANDing the third clock signal and the control signal; And Third logic means for selecting and outputting any one of the first clock signal and the third clock signal by ORing the signals output from the first and second logic means; A dynamic device using a two-phase clock signal, comprising a. The method of claim 10, wherein the second selection means, First logic means for receiving and ORing the second clock signal and the control signal; Second logic means for receiving and multiplying the fourth clock signal and the control signal as an input; And Third logic means for outputting any one of the second clock signal and the fourth clock signal by ORing the signals output from the first and second logic means; A dynamic device using a two-phase clock signal, comprising a.

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