KR100275709B1 - An audiovisual teleservices interface subsystem - Google Patents

Abstract

FIELD OF THE INVENTION The technical field of the present invention relates to systems for audiovisual teleservices using digital telecommunication services, such as a comprehensive information network ("ISDN"). In a preferred embodiment, interface subsystem 100 comprises ISDN interface circuit 130 for exchanging ISDN access and audiovisual information simultaneously. Interface subsystem 10 also includes host computer interface circuitry 144 for exchanging video, audio, high data, and low speed data with the host digital computer. The computer program executed by the digital signal processing circuit 122 implements CCITT H.221 and H.242 recommendations for audiovisual teleservices, video, audio, high data, and low speed data with other compatible terminals using digital telecommunications. A computer program is provided in the application layer 44 of 0SI which is performed by a host digital computer having an interface capable of exchanging data.

Description

[Name of invention]

Audiovisual Teleservice Interface Subsystem

[Technical Field]

TECHNICAL FIELD The present invention relates to the field of telecommunications, and in particular, to communicating audiovisual information using digital telecommunication services, such as Integrated Services Digital Network ("ISDN") communications.

Background Technology

In order to deal with current complex communication systems and to reasonably handle different systems interoperably, the International Organization for Standardization ("IS0") has developed a model that defines such systems. Using this model, called the Open System Interconnect (“OSI”) model, communication systems can be classified into hierarchies, which can form standards in each class. The OSI model provides seven different layers of layers that can occur in a communication system. Each layer in the 0SI model defines different functions performed by the communication system.

The lowest layer, called the physical layer in the 0SI model, defines the physical structure of the interface in a particular communication system or network. Thus, standards for the physical layer of a communication system define the number of wires, their electrical characteristics, the signal characteristics transmitted over these wires, the connectors used to join two sets of wires into a single longer set of wires, and the like.

The lowest layer, called the data link layer, in the 0SI model, defines how data is transmitted without error through the communication system.

Thus, the standard for the second layer in the OSI model specifies how to detect errors passing through the physical layer in transmission and how to correct any errors that may occur during transmission.

The next higher layer, called the network layer in the 0SI model, defines how connections are established between points in a communication system during data transfer. Thus, the standard for the third layer in the OSI model defines a signal transmitted over the data link layer that allows the communication system to transfer data between two points on the network.

Recommendations by the International Telegraph and Telephone Advisory Committee (“CCITT”) for ISDN communication channels define three lowest classes in the OSI model. Under the CITT Recommendation, basic ISDN access consists of two full duplex 64 kbps digital data channels called channels B1 and B2 and another full duplex 16 kbps digital channels called D channels. Using time division multiplexing under the CCITT recommendation, all three digital data channels can be transmitted over a single pair of twisted wires or two pairs of twisted wires. The ISDN basic rate access defined by the CCITT was originally intended to provide basic digital data transfer capability suitable for individual use, such as in a home or small business.

When ISDN base rate access was initially defined, each B channel was for transmitting one of the following.

1. Digital data from a personal computer or computer terminal.

2. Pulse code modulation ("PCM") encoded digital voice communications.

3. A mix of lower data rate communications including digital voice and data encoded as part of the full 64 kbps capacity of each B channel.

Under the ISDN Recommendations, the D channel serves two purposes. First, the D channel transmits signal information for controlling data transmission through two B channels. In addition, if the D channel does not transmit signal information, this D channel can be used to transmit packet switching or slow telemetry. According to the ISDN recommendation for basic rate access, the combined data rate at which digital data can be transmitted over twisted wire pairs is 144 kbps, the sum of 128 kbps for the combined B1 and B2 channels and 16 kbps for the D channel. to be.

In addition to the ISDN base rate access defined by the CCITT, the International Organization for Standardization has also defined a high performance ISDN communication channel called main rate access. Using time division multiplexing depending on the particular geopolitical location, an ISDN main rate access has 24 time slots or 32 time slots, each of which carries information of a single ISDN B channel. ISDN main rate access with 24 time-slots is called T1-connection, and ISDN main rate access with 32 time-slots is called E1-connection. One way that ISDN main rate access uses these 24 or 32 time-slots is that each 23 or 30 time-slot transmits independent B channel information and the remaining time-slots transmit D channel control data.

In addition, groups of 23 or 30 time-slots in ISDN main rate access can be used to transmit digital information at higher data rates. For example, using a connection classified as H0, six time-slots of ISDN main rate access can be used to transmit six B channel information simultaneously. Thus, the ISDN H0-connection carries 384 kbps digital information. In addition to the H0-connection, CCITT has defined a service called H11-connection, which consists of 24 B channels. The H11-connection can be established via an E1-connection or alternatively via a T1 connection that combines independent D-channel control information. Thus, the H11-connection simultaneously transmits 24 B channel information. CCITT also defined a service called H12-connection in which 32 time-slots of E1-connections simultaneously transmit 30 B-channel information and D-channel control data.

The CCITT ISDN Recommendation has established Recommendation H 221, which specifies the data structure used in the transmission of audiovisual teleservices over channels with a bandwidth of 56 to 1920 kbps. CCITT's H 221 recommendation defines a data structure for communicating audiovisual information through either one to six B channels, one to five H0-connections, or one of H11- and H12-connections. The use of one to six B channels for transmitting audiovisual information provides a data transfer rate of 64 to 384 kbps in increments of 64 kbps. The use of 1 to 5 H0-connections provides a data transfer rate of 384 to 1920 kbps in increments of 384 kbps. The H11-connection provides a data transfer rate of 1536 kbps and the H12-connection provides a data transfer rate of 1920 kbps.

In addition to the H.221 Recommendations, the CCITT also established Recommendation H.242, which specifies protocols for establishing audiovisual teleservices. The H 242 recommendation establishes a procedure in which two audiovisual terminals communicate with each other before and during the exchange of audiovisual information to match their respective capabilities for transmitting and receiving audiovisual information. Capabilities that communicate with each other between these two terminals include audio capability, video capability, transmission rate capability data capability, encryption capability, and bit rate allocation signal (" BAS ") capability.

FIG. 1 illustrates the relationship existing between B channel 22 and D channel 24 of three ISDN basic rate accesses and layer 28 corresponding to CCITT H.221 Recommendations. B channel 22 and D channel 24 belong to the layer that implements the CCITT I.400 Recommendation. In FIG. 1, arrow 32 represents the passage of time from the beginning to the end of an audiovisual telecommunication. Figure 1 also illustrates the overlap through each D channel 24 of layer 34 that implements the CCITT Q.921 recommendation and layer 36 that implements the CCITT Q.931 recommendation. Layers 34 and 36 provide independent call set-up and tear-down for each ISDN base rate access 26. A double arrow 38 extending between each B channel 22 and the H.221 layer 28 indicates a bidirectional exchange of viewing angle information between the two layers 30 and 28.

In addition to audiovisual information exchange between the two layers 30, 28, the double-headed arrow 42 also provides video data between the application layer 44 and the H.221 layer 28, which can use the received video data to generate a visible image. Indicates bidirectional exchange of. In order to provide video data to application layer 44, H.221 layer 28 extracts such data from audiovisual information received from B channel 22. The H.221 layer 28 also embeds video data received from the application layer 44 into the audiovisual information transmitted to the B channel 22. The double arrow 46 indicates the bidirectional exchange of audio data between the application layer 44 and the H.221 layer 28, which can use the audio data to generate an audible voice. Similar to processing audiovisual information and video data by H.221 layer 28, layer 28 extracts audio data from the audiovisual information received from B channel 22 and delivers it to coating layer 44. . H.221 layer 28 also embeds audio data received from coating layer 44 into audiovisual information that is transmitted to channel B 22. Bi-directional arrows 48 and 52 indicate bi-directional exchange of high speed data and low speed data between H.221 layer 28 and application layer 44, respectively. The H.221 layer 28 extracts the high speed data and the low speed data from the audiovisual information received from the B channel 22 and transmits the high speed data and the low speed data to the coating layer 44. It is embedded in the audiovisual information transmitted to the B channel 22.

2 illustrates the relationship existing between H.221 layer 28 and 23 B-channels 22 and D-channels 24, respectively, transmitted by 24 time-slots of ISDN main rate access 62. FIG. will be. B channel 22 and D channel 24 of ISDN main rate access 62 implement I.400 layer 30. In FIG. 2, the CCITT Q.921 layer 34 and the CCITT Q.931 layer 36 overlap through the time-slot of the ISDN main rate access 62 carrying the D channel 24. Similar to the first diagram, an arrow 38 extending between the various B channels 22 and the H.221 layer 28 indicates the bidirectional exchange of audiovisual information between the two layers 30 and 28. In FIG. 2 two sets of six arrows 38 represent two H0-connections 64. In FIG. 2, one H0-connection 64 consists of six B channels 22, each transmitted in six immediately adjacent time-slots. FIG. 2 also illustrates six randomly allocated time-slots transmitting six B channels 22 that make up another H0-connection 64. Except for the data transfer rate, the ISDN main rate access 62 is accessed, as indicated by the double-sided arrows 42, 46, 48, 52 of FIG. 2, which are identical to the double-sided arrows 42, 46, 48, 52 of FIG. The H.221 layer 28 exchanging audiovisual information with one or more H0-connections 64 provided by H.221 layer 28 exchanges audiovisual information with three ISDN basic rate access 26, as illustrated in FIG. Similar to the 221 layer 28, the same interface may be provided to the application layer 44 for exchanging video, audio, high speed data and low speed data.

3 illustrates the relationship between the B channel 22 and the D channel 24 and the H.221 layer 28 of the H11-connection, indicated by reference numeral 72. H11-connection 72 consists of ISDN main rate access 62 and ISDN basic rate access 26. Similar to FIGS. 1 and 2, ISDN main rate access 62 in combination with ISDN basic rate access 26 shown in FIG. 3 implements an I.400 layer of H11-connection 72. According to the I.400 Recommendation for H11-Connection 72, D channel 24 of ISDN base rate access 26 is used by CCITT Q.921 layer 34 and CCITT Q.931 layer 36. Send control information. In H11-connection 72 all 24 time slots in ISDN main rate access 62 are used as B channel 22 for exchanging audiovisual information with H.221 layer 28 as indicated by the double-headed arrow 38. do. H11-connection 72, as indicated by the double-headed arrows 42, 46, 48, and 52 of FIG. 3, which are the same as the double-headed arrows 42, 46, 48, and 521 of FIGS. 1 and 2 except for the data transfer rate. The H 221 layer 28 exchanging audiovisual information with the 24 B channels 22 provided by) is similar to the H 221 layer 28 illustrated in FIG. 1 or FIG. And the same interface to the application layer 44 for exchanging low speed data.

If two terminals exchange audiovisual information using H11-connection 72, H12-connection, or a single H0-connection 64, the ISDN operation is performed from the H.221 layer 28 of the transmitting terminal to the receiving terminal. The internal B channel phase relationship up to H.221 layer 28 is preserved intact. For any other form of ISDN transmission allowed under the CCITT H.221 Recommendation, preservation of the phase relationship between the B channels 22 is not guaranteed. If the receiving terminal is connected to the ISDN main rate access 62 or vice versa when the transmitting terminal is connected to two or more B channels 22 of the ISDN basic rate access 26, on a different B channel 22 Skew may occur between the data received at That is, when two or more B-channels 22 on two or more H0-connections 64 or ISDN basic rate access 26 are used to transmit or receive an audiovisual teleservice, data transmitted in phase is received. There is no need to reach in phase at the terminal. Skew in such received data may occur whenever an audiovisual teleservice is transmitted over the B channel 22 which is established by placing a different telephone call.

The CCITT ISDN recommendation causes the internal B channel skew between the two B channels 22 or two H0-connections 64 of the ISDN basic rate access 26 to be 1200 milliseconds. This skew between different B channels 22 of different H0-connections 64 or ISDN base rate access 26 is such that B channel 22 of H0-connections 64 or ISDN basic rate accesses 26 between terminals. This happens because in is transmitted over a different path.

Although the CCITT H.221 Recommendation prescribes the structure for digital audiovisual information transmitted over various different ISDN accesses or connections, it may be applied to any digital circuitry and / or computer hardware and / or computer software capable of performing such communications. No description or facial cleansing is done. In addition, the CCITT H.221 Recommendation does not provide any suggestions for data structures and protocols for exchanging video, audio, high-speed data, and low-speed data between interfaces, i.

[Initiation of invention]

It is a first object of the present invention to provide an interface subsystem for exchanging audiovisual information via digital telecommunications in accordance with the CCITT H.221 Recommendation.

It is a second object of the present invention to provide a cost effective interface subsystem capable of exchanging audiovisual information in accordance with the CCITT H.221 Recommendation.

It is a third object of the present invention to provide a modular interface subsystem that can be programmed to exchange audiovisual information in accordance with the CCITT H.221 Recommendation.

A fourth object of the present invention is to provide an interface service system for audiovisual teleservice that can be programmed from a host digital computer.

A fifth object of the present invention is to provide a modular interface subsystem capable of exchanging audiovisual information between computers using an industry standard architecture ("ISA") bus according to the CCITT H.221 Recommendation.

A sixth object of the present invention is to provide an interface system for exchanging audiovisual information with another interface subsystem using digital telecommunications in accordance with the CCITT H.221 Recommendation, and to exchange data and / or messages between audiovisual applications performed in a computer. To provide data structures and protocols.

A seventh object of the present invention is to provide an interface subsystem capable of simultaneously exchanging several independent digital telecommunication access and audiovisual information in accordance with the CCITT H.221 Recommendation.

In summary, in a preferred embodiment of the present invention, the interface subsystem according to the present invention comprises an ISDN basic rate interface circuit for exchanging digital audiovisual information with the first ISDN basic rate access. The interface subsystem according to the invention also includes a second ISDN interface circuit for exchanging digital audiovisual information with at least a second ISDN access. In one embodiment of the invention, this second ISDN access may be configured with one or more basic rate access. In another embodiment of the present invention, this second ISDN access may be the main rate access. The interface subsystem also includes host computer interface circuitry for exchanging digital audiovisual information with the host digital computer. In one embodiment of the invention, the host computer interface circuit fits an interface subsystem for exchanging digital audiovisual information with a digital computer using an ISA bus. Random access memory (“RAM”) is also included in the interface subsystem to store digital audiovisual information received by any interface circuitry.

The interface subsystem also includes all the interface circuits and digital signal processing circuits coupled to the RAM for controlling the operation of the interface circuits. The digital signal processing circuit exchanges digital audiovisual information with the interface circuit and processes the data received from the interface circuit. In processing the received digital audiovisual information, the digital signal processing circuitry synchronizes the digital audiovisual information received from several ISDN basic rate access or single ISDN main rate access by the interface subsystem. In the processing of digital audiovisual information, the digital signal processing circuit also multiplexes the digitalized video, audio and data signals exchanged through several ISDN accesses. The digital signal processing circuit also controls the operation of the interface circuit to respond to the initiation of an ISDN audiovisual teleservice and to initiate the service when requested by a host digital computer. In a preferred embodiment of the present invention, the digital signal processing circuit receives the audiovisual information of each successive word following reception of the ISDN interface circuit and transmits the audiovisual information of each successive word to the ISDN interface for transmission to several ISDN accesses. An integrated circuit digital signal processor that transmits to the circuit.

The RAM included in the interface subsystem includes a plurality of receive circuit buffers for receiving audiovisual information of the plurality of frames. The RAM also includes a plurality of sorting buffers, each of which can address octets received from individual B channels 22, locations that hold 8 bits of audiovisual information. The octets stored in the classification buffer are scanned to position the frame alignment signal ("FAS") specified by the CCITT H.221 Recommendation. After the FAS is located, the classification buffer receives audiovisual information of consecutive frames from each B channel 22 having the FAS located at the eighth bit of the first octet of the classification buffer and the eighth bit of the eighth octet. . Video, audio, high speed data and low speed data are extracted from audiovisual information of consecutive frames in the classification buffer and stored in each data buffer located in the RAM of the interface subsystem. A set of host computer interface receive buffers receives and stores video, audio, high speed data, and low speed data that can be removed by a host digital computer. The interface subsystem also includes a set of host computer interface transmit buffers that receive video, audio, high speed data, and low speed data from a host digital computer for transmitting audiovisual information from the ISDN interface circuit. The host computer interface receive buffer and the transmit buffer are preferably located in shared RAM disposed within the host computer interface circuit.

Under certain operating situations, the interface subsystem may receive a single stream of audiovisual information from multiple ISDN connections, such as several H0-connections 64. Under these circumstances, all video, audio, high speed data and low speed data are stored in a single set of host computer interface receive buffers. Under other operating conditions, the interface subsystem may receive audiovisual information of individual streams from multiple ISDN connections, such as several H0-connections 64. If this second situation occurs, video, audio, fast data, and slow data extracted from audiovisual information are stored in several sets of host computer interface receive buffers. This second mode of operation of the interface subsystem allows the establishment of an audiovisual teleservice that is fully compatible with the CCITT H.221 Recommendation.

In order to effectively and efficiently utilize various operating characteristics of the interface subsystem, the interface subsystem exchanges messages with the host digital computer to report its status to the host digital computer and receive control information from the host digital computer. For example, the interface subsystem is adapted to receive messages from a host digital computer that selects video, audio, fast data, and slow data for storage as a set of host computer interface receive buffers or for transmission as audiovisual information from the ISDN interface circuitry. . The interface subsystem also sends a message to the host digital computer when the host computer interface receive buffer set is full of data. Correspondingly, the interface subsystem sends a message to the host digital computer if the host computer interface transmit buffer set has insufficient data.

An advantage of the present invention is the use of a digital computer using an ISA bus for receiving and / or transmitting digital audiovisual information in accordance with the CCITT H.221 Recommendation.

Other features, objects, and advantages will become apparent to those skilled in the art from the following detailed description of the preferred embodiment, as illustrated in the various figures.

[Brief Description of Drawings]

1 is a diagram illustrating the data transfer relationship between the B and D channels of three ISDN basic rate accesses and the layer indicating the CCITT H.221 recommendation, and the data transfer relationship between the H.221 layer and the coating layer.

2 is a diagram illustrating the data transfer relationship between the B channel and the D channel of the ISDN main rate access and the layer indicating the CCITT H.221 recommendation, and the data transfer relationship between the H.221 layer and the coating layer.

Figure 3 shows the data transfer relationship between the B and D channels of the H11-connection consisting of ISDN main rate access and ISDN base rate access, and the layer indicating the CCITT H.221 Recommendation, and the data transfer relationship between the H.221 layer and the coating layer. Figure is an illustration.

4 is a functional block diagram illustrating an interface subsystem including an ISDN basic rate interface circuit, a second interface circuit, a host computer interface circuit, a RAM, and a digital signal processing circuit in accordance with the present invention.

5 shows the data structures present in the RAM of the interface subsystem and in the memory within the host computer interface circuit, and processes video and audio teleservice data through the H.221 layer to apply video, audio, high speed data and low speed data. Figures 5a, 5b and 5c show the interrelationships between the I.400 layer and the drawings used to exchange audiovisual teleservice data upon supply.

Optimal Mode for Implementing the Invention A fourth block diagram illustrates the interface subsystem in dashed line 100 according to the invention. The interface subsystem 100 provides an ISDN base rate interface circuit for exchanging audio-visual teleservice signals with ISDN base rate access 26 (not shown in FIG. 4) via a first ISDN base rate access connector 104. 102). Two pairs of electrical leads 106 couple the first ISDN basic rate access connector 104 to the isolation transformer circuit 108. Isolation transformer circuitry 108 uses Am79C32 ISDN data controller (“IDC”) integrated circuit 112 to exchange audiovisual teleservice signals on ISDN base rate access 26 (not shown in FIG. 4). Isolate from Advanced Micro Devices, Inc., Thomson Place 901, Sunnyvale, California, 94088-3453. IDC 112, commercially available from ("AMD"), is described in more detail in the AMD publication, entitled "Communication Products Overview" in Copyright 1991. AMD Publication No. 15513A. IDC 112 provides data transmission and reception capabilities on two B-channels 22 and D-channels 24 of 4-wire S / T ISDN basic rate access 26. IDC 112 also exchanges audiovisual teleservice signals with Am82525 extended high level serial communication controller (“HSCX”) integrated circuit 114. HSCX 114, available from AMD, is also described in detail in the AMD "Communication Products Overview" publication. When receiving or transmitting an audiovisual teleservice through ISDN base rate access 26, IDC 112 processes the exchanged information over D channel 24, and HSCX 114 handles two B channels 22. Process the exchanged information through

The IDC 112 and HSCX 114 exchange audiovisual information with the digital signal processing circuit 122 via the interface subsystem bus 124. The digital signal processing circuit 122 is preferably a TMS320C25 digital signal processor ("DSP") commercially available from Texas Instruments Inc. ("TI") at 75380-9066, Dallas, Post Office Box 809066, Texas. TMS320C25 is described in detail in TI publication, entitled "TMS320C2X User's Guide" in December 1990, Copyright 1990, TI Publication No. 164907-9721, Revision B. The interface subsystem bus 124 also connects the digital signal processing circuit 122 to the memory 126, the programmable array logic (“PAL”) integrated circuit 128, and the second ISDN interface circuit 130. PAL 128 fits various control signals transmitted by digital signal processing circuit 122 for controlling the operation of IDC 112, HSCX 114, and second ISDN interface circuit 130, and IDC 112. ) Fits the various status signals transmitted by the HSCX 114 or the second ISDN interface circuit 130 and received by the digital signal processing circuit 122. Memory 126 preferably includes 320 kilobytes of static RAM and 64 kilobytes of read-only memory (“ROM”). The ROM of the memory 126 is a " boot routine " that allows a computer program executed by the digital signal processing circuit 122 to be loaded into the RAM of the memory 126 of the host digital computer (not shown in FIG. 4). save only the boot routine).

The second ISDN interface circuit 130 fits the interface subsystem 100 for exchanging additional ISDN access and audiovisual teleservice signals. In a preferred embodiment of the present invention, the second ISDN interface circuit 130 exchanges audiovisual teleservice signals with two additional ISDN base rate access 26 or a single ISDN main rate access 62 as shown in FIG. May be selected to suit the interface subsystem 100. To fit the interface subsystem 100 for exchanging audiovisual teleservice signals with the ISDN main rate access 62, the electrical lead 134 connects a second ISDN interface circuit 130 to the main rate access connector 136. The second ISDN interface circuit 130 is selected from one of two different types of line card sticks (“LCSs”) available from Dallas Semiconductor, South Beltwood Parkway 4401, Dallas, Texas 75244-3292. . To fit the interface subsystem 100 for exchanging audiovisual teleservice signals with 1,536 kbps ISDN primary rate access 62 of the type used in various countries throughout the world, such as the United States and Japan, the second ISDN interface circuit 130 DS2283 Enhanced TILCS is preferred. In order to adapt the interface subsystem 100 for exchanging audiovisual teleservice signals with 2.048 kbps ISDN main rate access used in various countries in Europe, the second ISDN interface circuit 130 is preferably DS2281 CEPT LCS. The DS2283 LCS and DS2281 LCS are described in detail in the Dallas Semiconductor 1992-1993 Product Data Book. In order to fit the interface subsystem 100 for exchanging audiovisual teleservice signals with two additional ISDN basic rate access 26, the second ISDN interface circuit 130 is connected to one HSOX 114, two IDCs 112. ), Two isolation transformer circuits 108, two double pair electrical leads 106, and two ISDN basic rate access connectors 104, which interface sub-sections in substantially the same manner as shown in FIG. 4. Interconnected with the system bus 124 and the PAL 128, respectively.

If the interface subsystem 100 exchanges an H12-connection and an audiovisual teleservice signal as described above, the interface subsystem is responsible for the 30 B channels of ISDN main rate access 62 at a combined data rate of 1,920 kbps. 22) exchange audiovisual information. The H.221 layer 28 of this interface subsystem 100 is also favored by only six B channels 22 of the 30 or 24 B channels 22 provided by the ISDN main rate access 62. The H0-connection and audiovisual information can be exchanged at a 384 kbps data rate. Similarly, the H.221 layer 2S of the interface subsystem 100 may include one to six B channels 22 of the 30 or 24 B channels 22 provided by the ISDN main rate access 62. Audiovisual information can be exchanged at 64 kbps to 384 kbps data rates. If the above-described interface subsystem 100 exchanges audiovisual teleservice with the H11-connection 72 shown in FIG. 3 and not the H12-connection, the H12-connection is operated when the interface subsystem 100 operates. The only difference from that is that the maximum rate at which H.221 layer 28 exchanges audiovisual information with ISDN main rate access 62 is reduced from 1.920 kbps to 1,535 kbps. The reason for this decrease in maximum data rate is that the ISDN main rate access 62 of the H11-connection 72 provides only 24 B channels 22 rather than the 30 B channels 22 provided by the H12-connection. Because.

When the interface subsystem 100 only exchanges audiovisual teleservice signals with the ISDN main rate access 62, the H.221 layer 28 of the interface subsystem 100 is delimited by the ISDN main rate access 62. It exchanges audiovisual information at 384 kbps data rate with the H0-connection provided by only six B channels 22 of the 30 or 24 B channels 22 provided. Alternatively, the H.221 layer 28 of the interface subsystem 100 may include one to six B channels 22 of the 30 or 24 B channels 22 provided by the ISDN main rate access 62. And audio / video information can be exchanged in increments of 64 kbps and 64 kbps to 384 kbps. If the interface subsystem 100 exchanges audiovisual teleservice signals with one to three ISDN base rate access 26, the H.221 layer 28 of the interface subsystem 100 is a single ISDN base rate. 1 to 2 B channels 22 provided by access 26 and 1 to 4 B channels 22 provided by two ISDN base rate access 26, with a data rate of 64 kbps or 128 kbps. Increments by 64 kbps using a data rate of 64 kbps to 256 kbps and 64 by 1 kbps using 1 to 6 B channels 22 provided by three ISDN base rate accesses 26. Audiovisual information can be exchanged at a data rate of kbps to 384 kbps.

The multitasking computer program stored in the memory 126 and executed by the digital signal processing circuit 122 is an ISDN basic rate interface circuit 102 for performing the exchange of audiovisual information between the various ISDN accesses and the interface subsystem 100. And oversee the entire operation of the second ISDN interface circuit 130. Accordingly, the computer program executed by the digital signal processing circuit 122 is received or transmitted from these ISDN accesses according to the protocol set by CCITT Q.921 Recommendations, Q.931 Recommendations, H.242 Recommendations, and H.221 Recommendations. Process digital data.

The interface subsystem bus 124 also connects the digital signal processing circuit 122 and the memory 126 to the interface subsystem transceiver 142 included in the host computer interface circuit 144. The interface subsystem transceiver 142 is coupled to a shared RAM 146 that stores 32 kilowords of data. The shared RAM 146 is also connected to an ISA bus transceiver 148 that is coupled to a connector 152 that is inserted into an ISA bus (not shown in FIG. 4). The arbitration circuit 154 is connected to the interface subsystem transceiver 142, the ISA bus transceiver 148, and the ISA connector 152. In response to request signals received from interface subsystem transceiver 142, ISA bus transceiver 148, and ISA connector 152, reinforcement circuit 154 controls digital signal processing circuitry for the operation of shared RAM 146. 122 or the host computer that controls the operation of the ISA bus (not shown in FIG. 4). The host computer interface circuit 144 allows a computer program executed by the digital signal processing circuit 122 and a computer program executed by the host computer to interact with each other so that the interface subsystem 100 may interact with several ISDN accesses. Allows the host computer to control the overall operation of the interface subsystem 100 while exchanging audiovisual information and exchanging video, audio, fast data and slow data with the host computer.

The diagram formed by the combination of FIGS. 5A, 5B, and 5C in the manner shown in FIG. 5 shows some of the RAM and shared RAM 146 contained in the memory 126 of the interface subsystem 100. Different data structures are shown.

The data structures shown in FIGS. 5A, 5B, and 5C in combination are used and applied in an audiovisual teleservice exchange with the I.400 layer 30 when processing data through the H.221 layer 28. Layer 44 is used to feed video, audio, high speed data and low speed data. In order to provide a comprehensive background of all the information relating to the realization of such audiovisual teleservices, Applicants have presented CCITT I.400, Q.921, Q.931, H.242 and H.221 recommendations herein as reference. .

As detailed in TI's "TMS320C2X User's Guide" publication, a preferred digital signal processing circuit 122 is provided with two memory map 16-bit word registers for sending data to and receiving data from the serial port. It includes a serial port. These registers are shown in FIG. 5A and are referred to as data transmit registers ("DXR") 202 and data receiver registers ("DRR") 204, respectively. The DXR 202 holds data that the digital signal processing circuit 122 automatically transmits from the serial port. The DRR 204 holds data that is automatically received by the serial port through the operation of the digital signal processing circuit 122. When the interface subsystem 100 exchanges data with the ISDN main rate access 65, the digital signal processing circuit 122 is 16 bits into the DXR 202 for transmission from the serial port of the digital signal processing circuit 122. Serial contained in a multi-task computer program performed by digital signal processing circuit 122 to load words and to retrieve 16-bit words from DRR 204 received by the serial port of digital signal processing circuit 122. Generates an interrupt every 8 to 10 microseconds that requires a port interrupt manipulation routine.

As indicated by solid arrow 206 in FIG. 5A, the RAM of memory 126 is directed to TXA 208A and TXB 20B, respectively, to supply the next 16-bit word to DXR 202 every 8 to 10 seconds. Called contains a pair of linear buffers. To receive the next 16-bit word from the DRR 204 every 8 to 10 microseconds, as indicated by the solid arrow 212 in FIG. 5A, another pair of RAMs in the memory 126 are called RXA 214A and RXB 214B, respectively. Contains a linear buffer. If ISDN main rate access 62 has 24 time slots, each buffer TXA 208A, TXB 208B, RXA 214A and RXB 214B stores 960 16-bit word data. If the ISDN main rate access 62 has 30 time slots, each of the buffers TXA 208A, TXB 208B, RXA 214A and RXB 214B stores 1280 16 bit word data.

When the serial port interrupt manipulation routine responds to the continuous interrupt, it retrieves the data word from the consecutive locations in the linear buffer TXA 208A or TXB 208B and stores the data words in the consecutive locations corresponding to the linear buffers RXA 214A or RXB 214B. When the serial port interrupt manipulation routine reaches the end of a pair of linear buffers TXA 208A and RXA 214A or TXB 208B and RXB 214B, it sends an action at the start of the other pair of linear buffers. In FIG. 5A a pair of dashed arrows 216, 218 indicate that linear buffers TXB 208B and RXB 214B are not currently used to provide data to and receive data from DXR 202, which are Used in depletion of the linear buffers TXA 208A and RXA 214A. In this manner, the serial port interrupt manipulation routine pings back and forth continuously between a pair of linear buffers TXA 208A and 214A and another pair of linear buffers TXB 208B and RXB 214B. Whenever a serial port interrupt manipulation routine switches between a pair of TXA 208A and RXA 214A and another pair of TXB 208B and RXB 214B, it is the first half routine contained in the multitasking computer program performed by the digital signal processing circuit 122. Generates an interrupt that activates. When the first half routine is activated by an interrupt generated by the serial port interrupt manipulation routine, the first half routine receives audiovisual information received by the digital signal processing circuit 122 where the serial port interrupt manipulation routine has been stored by the RXA 214A or RXB 214B. Process and load new audiovisual information into TXA 208A or TXB 208B to prepare it for subsequent transmission from digital signal processing circuit 122.

When the serial port interrupt manipulation routine generates an interrupt, the audiovisual information present in the RXA 214A or RXB 214B shall be processed in accordance with CCITT H.221 and H.242 recommendations to extract video, audio, high speed data and low speed data. In particular, the audiovisual information present in RXA 214A or RXB 214B must be processed in H.221 layer 28 to recover the FAS and BAS embedded in the audiovisual information. The H.221 layer 28 of the receiving terminal processes the audiovisual information in the RXA 214A or RXB 214B to locate and extract the FAS and BAS before properly extracting the video, audio, fast data and slow data from the received audiovisual information. Should be.

As set out in more detail in the CCITT H.221 Recommendation, the lowest level audiovisual information is organized into groups called octets, each holding 8 bits of digital data. The 80 octets are then stacked vertically to form a frame that is 8 bits wide and 80 octets high. When audiovisual information exchanged over ISDN B channel 22 is organized in this manner, the eighth bit of each octet forming a vertical column 80 bits high along the right edge of the frame is called the service channel ("SC"). The FAS consists of eight consecutive bits in the SC located in the upper right corner of the frame from the eighth bit of the first octet to the eighth bit of the eighth octet. For even frames, the FAS has a bit pattern "X0011011", and for odd frames, the FAS has a bit pattern "X1XXXXXX". The value 0 or 1 assigned to the first bit of the FAS is used to define the milliframe structure described in more detail below. The value assigned to the 3rd to 8th bits of the FAS in the odd frame carries control information, alarm information and error checking information.

Similar to the FAS, the BAS consists of eight bits located just below the FAS of the SC in the eighth bit of the ninth octet and the eighth bit of the sixteenth octet. The BAS of each frame defines the codewords that specify the protocol for exchanging audiovisual information, i.e. the terminal ability to transmit and receive audiovisual information, and the video, audio, high speed data, and low speed data as audiovisual information exchanged through ISDN access. Send a codeword that specifies how to multiplex.

H12-connection. In the case of H11-connection 72 and H0-connection 64, one B channel 22 called I channel contains FAS, BAS and other control data defined according to CCITT H.221 Recommendation. When exchanging audiovisual information according to H.221 Recommendations, all remaining B channels 22 of the ISDN service transmit only audiovisual information.

In addition to octets and frames, the CCITT H.221 Recommendation describes a high-level structure called multiframe, consisting of 16 consecutive frames of audiovisual information. In addition, the CCITT H 221 Recommendation subdivides each multiframe into eight two-frame submultiframes. In each frame, the first bit of the FAS carries multiframe information.

As shown in FIG. 5A, the serial port interrupt manipulation routine is using linear buffer pairs TXA 208A and RXA 214A for responding to serial port interrupts, and the first half routine is represented by RXB as indicated by arrows 222A through 222AD. Data of previously stored 16-bit words is transferred to one or more circular buffers 224A through 224AD located in RAM of memory 126. If interface subsystem 100 exchanges audiovisual information with ISDN main rate access 62, each circular buffer 224 stores four frames of audiovisual information. Dotted lines are used to outline circular buffers 224B through 224AD, and circular buffers 224B through 224AD store data from RXB 214B or RSA 214A depending on the type of ISDN access through which interface subsystem 100 exchanges data. It is also used for the arrows 222B to 222AD because there is no need. Each circular buffer 224A through 224AD stores audiovisual information received over one B channel 22 of ISDN access. Thus, when interface subsystem 100 exchanges information with an H12-connection, all thirty circular buffers 224A through 224AD are required to store audiovisual information received via ISDN access. When interface subsystem 100 currently exchanges audiovisual information with H11-connection 72, only 24 circular buffers 224A through 224X are required to store audiovisual information received via ISDN access. When the interface subsystem 100 exchanges audiovisual information through a single H0-connection 64, six circular buffers 224A through 224F are required to store audiovisual information. When the interface subsystem 100 exchanges audiovisual information through one to three ISDN base rate access 26, only one to six circular buffers 224A to 224F are needed to store the audiovisual information. .

Associated with each circular buffer 224A through 224AD is a 15 word length record 232A through 232AD in the B channel directory 234 located in the RAM of the memory 126. The table below describes the data and locations stored in each of the 30 records 232A through 232AD of the various words in the B channel directory 234.

Arrow 242A in FIG. 5A indicates the definition by START-ADDRESS of the first record 232A of the B channel directory 234 of the first word place in circular buffer 224A. Arrow 244A indicates the definition by the END-ADDRESS word of the first record 232A location of the B channel directory 234 of the last word in circular buffer 224A. Arrow 246A indicates the definition by the WRITE-ADDRESS word in the first record 232A of the B channel directory 234 of the circular buffer 224A location where the next word from RXA 214A or RXB 214B will be stored. Arrow 248A indicates the first record of B channel directory 234 at the first byte of circular buffer 224A in frame 252 of audiovisual information for channel B 22 in each circular buffer 224A through 224AD. Indicate the provisions by ADDRESSO in 232A). 5A and 5B include corresponding arrows 232AD, 234AD, 236AD and 238AD indicating the definition by the last record 232AD in the B channel directory 234 in the same relationship as the 30 th circular buffer 224AD. do.

Each circular buffer 224A through 224AD stores audiovisual information from four or more consecutive frames 252, that is, audiovisual information of 160 sixteen bit words. The dotted line 254 indicates the boundary between adjacent frame size regions of the storage place in the circular buffers 224A to 224AD. However, the continuous frames 252 of audiovisual information stored in circular buffers 224A through 224AD are not necessarily required and are not aligned with the boundaries indicated by dashed lines 254. The first and last words in each circular buffer 224A through 224AD are each aligned on a decimal 40 word boundary. Once the first and last words of circular buffers 224A through 224AD are aligned on a 40 word boundary, only at the end of each sequence of 80 16-bit word data transfers from RXA 214A or RXB 214B to each circular buffer 224A through 224AD One can test the address wrap from the end of circular buffers 224A through 224AD to its starting point.

Although circular buffers 224A through 224AD shown in FIG. 5A illustrate skews that can occur between audiovisual information transmitted over independent B channels 22, strictly speaking, this figure illustrates the interface subsystem 100's. The H.221 layer 28 allows for accurate reception of audiovisual information from a single B channel 22 of an H12-connection, an H11-connection 72, a single H0-connection 64, or an ISDN basic rate access 26. It is not shown. As discussed above, the CCITT ISDN Recommendation preserves the internal B channel phase relationship for H12-connection, H11-connection 72 and H0-connection 64. That is, audiovisual exchanged over 30 B channels 22 in H12-connection, 24 B channels 22 in ISDN main rate access 62, or 6 B channels 22 in H0-connection 64 None of the frames 252 of information is skewed as shown in FIG. 5A. However, as noted above, the skew illustrated in FIG. 5A may occur among the B channels 22 of two or more H0-connections 64 or several B of one or more ISDN base rate access 26. May occur among the channels 22. When using these latter types of ISDN services, the interface subsystem 100 of the present invention locates audiovisual information in several B channels 22 by positioning FAS embedded in audiovisual information stored in circular buffers 224A through 224AD. Can be properly aligned. In positioning the FAS embedded in the audiovisual information stored in the circular buffers 224A through 224AD, the computer program executed by the digital signal processing circuit 122, as indicated by the arrows 262A through 262AD, is stored in the memory 126. In order to classify buffers 264A to 264AD (shown in FIG. 5B) located in RAM, 40 word segments are moved from each circular buffer 224A to 224AD that stores audiovisual information. Although the preferred digital signal processing circuit 122 addresses the full word of memory to facilitate the discovery of the FAS and the subsequent processing of audiovisual information, the 80 addresses in each classification buffer 264A through 264AD. A poor word keeps only one octet of audiovisual information. After the computer program has moved the audiovisual information into the classification buffers 264A through 264AD, the program only scans the classification buffers 264A through 264AD containing the channel audiovisual information to find the FAS that should be there. After the computer program executed by the digital signal processing circuit 122 sets the starting position of the frame 252 in that channel by looking for the FAS in the classification buffers 264A through 264AD, the ADDRESSO causes the appropriate circular buffer 224A to be set. To 224AD, assigns a value to ADDRESSO in the appropriate record 232A-232AD of the B-channel directory 234, which defines the starting location of frame 252.

After an appropriate value has been assigned to the ADDRESSO word for all circular buffers 224A to 224AD with audiovisual information, the computer program executed by the digital signal processing circuit 122 is classified with an octet of data constructed as described above. The frame 252 of audiovisual information from circular buffers 224A through 224AD, which stores audiovisual information in buffers 264A through 264AD, is transmitted. Therefore, if all the frames of audiovisual data are properly recorded in the classification buffers 264A to 264AD, the computer program executed by the digital signal processing circuit 122 extracts the BAS from the I channel audiovisual information. At this point, the computer program executed by the digital signal processing circuit 122 also processes audiovisual information in accordance with the CCITT H.221 Recommendation to extract video, audio, slow data and high speed data, thereby receiving the video data. Suitably store in video data buffer 274 as indicated by arrows 272A through 272AD, and suitably store audio data in received audio data buffer 278 as indicated by arrows 276A through 276AD, and arrows 282A through 282AD. Stores the high speed data in the received high speed data buffer 284 as indicated by < RTI ID = 0.0 >), and < / RTI > The received video data buffer 274, the received audio data buffer 278, the received fast data buffer 284 and the received slow data buffer 288 are all located in the RAM of the memory 126.

When supplying audiovisual information to the TXA 208A and TXB 208B, the first half operation uses a data storage structure in RAM of memory 126, which is an RXA except for omitting circular buffers 224A through 224AD. Processing the received audiovisual information stored with 214A and RXB 214B is the same as described above. Thus, the task of the first half in creating video, audio, high speed data and low speed data for transmission to TXA 208A and TXB 208B by serial or interrupt routine is to receive received low data buffer 288, received high speed data buffer 284. A copy of the received audio data buffer 278, the received video data beeper 274, and the classification buffers 264A-264AD.

5B and 5C, the shared RAM 146 included in the host computer interface circuit 144 includes various messages, video, audio, and / or messages between the interface subsystem 100 and the host digital computer (not shown). It provides storage for various data structures used to exchange high speed data and low speed data. Thus, shared RAM 146 stores a pointer structure that holds addresses of other structures used to exchange messages and data. In order to avoid confusion due to complexity in FIG. 5, the details of the addresses stored in the pointer structure 302 have been omitted from the figure. The information stored in the pointer structure 302 functions analog to START_ADDRESS, END-ADDRESS, WRITE_ADDRESS and ADDRESSO stored in each record 232A through 232AD in the B channel directory 234. The information stored in the pointer structure 302 allows the computer program executed by the digital signal processing circuit 122 and the host digital computer to access the structure in the shared RAM 146 used to exchange messages and data. Computer programs executed by the digital signal processing circuit 122 and the host digital computer may also use the information stored in the pointer structures 302 to monitor the status of these structures.

The information stored in the pointer structure 302 causes a computer program executed by the digital signal processing circuit 122 to provide a message for the host digital computer to the host computer message queue 304 located in the shared RAM 146. The host computer message queue 304 draws messages from computer programs executed by the digital signal processing circuit 122 as indicated by arrow 306 and computer programs executed by the host digital computer as indicated by arrow 308. Receive a message. In addition, the information stored in the pointer structure 302 allows a computer program executed by the digital signal processing circuit 122 to access a message stored in the interface subsystem message queue 312 located in the shared RAM 146. The interface subsystem message queue 312 receives messages from the host digital computer indicated by arrow 314 and messages fetched by the computer program executed by the digital signal processing circuit 122 as indicated by arrow 316.

In addition to the host computer message queue 304 and the interface subsystem message queue 312, the pointer structure 302 also allows the digital signal processing circuit 122 and the computer program executed by the host digital computer to share in the shared RAM 146. Enables the exchange of video, audio, fast data and slow data stored in one or more session block 318 located. One session block 318 is a separate set of video, audio, high-speed data, and low-speed data that interface subsystem 100 exchanges over separate ISDN connections, such as individual H0-connections 64 or individual B channels 22. Is required for. Included in each session block 318 is a session ID 322 that uniquely distinguishes each session and its associated ISDN connection.

Each session block 318 also includes a received video circular buffer 324. The computer program executed by the digital signal processing circuit 122 fetches video data from the received video data buffer 274 and stores it in the received video circular buffer 324 as indicated by arrow 326. The computer program executed by the host digital computer fetches video data from the received video circular buffer 324 as indicated by arrow 328. Session block 318 also includes a received audio circular buffer 332. The computer program executed by the digital signal processing circuit 122 fetches audio data from the received audio data buffer 278 and stores it in the received audio circular buffer 332 as indicated by arrow 334. The computer program executed by the host digital computer fetches audio data from the received audio circular buffer 332 as indicated by arrow 336. Session block 318 also includes a fast data circular buffer 342 received. The computer program executed by the digital signal processing circuit 122 fetches high speed data from the received high speed data buffer and stores it in the received high speed data buffer 342 as indicated by arrow 344. The computer program executed by the host digital computer fetches high speed data from the received high speed data circular buffer 342 as indicated by arrow 346. Session block 318 also includes a received slow data circular buffer 352. The computer program executed by the digital signal processing circuit 122 receives the low speed data from the received low data buffer 288 and stores it in the received low data circular buffer 352 as indicated by arrow 354. The computer program executed by the host digital computer fetches low speed data from the received sequential data circular buffer 352 as indicated by arrow 356.

Each session block 318 also includes a transmitted video circular buffer 362. The computer program executed by the host digital computer stores video data to be transmitted from the interface subsystem 100 in the transmitted video circular buffer 362 as indicated by arrow 364. The computer program executed by the digital signal processing circuit 122 retrieves the video data stored in the transmitted video circular buffer 362 and stores it in the transmitted video data buffer (not shown in the figure) as indicated by arrow 366. . Session block 318 also includes an audio circular buffer 372 to be transmitted. The computer program executed by the host digital computer stores audio data to be transmitted from the interface subsystem 100 in the transmitted audio circular buffer 372 as indicated by arrow 374. The computer program executed by the digital signal processing circuit 122 retrieves the audio video data stored in the transmitted audio circular buffer 372 and stores it in the transmitted audio data buffer (not shown in the figure) as indicated by the arrow 376. do. Session block 318 also includes a fast data circular buffer 382 transmitted. The computer program executed by the host digital computer stores the high speed data to be transmitted from the interface subsystem 100 in the high speed data circular buffer 382 transmitted as indicated by arrow 384. The computer program executed by the digital signal processing circuit 122 retrieves the fast data stored in the transmitted fast data circular buffer 382 and transmits the fast data buffer (not shown) session block (as shown by the arrow 386). 318 includes a slow data circular buffer 392 transmitted. The computer program executed by the host digital computer stores the slow data to be transmitted from the interface subsystem 100 in the transmitted slow data circular buffer 392 as indicated by arrow 394. The computer program executed by the digital signal processing circuit 122 fetches the slow data stored in the transmitted slow data circular buffer 392 and stores it in the transmitted slow data buffer (not shown) as indicated by the arrow 396. do.

Having multiple session blocks 318 in the shared RAM 146 allows the interface subsystem 100 to adapt to different communication environments efficiently and flexibly. For example, interface subsystem 100 may exchange audiovisual information in a single stream with two H0-connections 64 to obtain a data transfer rate of 768 kbps. Under these circumstances, two H0-connections 64 function as a single connection, while shared RAM 146 provides a single set of circular buffers 324, 332, 342, which pass all video, audio, high-speed data, and low-speed data. There is a need to provide a single session block 318 with 352, 362, 372, 382, 392.

Alternatively, interface subsystem 100 may exchange audiovisual information of two H0-connections 64 and two separate streams. In this second operating environment, two H0-connections 64 operate as separate ISDN connections, and the shared RAM 146 has two separate and independent passes through separate streams of video, audio, high speed data, and low speed data. At least two session blocks 318 with an inset of circular buffers 324, 332, 342, 352, 362, 372, 382, 392 should be provided. This second mode of operation for the interface subsystem l00 is the video, audio, high speed, where the interface subsystem 100 receives two different telecommunications and the H.221 layer 28 exchanges with the coating layer 44. It is adapted to participate in an audiovisual teleservices conference that preserves the identity of the two communications in data and slow data. By preserving the identity of the two communications in the data exchanged between the interface subsystem 100 and the host digital computer, the interface subsystem 100 allows the computer program executed by the host digital computer to be individually audiovisual on one half of the display screen. Allows you to synthesize composite displays that provide half of the data from a teleservice. Alternatively, a computer program executed by a host digital computer may use the entire screen of the display for one audiovisual teleservice while providing another audiovisual teleservice in a small window located within the larger display.

When the interface subsystem 100 operates to preserve the identity of two or more separate communications exchanged with individual ISDN connections, the computer program executed by the digital signal processing circuit 122 may store audiovisual information in the classification buffer 264A. To audiovisual information from the circular buffers 224A to 224AD, which are stored in the second through 264AD units, the identity of such communication is set. Thus, when the interface subsystem 100 operates in this manner, the computer program executed by the digital signal processing circuit 122 may reside in classification buffers 264A through 264D, each of which stores audiovisual information for separate operations. Differentiate groups that can prove identity.

A computer program executed by the digital signal processing chip 122 and the host digital computer to control the operation of the interface subsystem 100 for exchanging video, audio, fast data and slow data with the host digital computer as described above. Exchanges various messages via host computer message queue 304 and interface subsystem message queue 312. Listed below are various messages specifically related to audiovisual teleservice communication in which a computer program executed by the digital signal processing circuit 122 may be placed in the host computer message queue 304.

NEW_RX_BAS: This message informs the host digital computer that the computer program executed by the digital signal processing circuit 122 has identified a new and meaningful BAS in the received audiovisual information.

NEW_TX_BAS: This message informs the host digital computer that the computer program executed by the digital signal processing circuit 122 has begun to produce audiovisual information for transmission from the interface subsystem 100 in a new and meaningful different way.

RX_FRAMING_LOST: This message informs the host digital computer of a loss of frame or multiframe synchronization in the received audiovisual policy.

TX_FRAMING_LOST: This message informs the host digital computer that a terminal receiving audiovisual information sent from interface subsystem 100 has reported a frame or multiframe loss of synchronization.

H221_SYNC: This message informs the host digital computer that H.221 frame synchronization has been achieved by the interface subsystem 100 for received audiovisual information and the terminal receiving audiovisual information transmitted from the interface subsystem 100. .

NEW_CAPABILITY: This message informs the host digital computer that a provision of a new capacity has been received from audiovisual information in accordance with CCITT H.242 Recommendations.

RX_QUE_FULL: This message indicates that the received video circular buffer 324, the received audio circular buffer 332, the received fast data circular buffer 342 or the received low data circular buffer 352 are full and the digital signal processing is performed. The computer program executed by the circuitry 122 notifies the host digital computer that it has begun to discard the received video, audio, fast data and / or slow data.

TX_QUE_EMPTY: This message indicates that the transmitted video circular buffer 362, the transmitted audio circular buffer 372, the transmitted fast data circular buffer 382 and / or the transmitted slow data circular buffer 392 are empty, If the computer program executed by the digital signal processing circuit 122 did not properly prepare for the occurrence of this situation by a message from the host digital computer, the interface subsystem 100 begins to transmit 0 as audiovisual information. Notify the host digital computer.

Listed below are various messages related to audiovisual teleservice communication in which a computer program executed by the digital signal processing circuit 122 can retrieve from the interface subsystem message queue 312.

SET_CAPABILITIES: This message instructs the computer program executed by the digital signal processing circuit 122 to send a provision of a new capacity to a terminal that receives audiovisual information from the interface subsystem 100 in accordance with CCITT H.242 recommendations. .

GET_CAPABILITIES: This message instructs the computer program executed by the digital signal processing circuit 122 to send a NEW_CAPABILITIES message back to the host computer informing the definition of the current capacity of the other terminal.

IMMEDIATE_BAS: This message is performed by the digital signal processing circuit 122 to transmit a BAS code defined in a terminal that receives audiovisual information from the interface subsystem 100 and transmit subsequent audiovisual information according to this defined BAS code. Instructs the computer program to become.

FRAME_CHANNEL: This message instructs the computer program performed by the digital signal processing circuit 122 to begin framing in accordance with the CCITT H.221 Recommendation for a defined session audiovisual teleservice.

IMMEDIATE_BAS_SWITCH: This message sends a BAS code defined in a terminal that receives audiovisual information from the interface subsystem 100, transmits subsequent audiovisual information according to this defined BAS code, and has a prototype in a different session block 318. Instructs the computer program executed by the digital signal processing circuit 122 to start exchanging buffers with video, audio, high speed data, and low speed data.

EMPTY_BAS_SWITCH: This message transmits the BAS code defined in the terminal that receives audiovisual information from the interface subsystem 100, transmits the video circular buffer 362, the transmitted audio circular buffer 372, the transmitted fast data. Instructs the computer program executed by the digital signal processing circuit 122 to start transmitting subsequent audiovisual information according to the prescribed BAS code when the circular buffer 382 or the transmitted low data circular buffer 392 becomes empty. .

MEMORY_CONTROL: This message stores or transmits data in the received video circular buffer 324, the received audio circular buffer 332, the received fast data circular buffer 342, or the received slow data circular buffer 352. To start or end fetching data from video circular buffer 362, transmitted audio circular buffer 372, transmitted fast dada circular buffer 382, or transmitted slow data circular buffer 392 as specified in the message. Instructs the computer program executed by the digital signal processing circuit 122. By sending this message, the computer program executed by the host digital computer is stored in the circular buffers 324, 332, 342, 352 by the computer program executed by the digital signal processing circuit 122. Select from high speed data and low speed data. This message also allows a computer program executed by the host digital computer to select among video, audio, fast data and slow data for transmission from the circular buffers 362, 372, 382, 392 by the interface subsystem 100. .

In addition to the various messages listed above specifically related to audiovisual teleservice communication, computer programs executed by the digital signal processing circuit 122 and the host digital computer set up and terminate audiovisual teleservices such as placing telephone calls and allowing telephone calls. And exchange various messages related to responding to other types of telephone system control signals, such as dual tone multi-frequency ("DTMF") signals.

[Industry availability]

Interface subsystem 100 having circular buffers 224A through 224AD, which provides storage only for 120 frames 252 of audiovisual information in RAM of memory 126, has an independent B channel ( Only a limited amount of skew is allowed between 22). For example, if audiovisual information is exchanged over two H0-connections 64 to obtain a combined data transfer rate of 768 kbps, the interface subsystem 100 will accommodate approximately 140 milliseconds of skew between them. Can be. Under this situation, a storage location for 24 frames 252 is allocated to the circular buffers 224A through 224AD for the six B channels 22 arriving at the latest in time. The remaining storage for 96 frames 252 is allocated to circular buffers 224G through 224L for the six B channels 22 that arrive the earliest in time. If the skew between two H0-connections 64 exceeds the maximum allowed, one of the two connections must terminate and the telephone call must be replaced until two connections with an acceptable amount of skew are obtained. If it must be able to accommodate the largest amount of skew between independent B channels 22, this can be achieved by increasing the storage capacity of the memory 126 RAM available to the circular buffer 224.

The received video circular buffer 324, the received audio circular buffer 332, the received fast data circular buffer 342, and the received slow data circular buffer 352 are extracted from the audiovisual information and then extracted from audio, video, high speed. A host computer interface receive buffer is provided for receiving data and slow data. Similarly, the transmitted video circular buffer 362, the transmitted audio circular buffer 372, the transmitted fast data circular buffer 382 and the transmitted slow data circular buffer 392 are audiovisual from the interface subsystem 100. A host computer interface transmission buffer is provided for supplying video, audio, high speed data and low speed data for transmission as information. Although the preferred embodiment of the interface subsystem 100 utilizes circular buffers 324, 332, 342, and 352, other structures are known that function the same as these circular buffers 324, 332, 342, and 352. have. In particular, a first-in, first-out structure ("FIFOS") is a combination buffer of the received video data buffer 274 and the received video circular buffer 324, of the received audio data buffer 278 and the received audio circular buffer 332. Is equivalent to a combination buffer, a combination buffer of the received fast data buffer 284 and the received fast data circular buffer 342, and a combination buffer of the received low data buffer 288 and the received low data circular buffer 352. It may be used instead of these. Similarly, FIFOS combines the transmitted video circular buffer 362 with the transmitted video data buffer, the combined audio circular buffer 372 with the transmitted audio data buffer, and the transmitted fast data circular buffer. The combination buffer 382 with the transmitted high speed audio data buffer and the combined slow data circular buffer 392 with the transmitted slow data buffer are equivalent and can be used instead.

Although the interface subsystem 100 is described in connection with the exchange of audiovisual teleservices using ISDN communications, the interface subsystem 100 provides for other digital communications services that are compatible with CCITT H.221 Recommendations, such as T1 switching 56. I can accept it. Interface subsystem 100 may be readily used to transmit and / or receive digital data of the type using ISDN communication. The use of this interface subsystem 100 can be realized without changing the multi-tasking computer program carried out by the digital signal processing circuit 112. In addition, interface subsystem 100 may be used to transmit and / or receive digital data using a suitable coating layer computer program executed by a host digital computer.

Although the present invention has been described based on the preferred embodiments, it should be understood that this description is for illustrative purposes only and should not be construed as limiting. As a result, those skilled in the art will appreciate that various modifications, modifications and / or other applications are abundant without departing from the spirit and scope of the invention. Accordingly, the following claims should be construed as including all modifications, modifications or other applications falling within the true spirit and scope of the present invention.

Claims (32)

An interface subsystem for exchanging digital audiovisual information using digital telecommunications and exchanging video and audio data with a host digital computer, comprising: a first digital telecommunications interface circuit for exchanging digital audiovisual information with a first digital telecommunication access; A host computer interface circuit for exchanging video and audio data with the host digital computer, a random access memory for storing digital audiovisual information and video and audio data received from the interface circuit, and coupled to the interface circuit and random access memory. Control the operation of the interface circuitry, exchange digital audiovisual information with the digital telecommunications interface circuitry, exchange video and audio data with the host computer interface circuitry, and Interface subsystem comprising the audio-visual information and a programmable digital signal processing circuit for processing video and audio data. The interface subsystem of claim 1, further comprising a second digital telecommunications interface circuit for exchanging digital audiovisual information in a second digital telecommunications access. 3. The interface subsystem of claim 2 wherein the first digital telecommunications interface circuitry exchanges digital audiovisual information in an Integrated Services Digital Network ("ISDN") basic rate access. 4. The interface subsystem of claim 3 wherein the second digital telecommunications interface circuitry exchanges digital audiovisual information in a plurality of ISDN basic rate accesses. 4. The interface subsystem of claim 3 wherein the second digital telecommunications interface circuitry exchanges digital audiovisual information in ISDN main rate access. 6. The interface subsystem of claim 5 wherein the programmable digital signal processing circuitry synchronizes digital audiovisual information received by some digital telecommunication access. 6. The interface subsystem of claim 5 wherein the programmable digital signal processing circuit multiplexes digitalized video and audio data exchanged through several telecommunications accesses. 2. The subsystem of claim 1, wherein a read only memory (" ROM ") contained in the random access memory stores a computer program executed by the programmable digital signal processing circuit. 2. The interface subsystem of claim 1 wherein the programmable digital signal processing circuit receives digital viewing angle information of each consecutive word following the reception of the information by the digital telecommunications interface circuit. 2. The interface subsystem of claim 1 wherein the programmable digital signal processing circuit transmits digital viewing angle information of each consecutive word to the digital telecommunications interface circuit. 2. The interface subsystem of claim 1 wherein the programmable digital signal processing circuit controls the operation of the digital telecommunications interface circuit in response to initiation of a digital telecommunications service. 2. The interface subsystem of claim 1 wherein the programmable digital signal processing circuit controls the operation of the digital telecommunications interface circuit to initiate a digital telecommunications service. 2. The interface subsystem of claim 1 wherein the random access memory includes a plurality of receive circuit buffers for receiving a plurality of frames of audiovisual information from the digital telecommunications interface circuit. 2. The apparatus of claim 1, wherein the random access memory includes a plurality of classification buffers, each addressable location of the classification buffer retaining one octet of audiovisual information received from a digital telecommunications access and present in the classification buffer. While the octet is scanned to position the frame alignment signal ("FAS") embedded therein. 15. The system of claim 14, wherein after the FAS is located in the classification buffer, the classification buffer receives audiovisual information of consecutive frames from the digital telecommunication access. And the received audiovisual information is recorded in the classification buffer having the FAS located at the eighth bit of the first octet to the eighth bit of the eighth octet in the classification buffer. 15. The interface of claim 14, wherein after the FAS is located in the classification buffer, video data, audio data, high speed data, and low speed data are extracted from audiovisual information of the classification buffer and stored in separate received data buffers. system. 17. The interface subsystem of claim 16 wherein the respective received data buffers are located in the random access memory of the interface subsystem. 2. The host computer interface receive buffer set of claim 1, wherein the host computer interface receive buffer set stores video data, audio data, high speed data, and low speed data after video data, audio data, high speed data, and low speed data have been extracted from the received audiovisual information. And may be removed from the host computer interface receive buffer set by the host digital computer. 19. The apparatus of claim 18, wherein the host computer interface receive buffer set is located in a shared random access memory disposed within the digital signal processing circuit and the host computer interface circuit that can be directly accessed by the host digital computer. Interface subsystem. 19. The system of claim 18, wherein the digital telecommunications interface circuitry receives a single stream of audiovisual information from a plurality of digital telecommunications connections, wherein video data, audio data, high speed data, and low speed data are extracted from the audiovisual information. An interface subsystem, stored in a set of interface receive buffers. 19. The interface subsystem of claim 18 wherein the host computer interface receive buffer is a circular buffer. 19. The interface of claim 18 wherein the interface subsystem receives messages from the host digital computer selecting video data, audio data, high speed data, and low speed data for storage in the host computer interface receive buffer set. Subsystem. 19. The interface subsystem of claim 18, wherein the interface subsystem sends a message to the host digital computer specifying that the host computer interface receive buffer is full of data. 2. The system of claim 1, wherein the interface subsystem receives video data, audio data, high speed data, and low speed data stored as audiovisual information in a host computer interface transmission buffer by the host digital computer for transmission from the digital telecommunication interface circuit. Interface subsystem. 25. The computer system of claim 24, wherein the interface subsystem is further configured from the host digital computer to select video data, audio data, high speed data, and low speed data as audiovisual information in the host computer interface transmission buffer for transmission from the digital telecommunication interface circuit. Interface subsystem for receiving messages. 25. The interface subsystem of claim 24 wherein the interface subsystem sends a message to the host digital computer specifying that data in the host computer interface transmission buffer is insufficient. 25. The host digital computer of claim 24, wherein the interface subsystem sends a message specifying that audiovisual information should be transmitted in accordance with a new bit rate allocation signal (" BAS ") when data in the host computer interface transmission buffer becomes insufficient. Receiving from the interface subsystem. 2. A separate host computer interface receive buffer set as recited in claim 1, wherein said interface subsystem stores video data, audio data, high speed data, and low speed data extracted from audiovisual information received from an individual digital telecommunication connection by said digital telecommunication interface circuit. Storing in the interface subsystem. 28. The computer system of claim 27, wherein the interface subsystem is separate audiovisual information transmitted by a separate digital telecommunications connection, the host digital computer having a separate set of host computer interface transmission circuits for transmission by the digital telecommunications interface circuit. Interface subsystem for receiving video data, audio data, high speed data, and low speed data stored therein. The interface subsystem of claim 1, wherein the interface subsystem sends a message to the host digital computer specifying that audiovisual information including a new BAS has been received. The interface subsystem of claim 1, wherein the interface subsystem sends a message to the host digital computer specifying that audiovisual information is currently being transmitted in accordance with a new BAS. The interface subsystem of claim 1, wherein the interface subsystem receives a message from the host digital computer that specifies that audiovisual information should be transmitted in accordance with a new BAS.