KR100273303B1 - Cache hit distinction circuit for microprocessor - Google Patents

Abstract

PURPOSE: A circuit for discriminating a cache hit of a microprocessor is provided to reduce the size of a cache tag, and to perform a cache access at high speed by encoding a plurality of TLB hit signals generated from a virtual address tag, by comparing the signal encoded with an index of a TLB tag, and by discriminating whether a cache hit or not. CONSTITUTION: A virtual address tag(211) compares a virtual address with an address stored in the inside, and outputs a hit signal(AHIT) of 64 bits. A PPN(Physical Page Number) memory(212) receives the hit signal, and outputs a physical address(MPPN) of 51 bits from a relevant area. An OR gate(216) executes an OR for the hit signal of 64 bits and outputs a TLB(Translation Look-aside Buffer) hit signal. An encoder(217) encodes the hit signal, and converts the signal into index data(EIND). A cache index tag(213) outputs index data(CIND) of 6 bits from a space, which a virtual address designates. A comparator(214) outputs a cache hit signal or a comparison signal. A cache data memory(215) reads or writes cache data.

Description

Cache Hit Determination Circuit of Microprocessor

The present invention relates to a microprocessor, and more particularly, to enable a translation look-aside buffer (TLB) used in a memory management unit (MMU) to use a tag in common with a cache memory. The present invention relates to a cache hit determination circuit.

1 is a block diagram of a circuit for implementing the prior art, as shown therein, comparing a virtual address VA [63:13] with an address stored therein and outputting a 64-bit hit signal AHIT. PPI that outputs a 51-bit physical address (MPPN) in the address tag 111 and the corresponding region designated by the 64-bit hit signal AHIT from the virtual address tag 111. Physical page number) memory 112, a cache tag 113 for outputting a 51-bit physical address (CPPN) in a region designated by virtual address (VA [12: 5]), and an output of the memory 112 A comparator 114 for comparing the signal MPPN and the output signal CPPN of the cache tag 113 and outputting a comparison signal CHIT indicating a cache hit if it matches and a cache miss if it does not match. And cache data of the area designated by the virtual address VA [12: 5]. The cache data memory 115 outputs.

The virtual address tag 111 is composed of a content addressable memory (CAM: CAM), and stores 64 addresses to store a virtual address (VA [63:13]). It is configured to output the hit signal AHIT, which is '1', only in the region corresponding to.

The PPP memory 112 is composed of a static RAM (SRAM) having a feature of receiving decoded signals directly into a word line without an address decoder.

The virtual address tag 111 and the PPN memory 112 form a transfer translation buffer (TLB), and the cache tag 113 and the cache data memory 115 form a cache, which is a fast buffer memory.

Referring to the operation of the prior art as follows.

Typically cache hits or misses occur in the cache.

In the prior art, the hit or miss operation of a cache during cache access is as follows.

64-bit vitual address space, 64-bit physical address space, 8-Kbyte page size, 64-entry fully-assisted translation look-aside buffer, In the following description, it is assumed to be 'TBI'), 8-Kbyte direct-mapped virtually-indexed physically-tagged cache, and 32-bytecache line size.

First, the virtual address tag 111 is accessed by the input of the virtual address VA [63:13], and the cache tag 113 is accessed by the input of the virtual address VA [12: 5] at the same time.

At this time, the virtual address tag 111 constituted by a content addressable memory (CAM) has a value of '1' only in an area storing an address matching the virtual address (VA [63:13]) among 64 areas. An in hit signal A HIT is generated.

Accordingly, the OR gate 116 logically combines 64 hit signals AHIT from the virtual address tag 111 and outputs a TLB hit signal TLBhit.

If a miss occurs as the TLB hit signal TLBhit output from the OR gate 116 is '0', the microprocessor generates a trap and processes the virtual address (VA [63:13]). ) (VA [12: 5]) is re-entered to repeat the operation.

On the contrary, when the TBI hit signal TLBhit is output as '1' at the OR gate 116 and is hit, the 64 hit signals AHIT from the virtual address tag 111 are directly received as word lines. The PPI memory 112 outputs a 51-bit physical address MPPN in the corresponding area.

The cache tag 113 outputs the page number CPPN stored in the area designated by the virtual address VA [12: 5].

At this time, the comparator 114 compares the physical address MPPN in the PPI memory 112 with the physical address CPPN in the cache tag 113 and compares the hit signal CHIT according to the comparison result. Will print.

Accordingly, when the hit signal CHIT is output as '0' in the comparator 114 and a cache miss occurs, the cache line is output from the external memory using the physical address MPPN output from the PPI memory 112. After retrieving, the operation is repeated by re-inputting the virtual addresses VA [63:13] and VA [12: 5].

On the contrary, when the hit signal CHIT is output as '1' in the comparator 114 and the cache hit occurs, the cache data memory designated by the virtual address VA [12: 5] in the case of the load is loaded. The cache data (CDATA) outputted in the corresponding area of 115 is transmitted as a valid data to the place where the data is requested. ) Is stored in the corresponding area of the designated cache data memory 115.

However, the related art requires a 51-bit * 256 size memory to implement an 8-Kbyte cache according to the assumed conditions, so that the area occupied by the on-chip implementation becomes large.

In particular, if a larger cache memory is used or if the physical address area is larger, the area of the cache tag is increased in proportion and power consumption is increased.

In addition, conventionally, in order to determine the cache hit, the virtual address tag 111, the PPI memory 112, and the comparator 14 must be sequentially accessed, which takes a long time in this process.

Accordingly, the present invention encodes a plurality of TLB hit signals occurring in a virtual address tag and compares the encoded signal with an index for the TLB tag to determine whether a cache hit occurs in order to improve the conventional problem. Accordingly, an object of the present invention is to provide a cache hit determination circuit of a microprocessor invented to reduce cache tag size and to perform cache access at high speed.

1 is a block diagram of a circuit of the prior art;

2 is a block diagram of a circuit for practicing the present invention.

Explanation of symbols on the main parts of the drawings

211: virtual address tag 212: PPI memory

213: cache index tag 214; Comparator

215: cache data memory 216: ora gate

217: Encoder

In accordance with another aspect of the present invention, there is provided a cache hit determination circuit of a microprocessor provided with a cache memory, wherein the plurality of hit signals are encoded by encoding a plurality of hit signals in a virtual address tag that is a shared TLB tag. An encoder for converting to an index number of an area accessed from a tag, a cache index tag for storing index data indicating a storage location of a shared TLB tag, and outputting index data in a corresponding area designated by a virtual address, and the encoder And a comparator configured to compare output signals of the cache index tag and output a signal for determining whether a cache hit occurs.

The cache index tag may be configured as a CAM to invalidate cache lines using a TBI entry, which is replaced when a TBI miss occurs, within an clock.

Hereinafter, the present invention will be described in detail with reference to the drawings.

Fig. 2 is a block diagram of a circuit for implementing the present invention. As shown therein, the virtual address VA [63:13] is compared with the address stored therein to output a 64-bit hit signal AHIT. The PPP (PPN) that receives the address tag 211 and the 64-bit hit signal AHIT from the virtual address tag 211 directly as a word line and outputs a 51-bit physical address (MPPN) in the designated area. Memory 212 and OR gate 216 for ORing the 64-bit hit signal AHIT from the virtual address tag 211 to output a TLB hit signal TLBhit, and the virtual address tag 211. An encoder 217 that encodes a 64-bit hit signal AHIT and converts it into index data EIND of an area accessed by the virtual address tag 211, and a storage area of the virtual address tag 211. Index Days for A cache index tag 213 for storing the data and outputting 6-bit index data CIND in an area designated by the virtual address VA [12: 5], and an output signal EIND of the encoder 217; A comparator 214 for comparing the output signal CIND of the cache index tag 213 and outputting a comparison signal CHIT indicating a cache hit if it does not match and a cache miss if it does not match, and a virtual address; The cache data memory 215 reads cache data in an area designated by (VA [12: 5]) or writes cache data externally to the area.

The virtual address tag 211 and the PPI memory 212 are composed of a content addressable memory (CAM) and a static RAM (SRAM) as in the related art.

The cache index tag 213 is configured as a cam CAM to invalidate all cache lines that use a TLB entry, which is replaced when a TLB miss occurs, as an index.

Referring to the operation and effect of the embodiment of the present invention configured as described above are as follows.

In the present invention, as in the prior art, a 64-bit vitual address space (virtual address area), a 64-bit physical address space (physical address area), an 8-Kbyte page size (page size), and a 64-entry assiciative translation look-up (TLB). Assuming a side buffer, an 8-Kbyte direct-mapped virtually-indexed physically-tagged cache, and a 32-bytecache line size, a cache hit or cache miss determination operation during cache access will be described.

First, the virtual address tag 211 is accessed with the input of the virtual address VA [63:13] and the cache tag 213 is accessed with the input of the virtual address VA [12: 5] at the same time.

At this time, the virtual address tag 211 composed of the content addressable memory (CAM) has a value of '1' only for the corresponding area when there is an address matching the virtual address (VA [63:13]) among the 64 areas. A hit signal A HIT is generated.

Accordingly, the OR gate 216 logically combines the 64 hit signals AHIT from the virtual address tag 211 to output the TLB hit signal TLBhit.

If the TBI hit signal TLBhit outputted from the OR gate 216 is '0' and the TBI miss occurs, the microprocessor generates a trap and inputs valid page conversion information.

At this time, there may be cache lines that use the TBI entry as an index that is replaced by the occurrence of the TBI miss, but since the cache index tag 213 is configured as the cam CAM, all cache lines corresponding to one clock are invalidated. Lose.

Thereafter, when the TLB miss processing is completed, the operation for determining the cache hit for the re-entered virtual address VA [63:13] (VA [12: 5]) is performed again. do.

On the contrary, when the TBI hit signal TLBhit is output as '1' at the OR gate 216 and becomes a TBI hit, the 64 hit signals AHIT from the virtual address tag 211 are directly transmitted to the word line. The received PPI memory 212 outputs a 51-bit physical address (MPPN) in the corresponding area.

When a TBI hit occurs, the encoder 217 encodes 64 hit signals AHIT in the virtual address tag 211 to indicate a 6-bit index indicating a storage location of the virtual address tag 211. The signal is converted to EIND.

At this time, since the cache index tag 213 has already output the index signal CIND indicating the storage location of the virtual address tag 211 in the region designated by the virtual address VA [12: 5], the comparator 214 may use the above. The index signal CIND and the index signal EIND of the encoder 217 are compared with each other, and the hit signal CHIT is output according to the comparison result.

Accordingly, when the hit signal CHIT is output as '0' in the comparator 214 and a cache miss occurs, the cache line is output from the external memory using the physical address MPPN output from the PPI memory 212. After retrieving, the operation is repeated by re-inputting the virtual addresses VA [63:13] and VA [12: 5].

On the contrary, when the hit signal CHIT is output as '1' in the comparator 214 and a cache hit occurs, the cache data memory designated by the virtual address VA [12: 5] when the load is a load ( The cache data (CDATA) output in the corresponding area of 215 is valid data and is transmitted to the place where the data is requested. ]) Is stored in the corresponding area of the cache data memory 215.

As described in detail above, in order to make an 8K-byte cache under the assumed conditions, a cache tag made of SRAM having a size of 51 bits * 256 is conventionally required.

The present invention can be implemented by a cam (CAM) of 6 bits * 256 size by storing the index data indicating the storage location of the virtual address tag in the cache index tag has an effect that can be implemented in a much smaller size than the prior art.

In addition, although the CAM is approximately 2.5 times larger than the static RAM, the overall cache index tag is 1/3 smaller than the conventional cache tag, thereby reducing power consumption due to the reduction of the integrated area. There is also an expected effect.

In addition, although the virtual address tag 111, the PPI memory 112, and the 51-bit comparator 114 are sequentially accessed in order to determine a cache hit, the present invention provides a virtual address tag (a shared TLB tag). 211), the encoder 217 and the 6 bit comparator 214 are accessed in turn, the operation of the encoder 217 is faster than accessing the PPI (PPN) memory 112 and the 6 bit comparator 214 is 51 bits. Since it is faster than the comparator 114, the present invention has the effect of having a faster processing speed than the prior art as a whole.

In the present invention, the cache miss rate is slightly higher than that of the prior art because the cache line in the page indicated by the entry is invalidated due to the occurrence of the TIB entry, but the difference is negligible to less than 0.1%. CAM) invalidates the cache lines within one clock, thereby minimizing performance degradation.

Claims (3)

A microprocessor configured to have a virtual address tag of TLB share a tag of a cache, and outputs a 64-bit hit signal AHIT by comparing the virtual address VA [63:13] with an address stored therein. A virtual address tag, a 64-bit hit signal (AHIT) directly from the virtual address tag, and a PPI memory for outputting a 51-bit physical address (MPPN) in the designated area; The encoder converts the 64-bit hit signal AHIT from the virtual address tag into index data EIND representing an area accessed from the virtual address tag when the TBI hit is made, and the virtual address VA [12: 5)) a cache index tag for outputting 6-bit index data (CIND) for the storage area of the virtual address tag in the area designated by the A comparator for comparing the output signal EIND of the coder with the output signal CIND of the cache index tag, and outputting a cache hit if it matches and a signal CHIT indicating a cache miss if it does not match; A cache hit determination circuit of a microprocessor, characterized in that the cache data memory is configured to read cache data in an area designated by a virtual address (VA [12: 5]) or write external cache data to the area when a hit occurs. . The microprocessor of claim 1, wherein the cache index tag is configured as a content addressable memory (CAM) to invalidate a cache line that uses a TLB entry that is replaced when a TLB miss occurs. Cache hit determination circuit. 3. The cache hit determination circuit of claim 2, wherein invalidating the cache line is performed within one clock.