KR100269426B1 - Motion compensator having an improved frame memory - Google Patents

Abstract

PURPOSE: A motion compensation device with an improved frame memory is provided to improve the efficiency of motion compensation by changing a structure of a frame memory. CONSTITUTION: The first and the second frame areas(41,43) are used as a reference image for motion compensation and stores recovered I picture data or compensated P picture data. The third frame storage area(45) stores and displays compensated B picture data. The fourth frame storage area(47) stores a coded bit stream received from a video decoding device in predetermined units. Each picture data stored in the first, the second, and the third frame storage areas(41,43,45) is read according to a predetermined display order.

Description

Motion Compensator with Improved Frame Memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion compensation device, and more particularly, to a frame memory used for performing motion compensation or displaying motion compensated image data in a video decoder and a motion compensation device using the same. It is about.

In general, in order to transmit a high definition television (HDTV) signal to a channel having a limited bandwidth, band compression of an image signal should be performed. In this case, a moving picture expert group (MPEG) -2 image encoding algorithm is used. In the MPEG-2 image coding algorithm, first, since there is a high correlation between adjacent pixels in the screen, a discrete cosine transform (DCT) and quantization are performed on a block basis to reduce spatial redundancy. In addition, since the correlation between two screens that are adjacent in time is high, the temporal redundancy is reduced by estimating and compensating the motion between the two screens in macroblock units. This reduces statistical redundancy.

Among these, in the motion estimation and compensation process, a neighboring image is compared with a current image to detect a motion vector, which is information about an object's motion, and the current image is predicted using the motion vector. Generally, a block matching algorithm (weak BMA) or a pixel recursive algorithm (weak PRA) is used to detect a motion vector. Here, the PRA method is superior to the BMA method in terms of data reduction capability, but in terms of system complexity, the BMA method that is processed in units of blocks is much simpler than the PRA method that is processed in units of pixels. 261, H.262, MPEG-1, MPEG-2, etc.) also adopt this BMA method.

Meanwhile, in the MPEG-2 video encoding algorithm, there are three types of pictures I, P, and B according to the motion compensation method as shown in FIG. 1, and I, P, and I according to the period of the I picture that can be randomly accessed. B is grouped to form one group of pictures (hereinafter referred to as GOP). Here, the I picture performs only intraframe coding without performing motion compensation, the P picture performs forward motion compensation on the basis of the I picture or P picture of the previous picture with respect to the current picture, and the B picture Selects the best motion compensation block obtained by performing forward motion compensation, backward motion compensation, and interpolated motion compensation based on the I picture or P picture of the previous picture and the I picture or P picture of the next picture. do.

Methods for motion estimation and compensation include frame motion estimation and compensation mode, field motion estimation and compensation mode, dual prime motion estimation and compensation mode, and basically all motion estimation and compensation are half pixel. It is specified to have a half-pel unit.

Among these, frame motion estimation and compensation mode has been used since MPEG-1, and motion estimation and compensation are performed in a frame structure without distinguishing a top field or even field and a bottom field or odd field. do. To this end, a full search is performed on the macroblock MB to be encoded of the current frame up to half-pixel precision in the search region of the reference frame, thereby obtaining the smallest mean absolute error (MAE). The position to generate is determined as a motion vector for the macroblock. In fact, since data is given in units of pixels, a pixel-by-pixel motion vector is obtained through the first-order full search in pixel units, and then a half-pixel motion vector is obtained through interpolation and a second full search in half-pixel units. In the case of frame motion estimation, one motion vector is transmitted per one macroblock for a P picture, and one or two motion vectors are transmitted per one macroblock for a B picture. The number of bits required for transmission is small.

Next, the field motion estimation and compensation mode performs motion estimation and compensation for each field in the picture of the frame structure. For this purpose, the upper and lower, upper and upper, lower and upper, lower and lower positions in the unit of 16 * 8 (pixels) sub macroblocks between upper and lower fields of the current frame and upper and lower fields of the reference frame, respectively. After four motion vectors are obtained, one motion vector is generated to generate a minimum motion compensation error for each of the upper and lower fields of the current frame. Therefore, two motion vectors per macroblock for a P picture and two or four motion vectors per macroblock for a B picture are transmitted. The MPEG-2 image encoder applies all the frame / field prediction modes to all macroblocks, and then uses the prediction mode having the smaller prediction error. Meanwhile, since the prediction mode used by the encoder is transmitted in the MPEG-2 image decoder, motion compensation is performed to restore the image.

Next, the dual prime motion estimation and compensation mode transmits only one motion vector and differential motion vector (dmv) per macroblock, and is known to be effective for sequences with relatively slow motion. This mode is specified to be used only when the B picture is not used. That is, when the B picture is allowed, a better picture quality can be obtained using the B picture. However, when the B picture is not allowed, the dual prime prediction mode can be used to improve the picture quality with as little bit generation as possible. . In the dual prime prediction mode, first, the motion vectors of the upper, upper, and lower part of the four motion vectors obtained from the field prediction mode from upper to lower, upper to upper, lower to upper, lower to lower are used as the basic motion vectors. The upper and lower motion vectors and upper and lower motion vectors are scaled (* 2, * 2/3) and truncated, respectively, to form a basic motion vector. Next, each of the four basic motion vectors thus created is fine-tuned by -1, 0, and 1 in the horizontal and vertical directions to minimize the motion compensation error for the two 16 * 8 (pixels) sub macroblocks. A motion vector and a differential motion vector are transmitted. Since the dual prime prediction mode has a large amount of computation in the image encoder, it is necessary to calculate nine prediction candidate values per one basic motion vector. Therefore, the basic motion vector and the differential motion vector of one of 36 candidates must be calculated. Meanwhile, the image decoder can be implemented relatively simply because only two field motion vectors need to be calculated from the transmitted basic motion vector and the differential motion vector.

A schematic configuration of a general MPEG-2 image decoder for decoding a bitstream encoded by the MPEG-2 image encoding algorithm as described above is shown in FIG. 2. The video decoder of FIG. 2 is largely comprised of a decoder 21, a motion compensator 23, and a selector 25.

Referring to FIG. 2, the variable length decoder 21a performs demultiplexing and variable length decoding on a bitstream buffered and output from a bit buffer (not shown), such as a frame shape, a quantization result, and motion compensation information. Outputs encoded data indicating. Here, the motion compensation information includes a motion vector and data indicating the type of motion compensation.

First, when encoded data indicating the shape of a frame indicates an intra frame I, the variable-length decoded quantization result is applied to the inverse quantizer 21b, where inverse quantization is performed to perform discrete cosine transform (DCT) coefficients. Is restored. The inverse discrete cosine transformer 21c performs inverse discrete cosine transform on the restored discrete cosine transform coefficients to restore the pixel value. At this time, since the encoded data indicating the intra frame I is supplied as the selection control signal of the selecting section 25, the selecting section 25 selects the output of the inverse discrete cosine converter 21c. Therefore, the reconstructed image data output from the inverse discrete cosine converter 21c is output to an external display device (not shown) and stored in an area corresponding to a predetermined address in the first frame memory 23a.

Next, a description will be given of the case where the encoded data indicating the shape of the frame indicates the prediction frame P. FIG. First, the reconstructed image data stored in the first frame memory 23a is transferred to an area corresponding to a predetermined address in the second frame memory 23b. Inverse quantization and inverse discrete cosine transform are performed on the variable-length decoded quantization result to recover the prediction error. The reconstructed prediction error is supplied to the adder 23g and the selector 25. Meanwhile, when the motion vector output from the variable length decoder 21a is applied to the forward motion compensator 23c, the forward motion compensator 23c generates a motion compensation block from the second frame memory 23b and selects the selector ( 23f). At this time, since the encoded data indicating the prediction frame P is supplied as the selection control signal of the selector 23f, the output of the forward motion compensator 23c is constantly supplied to the adder 23g during the prediction frame decoding process.

The adder 23g adds the prediction error reconstructed from the motion compensation block and the inverse discrete cosine transformer 21c and supplies it to the selection unit 25. At this time, since the coded data indicating the prediction frame P is supplied as the selection control signal of the selecting section 25, the selecting section 25 selects the output of the adder 23g. Therefore, the reconstructed image data output from the adder 23g is output to an external display device (not shown) and stored in an area corresponding to a predetermined address in the first frame memory 23a.

Next, a description will be given of the case where coded data indicating a frame shape indicates an interpolation frame B. FIG. First, inverse quantization and inverse discrete cosine transform are performed on the variable-length decoded quantization result to recover the prediction error. The reconstructed prediction error is supplied to the adder 23g and the selector 25. On the other hand, the motion vector output from the variable length decoder 21a is supplied to the forward motion compensator 23c, the reverse motion compensator 23d, and the interpolated motion compensator 23e. Then, each motion compensator 23c to 23e generates a motion compensation block based on the reconstructed image data stored in the first and second frame memories 23a and 23b and supplies it to the selector 23f. The selector 23f selects one of the outputs of the motion compensators 23c to 23e according to the motion compensation form of the corresponding block, and supplies it to the adder 23g.

The adder 23g adds the prediction error reconstructed from the motion compensation block and the inverse discrete cosine transformer 21c and supplies it to the selection unit 25. At this time, since the coded data indicating the interpolation frame B is supplied as the selection control signal of the selecting section 25, the selecting section 25 selects the output of the adder 23g to an external display device (not shown). Is output.

The prior art related to the image decoder using the motion compensation as described above is mentioned schematically or partially in US Pat. Nos. 5,315,388, 5,337,086 and 5,353,062.

However, the order in which the image data reconstructed by the image decoder is displayed on the screen (this is called a display order) is shown in FIG. 1 as follows: I, B, B, P, B, B, P, B, B, .. , I, B, .., the order of decoding by the image decoder (referred to as decoding order), that is, the order of reconstructed image data output from the selector 25 is I, P, B, B, P. , B, B, P, B, ..., I, P, ... In order to solve such a mismatch between the display order and the decoding order, a conventionally provided video frame memory is provided to store reconstructed image data output from the selection unit 25, and then read and output the display image data according to the display order. . However, since the video frame memory must have a capacity to store at least three frames of image data according to the I picture and the P picture or the distance M between the P picture and the P picture, the price is high, and thus, the entire image decoder. In addition to increasing the price of, there is a problem that the delay time from the completion of decoding to increase the display.

As another method for resolving a mismatch between the display order and the decoding order, a frame buffer for delaying the B picture image data output from the selector 25 by a predetermined frame in accordance with M is provided separately. The reconstructed image data is read from the first and second frame memories 23a and 23b and the frame buffer (not shown). However, the timing control is complicated because the first and second frame memories 23a and 23b need to perform data read for motion compensation and data read for display.

Accordingly, the present invention has been made to solve the above-described problems, and in the image decoder, an area for storing image data for reference during motion compensation, an area for storing decoded image data for display, and image decoding It is an object of the present invention to provide a frame memory in which an area for storing a coded bitstream that is previously input is implemented on one memory module.

Another object of the present invention is to provide a motion compensation device using the frame memory.

In order to achieve the above object, the frame memory according to the present invention is an image decoder,

First and second frame storage regions for storing reconstructed I-picture or motion-compensated P-picture image data for display as well as being used as a reference image for motion compensation;

A third frame storage area for storing the motion compensated B picture image data for display; And

And a fourth frame storage area for storing the encoded bitstream input to the image decoder in predetermined bit units.

Each picture image data stored in the first to third frame storage areas is read according to a predetermined display order.

The motion compensation device according to the present invention to achieve the other object

A motion compensation controller configured to receive a motion vector and various flags, generate a plurality of motion compensation control signals for controlling a motion compensation process, and adjust a timing of the motion compensation process;

A memory controller configured to receive a motion vector and various flags and generate a read / write address signal and a memory control signal;

The reconstructed image data write operation, the data read operation for motion compensation, and the data read operation for display are controlled by the memory controller and used as a reference image for motion compensation, and at the same time for display, the reconstructed I picture or First and second frame storage areas for storing motion compensated P picture image data, a third frame storage area for storing motion compensated B picture image data for display, and an encoded bitstream input to the image decoder. A frame memory comprising a fourth frame storage area for storing a predetermined bit unit;

A bus controller which outputs a bus control signal;

Transmitting image data read from the frame memory for motion compensation or display, motion compensated image data for writing to the frame memory, and image data read from the frame memory for display in accordance with the bus control signal. Common bus; And

And a motion compensation unit configured to perform motion compensation on the image data supplied from the frame memory and the inverse discrete cosine transformed image data through the common bus according to the motion compensation control signal.

1 shows an example of a frame arrangement;

2 is a block diagram showing a schematic configuration of a typical MPEG-2 video decoder;

3 is a block diagram showing a motion compensation apparatus employing a frame memory according to the present invention in an image decoder;

4 is a view showing a RAS box setting method for one frame adopted in the present invention,

5 is a diagram showing the structure of a frame memory according to the present invention;

FIG. 6 is a diagram illustrating an SDRAM array for forming the first to fourth frame storage regions shown in FIG. 5;

FIG. 7 is a diagram illustrating time allocated to read and write operations in the frame memory of FIG. 5 for one macroblock; FIG.

8 is a diagram illustrating a scheduling process of first to third frame storage areas according to a decoding order and a display order.

* Explanation of symbols for main parts of the drawings

100: motion compensation control unit 200: memory control unit

300: frame memory 400: bus control unit

500: common bus 600: motion compensation unit

41 to 47: first to fourth frame storage areas 41a to 41f: first frame storage areas

43a ~ 43f: Second frame storage area 45a ~ 45f: Third frame storage area

47a ~ 47f: 4th frame storage area 51: address bus

53: Command Bus 55,55a ~ 55f: Data Bus

300a ~ 300f: SDRAM 1 ~ SDRAM 6

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 is a block diagram illustrating a motion compensator employing a frame memory according to the present invention in an image decoder. The motion compensator 33 includes a motion compensation controller 100, a memory controller 200, a frame memory 300, The bus controller 400 includes a common bus 500 and a motion compensator 600.

The motion compensation control unit 100 receives the motion vector mv and various flags from the variable length decoder 21 (see FIG. 2A), generates motion compensation control signals for controlling the motion compensation process, and generates a motion. Control the overall timing of the compensation process. In this case, the flag is information for motion compensation, and a signal (“decoded_pels”) indicating whether the data input to the image decoder is valid data, and the picture input to the image decoder includes any of an I picture, a P picture, and a B picture. A signal indicating whether the picture corresponds to a picture ("picture_coding_type"), a signal indicating whether the picture structure corresponds to an upper field, a lower field, or a frame picture ("picture_structure"), or a signal indicating a prediction mode in the image encoder ("mc_type"). "), A signal (" dct_type ") indicating a discrete cosine transform mode in the video encoder.

The memory controller 200 receives a motion vector mv and various flags from a variable length decoder 21 (see FIG. 2A) and generates write / read address signals and memory control signals.

The frame memory 300 controls the restored image data writing operation, the data reading operation for the motion compensation, and the data reading operation for the display by the memory controller 200, and has a capacity for storing four frames of pixel data. Have The frame memory 300 will be described in more detail with reference to FIGS. 4 to 6 as follows.

Referring to FIG. 4, in the present invention, one frame (1,920 pixels * 1,088 pixel standard is taken as an example) is divided into 1,020 (that is, 30 * 34) RAS (Row Address Strobe) boxes. That is, the number of the RAS box is the row address (RA) of the frame memory 300. Here, one RAS box is composed of eight macro blocks (MB0 to MB7), each macro block is composed of four Y blocks, one Cr block, and one Cb block, and each block is composed of eight boxes (boxes). It consists of There are eight pixel data in each box constituting the Y block, two pixel data in each box constituting the Cr block, and two pixel data in each box constituting the Cb block. The column address CA of the frame memory 300 is determined by the number of macroblocks constituting the RAS box selected by the row address, the number of blocks constituting the macroblock, and the number of boxes constituting the block. Is determined. In addition, the pixel address (pel address: PA) in the box is used to obtain a reference point (R.P) of the predicted macroblock.

If the reference point (RP) of the predicted macroblock is in the diagonally hatched area, that is, MB3 to MB7, the row address, or RAS box, must be changed to read all the pixel data of the macroblock. . When the RAS box is set up in the same manner as in FIG. 4, even in the worst case, one block of the four blocks constituting the macroblock does not need to change the RAS box in order to read all the pixel data of the macroblock. Therefore, the time required to fetch data from the frame memory 300 can be reduced. Here, the worst case refers to a case in which the reference point of the predicted macroblock is located inside MB7.

Meanwhile, referring to FIG. 5, the frame memory 300 has two memory banks, bank 1 and bank 2, bank 1 includes first and second frame storage regions 41 and 43, and bank 2 includes a second memory bank. There are three and fourth frame storage areas 45 and 47. Here, the first to fourth frame storage areas 41, 43, 45, and 47 each have a capacity to store one frame of pixel data, and the first to fourth frame storage areas 41, 43, 45, 47 each has 1,024 row addresses, and has a column address of 256 words (where 1 word is 8 bits). One address stores eight Y pixels, two Cr pixels, two Cb pixels, and a total of 12 pixel data. Here, 1,024 row addresses mean the RAS box number described above, and thus 4 row addresses remain. The column address of 256 words is derived by 8 macroblocks per one RAS box * 32 pixels per macroblock (= 256 pixels). Here, the first and second frame storage areas 41 and 43 are used to store reconstructed I-picture or motion-compensated P-picture image data for use as a reference image for motion compensation and to simultaneously display the third frame. The storage area 45 is used to store the motion compensated B-picture image data, and the fourth frame storage area 47 is used to store the coded bitstream input to the image decoder in predetermined bit units.

Meanwhile, when the image format is 4: 2: 0, the frame memory 300 may be implemented with six memories, for example, Synchronous-DRAM: 300a to 300f, as shown in FIG. 6. The SDRAMs 300a to 300f are divided into first to fourth subframe storage areas 41a to 41f, 43a to 43f, 45a to 45f, and 47a to 47f, respectively. Among them, the SDRAMs 300a to 300d each have luminance (Y) pixel data corresponding to one 8 * 8 block, and the SDRAM 300e receives color difference (Cr) pixel data corresponding to one 8 * 8 block. The SDRAM 300f stores color difference (Cb) pixel data corresponding to one 8 * 8 block. On the other hand, each of the SDRAMs 300a to 300f has a capacity of 16 Mbits and a data width of 16 bits. Since one pixel data pel corresponds to 8 bits, two pixel data may be output from one SDRAM through the data bus 55 during one fetch. That is, each pixel is loaded onto the common bus 500 in units of 12 pixels (96 bits) from each of the SDRAMs 300a to 300f in one fetch. In other words, two pixels are stored in each of the eight Y pixel data constituting one box in the SDRAMs 300a to 300d, and two pixels of Cr pixel data corresponding to the eight Y pixel data are stored in the SDRAM 300e. Each Cb pixel data corresponding to the eight Y pixel data is stored in two pixels in the SDRAM 300f. That is, in the SDRAMs 300a to 300f, 256 pixels (8 MB * 32 pels) are stored in one row address (RAS box). In this case, it is assumed that the luminance component Y and the color difference components Cr and Cb of the pixel data are stored in an area corresponding to the same address. As shown in FIG. 6, the address bus 51 and the instruction bus 53 are replaced with each other. Can share Here, SDRAM is taken as an example, and can be easily transformed into other asynchronous memory.

3, the bus controller 400 outputs a bus control signal for controlling the common bus 500.

The common bus 500 writes the motion compensated pixel data output from the motion compensator 600 to the frame memory 300 under the control of the bus controller 400, or the reference pixel data to be used in the motion compensator 600. Is provided as a transmission path for reading motion-compensated pixel data from the frame memory 300 to read from the frame memory 300 or to send it to another functional block such as a display device (not shown). In other words, the common bus 500 may include data between the frame memory 300, the motion compensator 600, the frame memory 300, a display device (not shown), the frame memory 300, and a bit buffer (not shown). It is responsible for the transmission, and the size of data to be transmitted is 12 pixels (pel), that is, 96-bit units. For one macroblock, the control timing of the common bus 500 by the bus controller 400 will be described with reference to FIG. 7 as follows.

In FIG. 7, "MC" is a phase for reading a reference frame picture from a corresponding area among the first to third frame storage areas 41, 43, and 45 of the frame memory 300 and inputting the reference frame picture to the motion compensator 600. "D" is a phase in which data used for display is read from a corresponding area among the first to third frame storage areas 41, 43, and 45 of the frame memory 300 and transmitted to a preprocessor (not shown). , "BBR" is a phase for reading data from the bit buffer area of the frame memory 300, that is, the fourth frame storage area 47, and inputting the data to the bit buffer (not shown), and "BBW" is a bit buffer (not shown). ) Is a phase for reading various additional information from the second frame storage area 47 of the frame memory 300 in a predetermined bit unit, and " W " The first to third frame storage areas 41, 43, and 45 of the memory 300 are stored in the corresponding area. Phase. In other words, in view of the frame memory 300, the read operation corresponds to the "MC", "D" and "BBR" phases, and the write operation corresponds to the "W" and "BBW" phases. For example, when a time unit allocated to one macroblock processing on the common bus 500 in the frame memory 300 is '202', an allocation example for each phase is "110". D "can be assigned as" 40 "," BBR "as" 16 "," BBW "as" 4 ", and" W "as" 32 ".

The motion compensator 600 controls the motion compensation controller 100 from a corresponding one of the first to third frame storage areas 41, 43, and 45 of the frame memory 300 through the common bus 500. After performing half-pixel compensation on the output pixel data, motion compensated pixel data is generated by adding pixel data output from an inverse discrete cosine converter (see FIG. 2: 21c). The motion compensated pixel data is stored in a corresponding one of the first to third frame storage areas 41, 43, and 45 of the frame memory 300 in units of 96 bits.

Subsequently, the decoding order in the video decoder shown in FIG. 2 is I, P, B, B, P, B, B, P, B, B, P, B, B, I, P, B, B, If the display order is I, B, B, P, B, B, P, B, B, P, B, B, P, I, B, B, and the display latency is two frames, The operation of the embodiment of the motion compensation device using the frame memory will be described in more detail as follows.

1) When I picture is input

The I picture data input to the image decoder is sequentially subjected to variable length decoding, inverse quantization, and inverse discrete cosine transform, and then the motion compensation unit 600 performs a motion compensation process in a predetermined format without performing a motion compensation process. Is put on.

The memory control unit 200 receives a motion vector ("0" because it is an I picture) and various flags from a variable length decoder (see FIG. 2A) and a write address for writing I picture data to the frame memory 300. Outputs a signal and a memory control signal. Then, the I picture data loaded on the common bus 500 is controlled by the bus controller 400, and according to the write address signal and the memory control signal from the memory controller 200, the first picture data in the frame memory 300 is controlled. It is stored in a predetermined area of the frame storage area 41. In this case, the picture structure stored in the frame memory 300 is preferably a field structure and is mounted on the common bus 500 in units of 12 pixels (96 bits). Meanwhile, the second and third frame storage areas 43 and 45 are empty. This situation corresponds to the second frame memory block in FIG.

2) When a P picture is input

When motion vectors and flags for the P picture are input from the variable length decoder (see FIG. 2A) to the motion compensation controller 100 and the memory controller 200, the motion compensation controller 100 may perform various kinds of motion compensation. Control signals (eg, dct_type, mc_type, etc.) are generated and applied to the motion compensator 600. Meanwhile, the memory controller 200 generates and applies the read address signal and the memory control signals to the frame memory 300 according to the motion vector and various flags. Then, the I picture pixel data stored in the region corresponding to the read address in the first frame storage region 41 in the frame memory 300 is read and loaded on the common bus 500 according to the memory control signal.

The I picture pixel data mounted on the common bus 500 is applied to the motion compensator 600 by 12 pixels (96 bits) under the control of the bus controller 400. The motion compensator 600 first adjusts the I picture pixel data output from the frame memory 300 to a data format processed by the motion compensator 600 and then performs half pixel compensation. Next, according to the motion compensation control signals dct_type and mc_type, the half-pixel-compensated I picture pixel data is added to the P picture pixel data inversely discrete cosine transformed by the inverse discrete cosine transformer (see FIG. 2C). Motion compensation is performed on the data. The motion compensated P picture pixel data is loaded on the common bus 500 by 12 pixels (96 bits) under the control of the motion compensation controller 100.

Meanwhile, the memory controller 200 receives a motion vector and various flags from a variable length decoder (see FIG. 2A), and writes a write address signal and a memory for writing motion compensated P picture data to the frame memory 300. Output a control signal. Then, the motion compensated P picture data mounted on the common bus 500 is controlled by the bus controller 400 according to the write address signal and the memory control signal from the memory controller 200. It is stored in a predetermined area of the second frame storage area 43. At this time, the third frame storage area 45 is empty. This situation corresponds to the third frame memory block in FIG.

3) When B picture is input

When motion vectors and flags for a B picture are input from the variable length decoder (see FIG. 2A) to the motion compensation controller 100 and the memory controller 200, the motion compensation controller 100 may perform various kinds of motion compensation. Control signals (eg, dct_type, mc_type, etc.) are generated and applied to the motion compensator 600.

The memory controller 200 generates read address signals and memory control signals for forward motion compensation according to the motion vector and various flags, and applies them to the frame memory 300. Then, the I picture pixel data stored in the region corresponding to the read address in the first frame storage region 41 in the frame memory 300 is read and loaded on the common bus 500 according to the memory control signal. The I picture pixel data mounted on the common bus 500 is applied to the motion compensator 600 by 12 pixels (96 bits) under the control of the bus controller 400. The motion compensator 600 adjusts the I picture pixel data output from the frame memory 300 to a data format processed by the motion compensator 600, and then performs half-pixel compensation to temporarily perform an internal buffer (not shown). Save as.

Next, the memory controller 200 generates the read address signal and the memory control signals for the backward motion compensation according to the motion vector and various flags, and applies them to the frame memory 300. Then, according to the memory control signal, the P picture pixel data stored in the region corresponding to the read address in the second frame storage region 43 in the frame memory 300 is read and loaded on the common bus 500. The P picture pixel data mounted on the common bus 500 is applied to the motion compensator 600 by 12 pixels (96 bits) under the control of the bus controller 400. The motion compensator 600 adjusts the P picture pixel data output from the frame memory 300 to a data format processed by the motion compensator 600, and then performs half-pixel compensation to temporarily store an internal buffer (not shown). Save as.

In addition, for bidirectional motion compensation, an average value of half-pixel compensated I picture pixel data and P picture pixel data is also temporarily stored in an internal buffer (not shown).

Next, the half pixel compensated I picture pixel data and the half pixel compensated P picture according to the motion compensation control signal mc_type for which one of the forward, reverse, and bidirectional motion compensation from the motion compensation controller 100 is selected. One of the pixel data, the average value of half-pixel compensated I picture pixel data and P picture pixel data is selected. The selected pixel data is combined with inverse discrete cosine transformed B picture pixel data in an inverse discrete cosine transformer (see FIG. 2C) to thereby perform motion compensation on the B picture pixel data. The motion compensated B picture pixel data is loaded on the common bus 500 by 12 pixels (96 bits) under the control of the motion compensation controller 100.

Meanwhile, the memory controller 200 receives a motion vector and various flags from a variable length decoder (see FIG. 2A) and writes a write address signal and a memory for writing motion compensated B picture data to the frame memory 300. Output a control signal. Then, the motion compensated B picture pixel data loaded on the common bus 500 is controlled by the bus controller 400 according to the write address signal and the memory control signal from the memory controller 200. In the third frame storage area 45. Meanwhile, the I picture pixel data stored in the first frame storage area 41 is loaded on the common bus 500 by 12 pixels (96 bits) under the control of the memory controller 200, and the Under control, it is output to a display device (not shown) for display in that phase. This situation corresponds to the fourth frame memory block in FIG.

Steps 1) to 3) are repeatedly performed according to the decoding order. When the P picture is input, the reference pixel data may be an I picture or a P picture according to the decoding order, and when the B picture is input, forward or backward Reference pixel data for motion compensation may be an I picture or a P picture, respectively, in decoding order. Further, the area where each reference pixel data is stored also becomes the first frame storage area 41 or the second frame storage area 43 in the decoding order. 8 illustrates a diagram of the decoding order and the display order. Arrows in FIG. 8 indicate image data referenced for motion compensation, and "D" indicates that image data is being read from the frame memory 300 for display.

On the other hand, the above detailed description is intended to describe particular embodiments presented herein and is not intended to limit the present invention. Those skilled in the art may make various changes and modifications within the technical spirit of the present invention with reference to the above detailed description and drawings.

As described above, according to the present invention, in a motion compensation apparatus, an area for storing image data for reference during motion compensation, an area for storing decoded image data for display, and an encoded bitstream input to an image decoder By adopting a frame memory implemented on one memory module as a region for storing the data, not only the image decoder configuration can be simplified but also the time required for display after the decoding is completed can be shortened.

Claims (19)

In the video decoder, First and second frame storage regions (41, 43) for storing reconstructed I-picture or motion-compensated P-picture image data for use as a reference image for motion compensation and for display; A third frame storage area 45 for storing the motion compensated B picture image data for display; And And a fourth frame storage area 47 for storing the encoded bitstream input to the image decoder in predetermined bit units. Each picture image data stored in the first to third frame storage areas (41, 43, 45) is read out according to a predetermined display order. 2. The frame memory according to claim 1, wherein the first to fourth frame storage areas (41, 43, 45, 47) each have a capacity of one frame. 2. The frame memory according to claim 1, wherein the picture structure stored in the first to third frame storage areas (41, 43, 45) is a field structure. 2. The frame memory according to claim 1, wherein the data writing and reading unit for the first to fourth frame storage areas (41, 43, 45, 47) is 96 bits. The data storage device of claim 1, wherein the first to fourth frame storage areas 41, 43, 45, and 47 each have 1,024 row addresses and 256 word column addresses, and one pixel stores 12 pixel data. Frame memory. The frame memory according to claim 1, wherein one frame picture stored in the first to third frame storage areas (41, 43, 45) comprises a plurality of RAS boxes composed of 4 * 2 macroblocks. In the video decoder, First and second subframe storage areas 41a to 41d and 43a to 43d for storing reconstructed I-picture or motion-compensated P-picture image data for use as a reference image for motion compensation and for display. Third subframe storage areas 45a to 45d for storing the compensated B picture image data for display, and a fourth subframe storage area 47a for storing the coded bitstream input to the image decoder in units of predetermined bits. First to fourth SDRAMs 300a to 300d each configured to ˜47 d) and storing Y pixel data; First and second subframe storage areas 41e and 43e for storing reconstructed I-picture or motion-compensated P-picture image data for use as a reference image for motion compensation and for display, and motion-compensated B-picture. A third subframe storage area 45e for storing the image data for display and a fourth subframe storage area 47e for storing the encoded bitstream input to the image decoder in predetermined bit units, and Cr A fifth SDRAM 300e for storing pixel data; And First and second subframe storage areas 41f and 43f for storing reconstructed I pictures or motion compensated P picture image data for display as well as being used as reference images for motion compensation, and motion compensated B pictures. A third subframe storage area 45f for storing image data for display and a fourth subframe storage area 47f for storing the coded bitstream input to the image decoder in predetermined bit units, and Cb And a sixth SDRAM (300f) for storing pixel data. 8. The frame memory according to claim 7, wherein the first to fourth subframe storage areas (41a to 41f, 43a to 43f, 45a to 45f, and 47a to 47f) each have a capacity of one frame. 8. The frame memory of claim 7, wherein the picture structure stored in the first to sixth SDRAMs (300a to 300f) is a field structure. 8. The frame memory of claim 7, wherein the data writing and reading unit for the first to sixth SDRAMs (300a to 300f) is 16 bits. 8. The first and fourth subframe storage areas 41a to 41f, 43a to 43f, 45a to 45f, and 47a to 47f respectively have 1,024 row addresses and 256 word column addresses. Frame memory. 8. The method of claim 7, wherein one frame picture stored in the first to third subframe storage areas 41a to 41f, 43a to 43f, and 45a to 45f is a plurality of RAS boxes configured of 4 * 2 macroblocks. Frame memory, characterized in that made. 13. The frame memory according to claim 7, wherein the first to sixth SDRAMs (300a to 300f) share an address bus and an instruction bus. A motion compensation controller (100) for receiving a motion vector and various flags to generate a plurality of motion compensation control signals for controlling a motion compensation process, and adjusting timing of the motion compensation process; A memory controller 200 which receives a motion vector and various flags and generates a read / write address signal and a memory control signal; The reconstructed image data write operation, the data read operation for motion compensation, and the data read operation for display are controlled by the memory controller 200, and the reconstructed I picture or motion compensated P picture image data is used as a reference image. And a first frame storage area for storing the display, a third frame storage area for storing the motion compensated B-picture image data for display, and an encoded bitstream input to the image decoder. A frame memory 300 having a fourth frame storage area for storing bit by bit; A bus controller 400 for outputting a bus control signal; Image data read from the frame memory 300 for motion compensation or display, motion compensated image data for writing to the frame memory 300, and image data read from the frame memory 300 for display A common bus 500 for transmitting the signal according to the bus control signal; And And a motion compensation unit 600 for performing motion compensation on the image data supplied from the inverse discrete cosine transformed image and the image data supplied from the frame memory 300 through the common bus 500 according to a motion compensation control signal. Motion compensation device, characterized in that. 15. The motion compensating device according to claim 14, wherein the first to fourth frame storage areas (41, 43, 45, 47) in the frame memory (300) each have a capacity of one frame. 15. The motion compensation device according to claim 14, wherein the picture structure stored in the first to third frame storage areas (41, 43, 45) in the frame memory (300) is a field structure. 15. The motion compensating device according to claim 14, wherein the frame memory (300) is implemented with six SDRAMs (300a to 300f). 18. The motion compensation apparatus of claim 17, wherein the six SDRAMs (300a to 300f) share an address bus and a command bus. 18. The motion compensation apparatus of claim 17, wherein data writing and reading operations of the frame memory are performed in units of 96 bits.

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