KR100266989B1 - Apparatus for correcting error in DVD system - Google Patents

Abstract

PURPOSE: An error corrector of a DVD-ROM(Digital Versatile Disk-Read Only Memory) driver is provided to improve reliability of data by correcting data having an error before treating the data when an analog signal is converted into a digital signal. CONSTITUTION: An A/D converter(51) converts analog signals into corresponding digital signals. A PLL(Phase Locked Loop,52) outputs system clocks synchronized with sampling clocks of the A/D converter. An error correction unit(80) corrects error of the digital data from the A/D converter. A synchronization detector(53) detects synchronizing signals from the digital data of the error correction unit. A demodulator(54) demodulates the data of the synchronization detector into original data. An interface(55) converts the demodulated data and the synchronizing signals into signals available for a computer and transfers the data to a host interface. A error corrector of a DVD-ROM driver promotes improvement in reliability of the demodulated data by correcting error depending on system characteristics when the analog signals are converted into digital signals.

Description

Device for correcting error of DVD system {Apparatus for correcting error in DVD system}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to error correction in a digital video disc (DVD) system. In particular, when converting a playback analog signal read from a disc into a digital signal, if there is an error in the converted digital data, the digital signal is processed before processing the digital signal. The present invention relates to an error correcting apparatus of a DVD system which improves data reliability by correcting data in which an error has occurred.

In general, a DVD-ROM driver is a device that processes data (audio and video data) reproduced from a disc and transfers the data to a host computer through a host interface so that the reproduced data is processed.

The system of such a general DVD-ROM driver is as shown in FIG.

As shown in the drawing, the pickup 20 for reading data recorded on the disc 10 and the reproduced analog signal obtained from the pickup 20 are processed and delivered to the digital signal processor 50 at a later stage. At the same time, the analog signal processor 30 generates a servo control signal for pickup servo control from the reproduced signal and transmits the servo control signal to the servo unit 40, and the pickup 20 according to the servo control signal obtained from the analog signal processor 30. The digital signal which converts the analog signal obtained by the servo signal 40 and the analog signal processing part 30 into the corresponding digital signal, demodulates the converted digital signal into original digital data, and outputs it. The processor 50 and the digital signal processed by the digital signal processor 50 are temporarily stored in the buffer RAM 70, and stored at the address requested by the host. The host interface unit 60 which retrieves the data stored in the buffer RAM 70 and transmits the data to the host side, and the host computer 80 which interfaces with the host interface unit 60 to receive and process the reproduced data. ).

In the general DVD-ROM driver configured as described above, when the disc 10 is seated in a normal position, the pickup 20 reads the data recorded on the disc 10.

At this time, the read signal is a sinusoidal analog signal, and the analog signal processor 30 processes the reproduced analog signal and delivers the digital signal to the digital signal processor 50. At the same time, the pickup servo control is performed from the read analog signal. It makes a servo control signal for and delivers it to the servo unit 40.

Then, the servo unit 40 controls the transfer of the pickup 20 according to the transmitted servo control signal, and the digital signal processing unit 50 receives the analog signal obtained from the analog signal processing unit 30 by digital data. And convert the digital data into original data and demodulate the converted digital data to the host interface unit 60. The host interface unit 60 temporarily stores the transferred data in the buffer RAM 70. Done.

Thereafter, if there is a request for data reproduced from the host computer 80, the reproduced data temporarily stored in the buffer RAM 70 is fetched and transmitted to the host computer 80.

As a result, the host computer 80 processes the reproduced data.

Here, the digital signal processing unit 50 converts the reproduced analog signal into a digital signal and demodulates the converted digital data into original data, as shown in FIG.

As shown therein, the analog / digital converter 51 converts the analog signal processed by the analog signal processor 30 into a digital signal, and is synchronized with the sampling clock obtained by the analog / digital converter 51. The PLL 52 which generates a clock, the synchronization detector 53 which detects a synchronization signal from the digital data obtained by the analog / digital converter 51, and the data and the synchronization signal obtained by the synchronization detector 53 are inputted. Demodulation unit 54 for demodulating the data into original data, and an interface for converting the data demodulated by the demodulation unit 54 and the synchronization signal into a signal that can be processed by a computer to the host interface unit 60. It consisted of 55 parts.

The conventional digital signal processor 50 configured as described above first converts an analog signal input from the analog / digital converter 51 into a digital signal according to a sampling clock.

In this case, the PLL 52 generates a clock clock synchronized with the sampling clock and provides the clock clock to each part of the system, and the synchronization detector 53 uses the digital data obtained from the analog / digital converter 51. The synchronization signal is detected.

The demodulator 54 then demodulates the digital data whose synchronization has been detected to the original data, and transmits the demodulated data and the synchronization signal to the interface unit 55. The interface unit 55 demodulates the demodulated data. The synchronous signal is converted into an RS signal that can be processed by a computer and transmitted to the host interface unit 60.

However, such a conventional digital signal processing unit does not include a device for correcting an error included in the converted digital signal, which has a disadvantage in that it does not guarantee the reliability of the processed data during data processing at a later stage.

In addition, in some apparatuses, there are systems having an apparatus for correcting an error of the converted digital data, but the error correction method in such a system rather corrects an error generated by a method of delaying an error signal to the next signal. The adverse effect occurred and the error increased.

Accordingly, the present invention has been proposed to solve the above problems of the conventional digital signal processor,

The present invention is to improve the reliability of the data by correcting the data in error before processing the digital signal if there is an error in the converted digital data when converting the playback analog signal read from the disk into a digital signal It is an object of the present invention to provide an error correction apparatus of a DVD system.

The first embodiment of the error correction apparatus according to the present invention for achieving the above object,

In the error correction apparatus of the digital video disk system,

An error detection unit for detecting error data having a number of consecutive "1" or "0" two or less from digital data through an analog / digital converter for converting a reproduced analog signal into a digital signal;

A level detector for detecting a level of error data detected by the error detector;

A first phase inverter for inverting a phase of data before or after data having an error among data input according to the level detected by the level detector;

First and second delayers configured to sequentially delay data obtained by the first phase inverter at regular intervals;

And a second phase inverter for inverting the phase of the data through the second delay and outputting the data as error corrected data.

The second embodiment of the error correction apparatus according to the present invention for achieving the above object,

In the error correction apparatus of the digital video disk system,

An error detection unit for detecting error data having a number of consecutive "1" or "0" two or less from digital data through an analog / digital converter for converting a reproduced analog signal into a digital signal;

A level detector for detecting a level of error data detected by the error detector;

A third phase inverter for inverting the phase detected by the level detector according to an external selection signal;

A first phase inverter for inverting a phase of data before or after the error data generated according to the output of the third phase inverter;

First and second delayers configured to sequentially delay data obtained by the first phase inverter at regular intervals;

And a second phase inverter for inverting the phase of the data through the second delayer according to the signal output from the third phase inverter and outputting the data as error corrected data.

The third embodiment of the error correction apparatus according to the present invention for achieving the above object,

In the error correction apparatus of the digital video disk system,

A 12T error detector for detecting error data having a maximum number of consecutive "1" or "0" from the converted digital data through the analog-to-digital converter for converting the reproduced analog signal into a digital signal;

A level detector for detecting a level of error data detected by the 12T error detector;

A third phase inverter for inverting the phase detected by the level detector according to an external selection signal;

A first phase inverter for phase inverting the first or last bit of data input according to the output of the third phase inverter;

First to eleventh delay units sequentially delaying data obtained by the first phase inverter at a predetermined period;

And a second phase inverter for inverting the phase of the data through the eleventh delay according to the signal output from the third phase inverter and outputting the data as error corrected data.

1 is a system block diagram of a general digital video disk (DVD) -ROM (ROM) driver;

2 is a detailed configuration diagram of the digital signal processor of FIG. 1;

3 is a block diagram of an error correction apparatus of a DVD system according to the present invention;

4 is a configuration diagram of a first embodiment of the error correction unit of FIG. 3;

5 is a data timing diagram showing an error correction state in the error correction unit of FIG. 3, (a) is a timing diagram of analog input data, and (b) is a timing diagram of digital data obtained by converting analog input data into digital data. (C) is a data diagram showing an error state of digitized data, and (d) is a data diagram in which error corrected data exists.

6 is a configuration diagram of a second embodiment of the error correction unit of FIG. 3;

7 is a configuration diagram of a third embodiment of the error correction unit of FIG.

<Description of the code | symbol about the principal part of drawing>

51: analog / digital conversion unit 53: synchronous detection unit

54: demodulation part 55: interface part

80: error correction unit 81: level detection unit

82: error detector 83, 86: first and second phase inverters

84,85: first and second retarders

Hereinafter, described in detail with reference to the accompanying drawings, preferred embodiments of the present invention.

An error correction apparatus of the DVD system according to the present invention is as shown in FIG.

As shown therein, an analog / digital converter 51 for converting a reproduced analog signal into a corresponding digital signal and a system clock synchronized with a sampling clock obtained by the analog / digital converter 51 are generated. A synchronization signal is detected from the PLL 52, the error correcting unit 80 correcting an error of the digital data converted by the analog / digital converting unit 51, and the digital data obtained by the error correcting unit 80. And a demodulator 54 for demodulating the data obtained by the sync detector 53 into original data, and the data and the sync signal demodulated by the demodulator 54 can be processed by a computer. The interface unit 55 converts the signal into a signal and transmits the signal to the host interface unit 60.

Here, the blocks having the same reference numerals as those of the accompanying drawings in Fig. 2 have the same configuration and the same functions as the blocks in the accompanying drawings in Fig. 2.

In the above, the error correction unit 80, as shown in Figure 4, and the error detection unit 82 for detecting error data of the number of consecutive "1" or "0" from the converted digital data and two or less; A level detector 81 for detecting the level of the input data and the level of the error data detected by the error detector 82 and a phase of the error data input according to the level detected by the level detector 81. A first phase inverter 83 for inverting, first and second delayers 84 and 85 for sequentially delaying data obtained by the first phase inverter 83 at a predetermined period, and the second delay unit And a second phase inverter 86 which inverts the phase of the error data through 85 to output the error corrected data.

In the error correcting apparatus according to the present invention configured as described above, first, the analog / digital converting unit 51 converts the reproduced analog signal as shown in FIG. 5A into digital data as shown in FIG.

The error correction unit 80 then corrects the error data generated from the converted digital data as shown in FIG. 5C and outputs the error corrected data as shown in FIG.

In other words, the reproduced analog signal becomes a sinusoidal analog signal, and when it is digitized, it becomes a digital signal of "1" or "0" type. The digital signal has a rule that the number of consecutive "1" or "0" is at least two and at most ten. If the number of " 0 " or " 1 " of the converted digital signal is two, it is called 3T, three is 4T, ..., ten is 11T. If the number of consecutive " 1 " or " 0 " is two or less, that is, one, it is an obvious error and the error correction unit 80 tries to correct it.

If " 1 " of the converted digital data is one, the signal before and after the signal is " 0 " as shown in Fig. 5C. Thus, the possibility of error exists both before and after.

That is, it is the case that the previous signal is not mixed with the "1" due to noise or the rear signal is mixed with the noise and does not become "1".

In this case, if either side is unilaterally selected and converted to "1", this may increase the error.

Therefore, in the present invention, in consideration of the fact that the operation of the general system depends on the change state ("0"-> "1" or "1"-> "0"), the error data is "1" according to the characteristics of the system. If the back side signal is reversed to make "1", and if the error data is "0", the front side signal is reversed to "0" to correct the generated error.

An error correction apparatus that performs this role is shown in FIG. 4.

That is, the 2T error of which the number of "0" or "1" is 1 is detected from the data input from the error detection part 82, and the level detection part 81 detects the level of the error data detected by the error detection part 82. Is detected.

In addition, the data of the front or rear of the level detected by the first phase inverter 83 is phase-inverted, and the front of the data of which the predetermined time is delayed sequentially through the first and second delayers 84 and 85. Alternatively, the phase of the backward data may be inverted in the second phase inverter 86 to correct an error generated.

6 is another exemplary embodiment of an error correcting unit according to the present invention.

As shown therein, an error detector 82 detects error data having a number of two consecutive "1s" or "0s" from the converted digital data, and the error data detected by the error detector 82. A level detector 81 for detecting a level, a third phase inverter 87 for inverting a phase detected by the level detector 81 according to an external selection signal, and a third phase inverter 87 The first phase inverter 83 inverts the phase of the data before or after the data having an error among the data inputted according to the output, and sequentially delays the data obtained by the first phase inverter 83 at regular intervals. The error correction is performed by inverting the phase of the error data through the second delay unit 85 according to the signals output from the first and second delay units 84 and 85 and the third phase inverter 87. And a second phase inverter 86 for outputting data.

The error correction device configured as described above adds an external selection terminal to correct the error by changing the level of the front and rear signals according to the level of the reverse signal of the error signal in addition to changing the corrected position according to the level of the error signal. Way.

7 is another embodiment of an error correction unit according to the present invention.

As shown therein, the 12T error detector 88 detects error data having a maximum number of consecutive "1" or "0" from the converted digital data, and the 12T error detector 88 detects the error data. A level detector 81 for detecting a level of error data, a third phase inverter 87 for phase reversing the level detected by the level detector 81 according to an external selection signal, and the third phase inverter ( A first phase inverter 83 for inverting the phase of the first or last bit of the data having an error according to the output of 87), and sequentially delaying the data obtained by the first phase inverter 83 at regular intervals. Error corrected data by inverting the phase of the error data through the eleventh delay unit 98 according to the signals output from the first to eleventh delay units 88 to 98 and the third phase inverter 87. It consists of a second phase inverter 86 for outputting.

The error correcting unit configured as described above corrects an error generated by inverting the phase of the first or last bit of 12T and converting it to 11T.

As described above, the present invention has an effect of improving reliability of demodulated data by correcting an error generated when converting a reproduced analog signal into a digital signal according to the characteristics of the system.

Claims (3)

In the error correction apparatus of the digital video disk system, An error detection unit for detecting error data having a number of consecutive "1" or "0" two or less from digital data through an analog / digital converter for converting a reproduced analog signal into a digital signal; A level detector for detecting a level of error data detected by the error detector; A first phase inverter for inverting a phase of data before or after data having an error among data input according to the level detected by the level detector; First and second delayers configured to sequentially delay data obtained by the first phase inverter at regular intervals; And a second phase inverter for inverting the phase of the data through the second delay and outputting the data as error corrected data. In the error correction apparatus of the digital video disk system, An error detection unit for detecting error data having a number of consecutive "1" or "0" two or less from digital data through an analog / digital converter for converting a reproduced analog signal into a digital signal; A level detector for detecting a level of error data detected by the error detector; A third phase inverter for inverting the phase detected by the level detector according to an external selection signal; A first phase inverter for inverting a phase of data before or after the error data generated according to the output of the third phase inverter; First and second delayers configured to sequentially delay data obtained by the first phase inverter at regular intervals; And a second phase inverter for inverting the phase of the data through the second delayer according to the signal output from the third phase inverter and outputting the data as error corrected data. In the error correction apparatus of the digital video disk system, A 12T error detector for detecting error data having a maximum number of consecutive "1" or "0" from the converted digital data through the analog-to-digital converter for converting the reproduced analog signal into a digital signal; A level detector for detecting a level of error data detected by the 12T error detector; A third phase inverter for inverting the phase detected by the level detector according to an external selection signal; A first phase inverter for phase inverting the first or last bit of data input according to the output of the third phase inverter; First to eleventh delay units sequentially delaying data obtained by the first phase inverter at a predetermined period; And a second phase inverter for inverting the phase of the data through the eleventh delay in accordance with the signal output from the third phase inverter and outputting the data as error corrected data.

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