KR100265059B1 - Apparatus for processing frame of swan2 catv system - Google Patents

Abstract

PURPOSE: A frame processor of a SWAN 2 CATV system is provided to perform an ATM cell extracting function, an UTOPIA transmission function, a synchronism and error checking function, and a CPE overhead processing function. CONSTITUTION: A clock generator(10) generates and provides a system synchronous clock to each terminal of a system. A CPE packet-ATM converter(20) processes a CPE packet overhead and an alarm signal from a CPE packet stream of four channels from a subscriber. A controller(40) controls a transmission of an ATM cell according to a far end block error value and a BIP-8 from the CPE packet-ATM converter(20). A DS 3 matching means(50) sends an ATM obtained by the CPE packet-ATM converter(20) to the subscriber as a downward signal. An STS-1 overhead processor(70) processes an STS-1 overhead of the downward signal. An STS-1 matching means(60) sends the downward signal obtained through the DS 3 matching means(50) to the subscriber according to a control signal from the STS-1 overhead processor(70).

Description

Swan 2 Cable System's Frame Processing System

The present invention implements a module for converting a CPE packet transmitted upward from a subscriber in an asynchronous transmission mode (ATM) based SWAN2 cable (CATV) network to a frame suitable for an ATM transmission mode. The Swan2 Cabletive system for smoothly performing the function of extracting the data, the UTOPIA transmission function, the synchronization and error check function, and the CPE overhead processing function required for CPE packet transmission / reception is related to the frame processing apparatus of the system.

More specifically, to provide a conversion module for converting a 61 byte CPE packet having a 1.62 Mbps rate transmitted upward from a subscriber into a frame suitable for an ATM transmission mode in an ATM-based Swan 2 cable (CATV) system. Swan2 CABLE relates to the frame processing apparatus of the system.

In general, SWAN2 system is based on satellite transmission and ATM transmission, and is a comprehensive information and communication network that provides voice service, video and data service through a single line by connecting optical cables.

The network structure of such a general SWAN2 system is shown in FIG. It is composed of a set-top box (1) for accommodating up to 16 subscribers, and a remote terminal (2) for converting the CPE packets transmitted upward from the set-top box (1) into ATM frames and transmitting them in units of ATM cells. In the remote terminal 2, there is a Remote Terminal Interface for Video (RTIV) block 2a for transmitting and receiving data to and from the set-top box 1.

In the SWAN2 incoming network having such a configuration, an uplink signal transmitted from the set-top box 1 on the subscriber side to the remote terminal 2 is a CPE packet (1.62 Mbps) having a size of 61 bytes, and the set-top box on the subscriber side on the remote terminal 2. The downlink signal transmitted to (1) is an STS-1 frame of 51.84 Mbps, and the CPE packet includes 53 bytes of ATM cells.

In this case, the 53-byte ATM cell has a structure as shown in FIG. 2, and the ATM cell is included in the CPE packet. Thus, the remote terminal 2 has the same 53-byte size from the CPE packet transmitted upward. It extracts only ATM cells and transmits them upward through the UTOPIA interface, which is the interface standard between ATM and physical layers, and provides related control and alarm signals such as FEBE (Far End Block Error) and BIP-8 error checking. Will be performed.

However, in the conventional ATM-based SWAN2 CATV network, a data interface between a DS3 matching unit for transmitting and receiving an ATM cell and a commercial chip connected to a subscriber is interfaced with a different interface method.

That is, the DS3 unit interfaces data in the form of ATM cell through the Utopia Level-1 interface. In this case, the CPE packet is interfaced to the commercial chip connected to the subscriber side, so a circuit for converting the data must be added for smooth interface of data. .

In order to realize this, in the related art, a function of converting a CPE packet into a signal suitable for a utopia level-1 interface was designed and used in a commercial chip. Since such a commercial chip is an expensive chip, it has a very unreasonable disadvantage in economics.

Accordingly, the present invention has been proposed to solve the above-mentioned problems in converting the conventional CPE packet into the ATM frame, and an object of the present invention is to provide the SWAN2 based on the asynchronous transmission mode (ATM). Implementing a module that converts CPE packets transmitted upward from subscriber in CATV) network into frames suitable for ATM transmission mode, extracts ATM cell, UTOPIA transmission function, synchronization and error check function, CPE Swan2 Cableive, which facilitates the CPE overhead processing required for packet transmission / reception, provides the system's frame processing.

Technical means for achieving the object of the present invention comprises a clock generating means for generating a plurality of system synchronization clocks and providing them to each end of the system; A CPE packet-to-ATM converter for processing CPE packet overhead and alarm signals from a four-channel CPE packet stream transmitted from a subscriber side in synchronization with a predetermined clock generated by the clock generation means, and extracting and outputting only an ATM cell; Control means for controlling transmission of an ATM cell according to a far end block error (FEBE) value and an even parity check (BIP-8) error coefficient value generated at a predetermined period in the CPE packet to ATM conversion means; Under the control of the control means, the DSPE which delivers the ATM cell obtained from the CPE packet to ATM converting means as an uplink signal to the remote terminal switching unit, and receives the downlink signal switched from the remote terminal switching unit and delivers it to the STS-1 matching unit. It consists of matching means.

1 is a general Swan 2 network structure diagram,

2 is a general CPE packet structure diagram,

3 is a block diagram of a frame processing apparatus of the Swan 2 cable system according to the present invention,

4 is a block diagram showing an embodiment of the CPE packet-ATM cell converter of FIG.

5 is a state transition diagram of a CPE packet according to a counter value in the present invention.

6 is a periodic diagram of a CPE packet,

7 is an input / output timing diagram of each part of FIG.

8 is a signal flow diagram illustrating a CPE packet processing method in the present invention.

* Explanation of symbols for main parts of the drawings

10: clock generator 20: CPE packet-ATM converter

40: control unit 50: DS3 matching unit

60: STS-1 matching part

Hereinafter, described in detail with reference to the accompanying drawings, preferred embodiments of the present invention according to the technical spirit as described above.

3 is a block diagram of a frame processing apparatus of the Swan 2 cable system according to the present invention.

As shown in FIG. 10, a reference numeral 10 denotes a clock generator which generates a plurality of system synchronization clocks and provides them to each end of the system. The reference numeral 20 is synchronized with a predetermined clock generated by the clock generator 10 and transmitted from the subscriber side. A CPE packet-to-ATM converter which processes CPE packet overhead and alarm signals from a four-channel CPE packet stream and extracts and outputs only ATM cells. 40 denotes a FEBE generated at a predetermined cycle by the CPE packet-to-ATM converter 20. The control unit controls the transmission of the ATM cell according to the value and the BIP-8 error count value.

In addition, the reference numeral 50 transfers the ATM cell obtained from the CPE packet-to-ATM converter 20 as an uplink signal to the remote terminal switching unit under the control of the controller 40, and the downlink signal switched from the remote terminal switching unit. Is a DS3 matching unit which is received and transmitted to the STS-1 matching unit 60, and 70 is an STS-1 overhead processing unit which processes the STS-1 overhead included in the downlink signal.

4 is a detailed block diagram of the CPE packet-to-ATM converter 20.

Here, reference numeral 21 denotes synchronization of a transmitted CPE packet stream, FEBE byte latch, internal bit clock and byte clock generation, CPE reset signal generation in CPE packet unit period, enable signal generation for each CPE packet internal data. A CPE packet processing control unit for performing a function, reference numeral 22 is a serial-parallel conversion unit for converting the transmitted serial CPE data into 8-bit parallel data, reference numeral 23 in the serial-parallel conversion unit 22 The synchronous comparison unit checks the synchronization of the CPE packets by comparing the delayed parallel data obtained with preset synchronization detection data to detect synchronization signals.

Reference numeral 24 denotes an FEBE register for latching FEBE bytes from the parallel data obtained by the serial-parallel conversion section 22, and reference numeral 25 checks the parity of the parallel data obtained by the serial-parallel conversion section 22. And a result of comparing the result value with the CPE-OCTET and outputting the result value as a BIP-8 calculation value, wherein reference numeral 26 denotes the serial number according to the ATM enable signal generated by the CPE packet processing controller 21. -An ATM cell accumulator that accumulates only ATM cells of the parallel data obtained by the parallel converter 22.

Further, reference numeral 27 is a BIP-8 register for temporarily storing the BIP-8 error value generated by the BIP-8 calculation unit 25 and then transferring the BIP-8 error value to the microprocessor interface unit 28. Reference numeral 28 is a BIP-8 register. The BIP-8 error value obtained from the eight registers 27 and the FEBE value generated from the FEBE register 24 are transmitted to the controller 40 at regular intervals.

Further, reference numeral 29 denotes an accumulation control unit for controlling data reading of the ATM cell accumulating unit 26 and data recording of the ATM cell first-in-first-out unit according to the BIP-8 calculation value obtained from the BIP-8 calculation unit 25 and the utopia clock. Reference numeral 30 denotes an ATM cell first-in-first-out unit that first-in-first-outs an ATM cell obtained from the ATM cell accumulating unit 26 according to a data recording control signal generated by the accumulation control unit 29.

In addition, reference numeral 31 is a clock generator which provides oscillation clocks generated at a predetermined period in the oscillator 32 to clocks required by the system and provided to each stage of the apparatus, and reference numeral 33 is provided by the clock generator 31. It is a utopia interface unit for transmitting the first-in first-out ATM cell in the first-in first-out unit 30 in synchronization with the system clock.

When described in detail with reference to Figures 3 to 8 attached to the operation of the frame processing apparatus in the system Swan 2 cable according to the present invention configured as described above are as follows.

First, when power is supplied to the system, the clock generator 10 generates a clock required by the system and provides the clock to each end of the system. The CPE packet-ATM converter 20 is synchronized with the system clock to set up a subscriber set-top box. Receives 61 channels of CPE packet data stream (RT02b) transmitted upward from the system, processes CPE packet overhead and alarm signals (FEBE, BIP-8), and extracts only 53 bytes of pure ATM cell, Utopia transmission interface Through the transfer to the DS3 matching unit 50 (RTIV02). In addition, the CPE packet overhead and the alarm signal processing value are transmitted to the controller 40 (RTIV04).

The operation of the CPE packet-ATM conversion unit 20 will now be described in more detail with reference to FIG. 4.

First, the CPE packet processing control unit 21 matches a CPE packet stream transmitted from the subscriber side to detect synchronization, latches FEBE bytes, generates an internal bit clock and a byte clock, and generates a CPE packet in a CPE packet unit period. It generates a set signal and generates an enable signal for each data inside the CPE packet, and the like, where the CPE packet processing controller 21 is not shown in the figure, but the CPE reset signal generator and the clock are largely generated. It is divided into CLK-Gen, 8-counter and enable signal generator (Ena-gen), and the operation of each block is as follows. The CPE reset signal generator generates a reset signal every 61 bytes of CPE packet units. SD (see C in FIG. 7) and DOE (see D in FIG. 7) transmitted from the subscriber side (RTMD) When both are high signals (H), the CPE reset value becomes “H” (see F in Fig. 7), which starts the CPE cycle in the module. In contrast, when one of the DS and DOE values becomes “L”, the CPE reset signal becomes “L” (see G in FIG. 7) to complete one CPE cycle. The clock generator CLK-Gen generates an internal clock required by the reception clock RSCLK (see B of FIG. 7) received from the subscriber side RTMD. When the CPE-Reset signal is “H”, That is, the reception clock RSCLK is valid only during the CPE packet period. In addition, the 8-counter receives a valid receive clock (RSCLK) to generate a byte clock through an octal counter. The enable signal generator (Ena-gen) generates a status signal for a 61-byte CPE packet. 57 counters are operated by receiving the byte clock from the 8-counter, and the enable signals generated during the counter operation are synchronized enable and FEBE enabled as shown in (J) to (N) in FIG. enable, ATM enable, BIP-8 enable, BIP check, and so on. And the state transition for the CPE packet according to each counter value is shown in FIG.

On the other hand, the serial-parallel conversion unit 22 converts the serial CPE data (RSD) (see A in FIG. 7) transmitted from the subscriber side (RTMD) into 8-bit parallel data (CPE-OCTET [0: 7]). The delay is applied by 1/2 clock of the reception clock RSCLK in consideration of the internal timing. That is, the rising edge of the CPE state clock as shown in (E) of FIG. 7 obtained by converting the serial CPE data transmitted from the subscriber side into parallel data synchronized with the reception clock RSCLK and obtained by the CPE packet processing control unit 21. In order to latch data at (↑), CPE data from S2P block is delayed by 1/2 cycle of receiving clock RSCLK and outputted.

The synchronous comparison section 23 is a block for checking whether or not the CPE packet is synchronized, and the rising edge ↑ of the synchronous enable signal SYNC-EN (see J in FIG. 7) obtained by the CPE packet processing control section 21. Reads CPE-OCTET [0: 7]) converted by the serial-to-parallel converter 22 and compares it with a preset value of "0 * 07" to detect synchronization, and output synchronization failure value (SYNC-FAIL). ) Becomes “L” at the beginning of the CPE packet and then “H” at the end of the CPE packet. Even if the synchronization fails after the synchronization comparison, it is asserted as “H”. If the synchronization failure value (SYNC-FAIL) is “L”, the enable clocks for the CPE state do not occur. Here, the cycle of the CPE packet is as shown in FIG.

In addition, the FEBE register 24 latches the FEBE byte in the CPE packet and transmits it to the microprocessor interface unit 28. The rising edge of the FEBE enable signal FEBE-EN obtained by the CPE packet processing control unit 21 is obtained. Read the CPE-OCTET [7: 0] at (↑) and store it in a register, and store the CPE-OCTET [7: 0] stored at the rising edge (↑) of the FEBE-GET in the register at the microprocessor interface unit. Will be sent to (28).

In addition, the BIP-8 calculation unit 25 checks the even parity of the data of the CPE packet at the rising edge (↑) of BIP8-EN as shown in FIG. 7 (M) obtained by the CPE packet processing control unit 21. The range is from the sync byte to the last 53th ATM data, and CPE-OCTET [0: 7] is read at the rising edge (↑) of BIP8-CHK and compared with the result of searching for the even parity. As a result of this comparison, if the BIP-8 value is normal, the BIP8-OK signal as shown in FIG. 7 (P) is generated, and if it is abnormal, the BIP8-ERR signal as shown in FIG. 7 (O) is generated. Here, the BIP8-OK signal is provided to the accumulation control unit 29 so that the accumulated data is transmitted to the ATM cell first-in-first-out unit 30, and the BIP8-ERR signal is provided to the BIP-8 register 27 to provide the BIP-8. 8 Let the error value be counted.

When the BIP-ERR signal is generated from the BIP-8 calculator 25, the BIP-8 register 27 increments the counter value by 1 at the rising edge ↑ every time the BIP-ERR signal is generated. The counter value is transmitted to the microprocessor interface unit 28 at the rising edge ↑ of the BIP-GET. When the transfer of the counter value is completed, the counter value is cleared to "0 * 00".

In addition, the accumulation control unit 29 reads the ATM cell accumulation unit 26 and the ATM cell first-in-first-out unit according to the BIP8-OK signal obtained from the BIP-8 calculation unit 25 and the utopia clock (UTOPIA-CLK; 14.321 MHz). 30. When the BIP8-OK signal is received, the VALID signal is asserted high (H) as shown in (V) of FIG. 7, and the ATM cell accumulates at the rising edge (↑) of the utopia clock. The unit 26 reads the input ATM cell, and controls the ATM cell first-in-first-out unit 30 to write data at the falling edge (↓) of the utopia clock.

In addition, the ATM cell accumulator 26 is a 53-byte memory, which is a rising edge of the ATM enable signal ATM-EN as shown in FIG. 7 (L) obtained by the CPE packet processing control unit 21. (↑) records the digital ATM cell converted by the serial-to-parallel conversion section 22, and reads and outputs the recorded data on the rising edge (↑) of the utopia clock when the VALID signal is high. do.

In addition, the ATM cell first-in-first-out unit 30 is a 53-byte first-in first-out unit, and records data such as (S) of FIG. 7 obtained by the ATM cell accumulating unit 26 at the falling edge (↓) of the VALID. When the first-in first-out data is full, the U-topia interface unit 33 asserts a read-enable signal (Read-enb) as shown in FIG. When the read signal REAB such as (W) of FIG. 7 is asserted in the utopia interface unit 33, data is read at the rising edge ↑ of the utopia clock. In this case, when converting a CPE packet into an ATM frame, four upstream CPE packet streams must be matched. Therefore, ATM cell multiplexing must be performed internally. However, in the present invention, since only one channel of CPE packet stream is accommodated, it is designed as a first-in, first-out of ATM cell size, and the ATM multiplexing block is omitted.

Next, the clock generator 31 divides the 28.624 MHz oscillation clock obtained by the oscillator 32 into two to generate a 14.312 MHz utopia clock (UTOPIA-CLK) required by the system to generate the ATM cell accumulator 26. And the ATM cell first-in first-out unit 30 and the utopia interface unit 33, respectively, the utopia interface unit 33 is a read enable signal transmitted from the ATM cell first-in first-out unit 30 (Read-enb) It is controlled by the Tx-CLAV signal such as (Z) of FIG. 7 coming from the signal and the physical layer, and the ATM cell data obtained from the ATM cell first-in-first-out unit 30 is changed into a format suitable for the utopia interface. Transmission data TxData [7: 0], such as Y), TxSOC, such as (A ') of FIG. 7, transmission enable signal TxEnb, such as (B') of FIG. 7, and (C ′) of FIG. Is transmitted to the DS3 matching unit 50 as described above.

The microprocessor interface unit 28 transfers the FEBE value and the BIP-8 data transmitted from the FEBE register 24 and the BIP-8 register 27 to the controller 40 at a predetermined period, where the BIP-8 is used. The error count value, that is, the BIP-8 register value, is reset to "0 * 00". The access address for the current four channels of the CPE packet stream, that is, the address ADDR [3: 0] is as follows.

In this process, only the ATM cell is extracted from the CPE packet transmitted upward from the subscriber side and transferred to the DS3 matching unit 50 through the utopia interface, and the DS3 matching unit 50 is controlled by the controller 40 to the remote terminal switching unit. It will print the ATM cell. In addition, the downlink signal is switched by the remote terminal switching unit and transferred to the DS3 matching unit 50, and only the data is extracted from the DS3 matching unit 50 and transferred to the STS-1 matching unit 60, STS-1 overhead Is processed by the STS-1 overhead processing unit 70 and transmitted to the STS-1 matching unit 60 as a signal for controlling the STS-1 matching unit 60. Then, the STS-1 matching unit 60 transmits the data to the subscriber side (RTMD).

8 is a schematic diagram illustrating a procedure of converting a CPE packet to an ATM frame according to the present invention. First, in a standby state (ST1), when a CPE packet stream is input, the process proceeds to the CPE processor controller by SD and DOE. ST2) Here, if the synchronization of the CPE packet stream is checked (ST3) and there is no abnormality (ST4), an enable signal that can be transmitted to each block such as FEBE, ATM, and BIP8-CHK is generated (ST6). At the end of the CPE packet stream, BIP8 is checked (ST7), and if there is no error, the data is transmitted to the ATM first-in, first-out (ST8), and the data in the ATM first-in-first-out is output to the DS3 matching unit by utopia transmission control ( ST9) (ST10).

As described above, the present invention enables the ATM frame conversion of the uplink CPE packet data when the ATM-based Swan2 CATV network is constructed, and thus uses the implemented alarm data processing function, utopia interface function, cell multiplexing function, and the like. Various kinds of packet data can be connected to ATM network.

In addition, since the CPE packet can be controlled, an additional service can also be performed using the currently reserved portion.

Claims (3)

An ATM-based Swan2 cable system for transmitting a CPE packet through an ATM network, the system comprising: clock generating means (10) for generating a plurality of system synchronization clocks and providing them to each end of the system; CPE packet-to-ATM conversion means for processing CPE packet overhead and alarm signals from four channel CPE packet streams transmitted from subscribers in synchronization with a predetermined clock generated by the clock generation means 10 and extracting and outputting only ATM cells 20; Control means 40 for controlling the transmission of the ATM cell according to the Far End Block Error (FEBE) value and the BIP-8 (even parity check) error coefficient value generated in the CPE packet-ATM conversion means 20 at a predetermined period and ; Swan 2, characterized in that it comprises a DS3 matching means 50 for transmitting the ATM cell obtained from the CPE packet-ATM conversion means 40 in an uplink signal to the remote terminal switching unit under the control of the control means 40. Cable handling system of frame system. The STS-1 overhead processing means (70) for processing the STS-1 overhead of the downlink signal switched by the remote terminal switching unit, and the STS-1 overhead processing means (70). Swan-2 cable system is characterized in that it further comprises a STS-1 matching means 60 for transmitting a downlink signal obtained through the DS3 matching means 50 to the subscriber side according to the control signal due to the overhead Processing unit. The CPE packet-to-ATM conversion means 20 matches the transmitted CPE packet streams to detect synchronous detection, FEBE byte latch, internal bit clock and byte clock generation, and CPE packet reset cycles. Generation and CPE packet processing control unit 21 for performing an enable signal generation function for each internal data of the CPE packet, and serial-to-parallel conversion unit 22 for converting the transmitted serial CPE data into 8-bit parallel data. And a synchronous comparison section 23 for comparing the delayed parallel data obtained by the serial-to-parallel conversion section 22 with preset synchronous detection data for detecting a synchronous signal to check the synchronization of the CPE packets. The FEBE register 24 latches the FEBE byte from the parallel data obtained by the parallel conversion section 22, and the parity of the parallel data obtained by the serial-to-parallel conversion section 22 and checks the missing values and A BIP-8 calculator 25 for comparing CPE-OCTET and outputting the result as a BIP-8 calculated value, and the serial-to-parallel converter according to the ATM enable signal generated from the CPE packet processing controller 21; 22) an ATM cell accumulator 26 accumulating only ATM cells among parallel data obtained at 22), and a BIP-8 which temporarily stores a BIP-8 error value generated by the BIP-8 calculator 25 and delivers the BIP-8 error value to the microprocessor interface unit. The microprocessor interface unit 28 for transmitting the register 27, the BIP-8 error value obtained from the BIP-8 register 27, and the FEBE value generated from the FEBE register 24 to the control unit 40 at a predetermined period. And an accumulating control unit 29 for controlling the data read of the ATM cell accumulating unit 26 and the data recording of the first-in first-out part according to the BIP-8 calculated value obtained by the BIP-8 calculating unit 25 and the utopia clock. Record data generated by the control unit 29 According to the control signal, the ATM cell first-in-first-out unit 30, which first-in first-outs the ATM cell obtained from the ATM cell accumulator 26, and the oscillation clock generated by the oscillator 32 at a predetermined period as a utopia clock required by the system. Utopia interface unit for transmitting the first-in, first-out first ATM cell in synchronization with the clock generator 31 and the utopia clock provided by the clock generator 31, the device for each stage of the device; Frame processing apparatus of the Swan 2 cable system, characterized in that consisting of (33).

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